WO2008007619A1 - Écran plasma et procédé de pilotage de son panneau d'affichage - Google Patents
Écran plasma et procédé de pilotage de son panneau d'affichage Download PDFInfo
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- WO2008007619A1 WO2008007619A1 PCT/JP2007/063558 JP2007063558W WO2008007619A1 WO 2008007619 A1 WO2008007619 A1 WO 2008007619A1 JP 2007063558 W JP2007063558 W JP 2007063558W WO 2008007619 A1 WO2008007619 A1 WO 2008007619A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/296—Driving circuits for producing the waveforms applied to the driving electrodes
- G09G3/2965—Driving circuits for producing the waveforms applied to the driving electrodes using inductors for energy recovery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J11/00—Gas-filled discharge tubes with alternating current induction of the discharge, e.g. alternating current plasma display panels [AC-PDP]; Gas-filled discharge tubes without any main electrode inside the vessel; Gas-filled discharge tubes with at least one main electrode outside the vessel
- H01J11/20—Constructional details
- H01J11/22—Electrodes, e.g. special shape, material or configuration
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
- G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
Definitions
- the present invention relates to a plasma display device used for a wall-mounted television or a large monitor, and a method of driving a plasma display panel.
- a typical AC surface discharge type panel as a plasma display panel (hereinafter referred to as "panel"), a large number of discharge cells are formed between a front plate and a back plate disposed opposite to each other.
- a front plate a plurality of display electrode pairs consisting of a pair of scan electrodes and sustain electrodes are formed in parallel to each other on the front glass substrate, and a dielectric layer and a protective layer are formed to cover the display electrode pairs.
- the back plate includes a plurality of parallel data electrodes on the back glass substrate, a dielectric layer covering them, and a plurality of partitions on top of the back electrodes, which are parallel to the data electrodes.
- a phosphor layer is formed on the surface and the side surfaces of the partition walls. Then, the front plate and the back plate are arranged to face each other so that the display electrode pair and the data electrode intersect each other in a three-dimensional manner, and sealed.
- a discharge gas containing, for example, 5% xenon in a partial pressure ratio is enclosed in the discharge space inside. It is done.
- a discharge cell is formed in the portion where the display electrode pair and the data electrode face each other. In a panel of such a configuration, ultraviolet light is generated by discharging the gas in each discharge cell, and the ultraviolet light excites the phosphors of red, green and blue colors to perform color display! / !.
- a sub-field method that is, a method of performing gradation display by combining sub-fields which emit light after dividing one field period into a plurality of sub-fields, is generally used. It is.
- Each sub-field has an initialization period, an address period, and a sustain period, and generates an initialization discharge during the initialization period to form wall charges necessary for the subsequent address operation on each electrode.
- an initializing operation for generating an initializing discharge in all discharge cells hereinafter abbreviated as “all cell initializing operation”
- an initializing discharge in a discharge cell having undergone a sustain discharge are generated.
- selection initialization operation There is an initialization operation (hereinafter, abbreviated as “selection initialization operation”).
- address pulse voltage is selectively applied to the discharge cells to be displayed to generate address discharge to form wall charges (hereinafter, this operation is also referred to as “address”).
- sustain pulses are alternately applied to the display electrode pair consisting of the scan electrode and the sustain electrode, sustain discharge is generated in the discharge cell in which the address discharge has occurred, and the phosphor layer of the corresponding discharge cell is illuminated.
- an all-cell initializing operation for discharging all discharge cells is performed in an initialization period of one sub-field among a plurality of sub-fields, and the other sub-field initial stage is performed.
- Patent Document 2 focuses on the fact that each of the display electrode pairs is a capacitive load having an inter-electrode capacitance of the display electrode pair, and uses a resonant circuit including an inductor as a component to set the capacitance between the inductor and the inter-electrode.
- An electric power recovery circuit is disclosed that performs LC resonance, recovers the charge stored in the interelectrode capacitance in a capacitor for recovering electric power, and reuses the recovered charge for driving a display electrode pair.
- the address discharge becomes unstable and the display should be performed. Address discharge did not occur in the discharge cell, and problems such as deterioration of image display quality or increase in voltage required to cause address discharge occurred.
- the voltage applied to the discharge cell at the time of writing is increased to stably generate the address discharge, the discharge cell where the address operation is not performed is affected by the adjacent discharge cell, for example, the wall charge decreases. Then, problems occur such as the writing becoming unstable in the next sub-field.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2000-242224
- Patent Document 2 Japanese Patent Publication No. 7-109542
- a panel provided with a plurality of discharge cells having a display electrode pair consisting of scan electrodes and sustain electrodes, a setup period for generating a setup discharge in the discharge cells, and writing in the discharge cells
- a plurality of subfields each having a writing period for generating a discharge and a sustaining period for causing a sustaining discharge in a discharge cell by marking a sustaining pulse on a display electrode pair are provided in a plurality of field periods, and the rising slope of the sustaining pulse is
- the sustain pulse generation circuit generates at least two types of sustain pulses having different rising slopes, and at the end of the sustain period, the sustain pulse having a steep rise is generated.
- the method is characterized by applying to one electrode of the display electrode pair continuously for at least a number of times.
- FIG. 1 is an exploded perspective view showing a structure of a panel in the embodiment of the present invention.
- FIG. 2 is an electrode array diagram of the same panel.
- FIG. 3 is a schematic diagram of drive waveforms showing a sub-field configuration in the embodiment of the present invention.
- FIG. 4 is a drive voltage waveform diagram applied to each electrode of the panel in the embodiment of the present invention.
- FIG. 5 is a waveform chart schematically showing the first sustaining pulse and the second sustaining pulse in the embodiment of the present invention.
- FIG. 6 is a schematic diagram showing how a first sustaining pulse and a second sustaining pulse are applied to the display electrode pair in the sustaining period of the embodiment of the present invention.
- FIG. 7 is a diagram showing the relationship between the second sustain pulse and the scan pulse voltage in the embodiment of the present invention.
- FIG. 8 is a diagram showing the relationship between the number of applications of the second sustain pulse and the scan pulse voltage in the embodiment of the present invention.
- FIG. 9 is a diagram showing a change in voltage Ve2 when the application condition of the second sustaining pulse in the embodiment of the present invention is changed.
- FIG. 10 is a diagram showing a change in scan pulse voltage when the sub-field to which the second sustain pulse is applied in the embodiment of the present invention is changed.
- FIG. 11 is a circuit block diagram of a drive circuit for driving a panel in the embodiment of the present invention.
- FIG. 12 is a circuit diagram of a sustain pulse generating circuit in the embodiment of the present invention.
- FIG. 13 is a waveform diagram of a first sustain pulse in the embodiment of the present invention.
- FIG. 14 is a waveform diagram of a second sustain pulse in the embodiment of the present invention. Explanation of sign
- FIG. 1 is an exploded perspective view showing the structure of panel 10 in accordance with the exemplary embodiment of the present invention.
- a plurality of display electrode pairs 28 composed of scan electrodes 22 and sustain electrodes 23 are formed on the front plate 21 made of glass.
- a dielectric layer 24 is formed to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24.
- a plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and further, parallel-bar-like partitions 34 are formed thereon. Then, on the side surfaces of the partition walls 34 and on the dielectric layer 33, phosphor layers 35 emitting light of red (R), green (G) and blue (B) are provided.
- the front plate 21 and the back plate 31 are disposed opposite to each other so that the display electrode pair 28 and the data electrode 32 intersect each other across a minute discharge space, and the outer peripheral portion thereof is sealed with a glass frit or the like. Sealed by material.
- a mixed gas of neon and xenon is enclosed as a discharge gas.
- a discharge gas with a xenon partial pressure of about 10% is used to improve luminance.
- the discharge space is divided into a plurality of sections by the barrier ribs 34, and a discharge cell is formed at the intersection of the display electrode pair 28 and the data electrode 32. An image is displayed as the discharge cells discharge and emit light.
- the structure of panel 10 is not limited to that described above, and may have barrier ribs in the form of stripes, for example. Further, the mixing ratio of the discharge gas may not be limited to those described above, and may be other mixing ratios.
- FIG. 2 is an electrode array diagram of panel 10 in accordance with the exemplary embodiment of the present invention.
- n long scan electrodes SCl to SCn (scan electrode 22 in FIG. 1) and n sustain electrodes SUl to SUn (sustain electrodes 23 in FIG. 1) are arranged in the row direction, and Long m data electrodes Dl to Dm (data electrodes 32 in FIG. 1) are arranged.
- the plasma display apparatus uses the sub-field method, that is, one field period is divided into a plurality of sub-fields, and gradation display is performed by controlling the light emission / non-light emission of each discharge cell in each subfield. Do.
- Each sub-field has an initialization period, a write period and a sustain period.
- the initialization operation includes an all-cell initialization operation for generating an initialization discharge in all discharge cells, and a selection for generating an initialization discharge in a discharge cell which has undergone a sustain discharge in the immediately preceding subfield. There is an initialization operation.
- address discharge is selectively generated in the discharge cells to be lit in the subsequent sustain period to form wall charges.
- sustain pulses in a number proportional to the luminance weight are alternately applied to the display electrode pair 28, and sustain discharge is generated in the discharge cell in which the address discharge is generated to emit light.
- the proportional constant at this time is called "brightness ratio".
- FIG. 3 is a schematic diagram of drive waveforms showing a sub-field configuration in the embodiment of the present invention.
- FIG. 3 schematically shows driving waveforms in one field in the sub-field method, and driving voltage waveforms of the respective sub-fields will be described later.
- one field is divided into ten subfields (first SF, second SF, ⁇ , 10th SF), and each subfield is, for example, (1, 2, 3, 6, 6). 11, 18, 30, 44, 60, 80) Shows a sub-field configuration with a luminance weight of In the first SF initializing period, the all-cell initializing operation is performed (hereinafter, the subfield in which the all-cell initializing operation is performed is abbreviated as “all-cell initializing subfield").
- the selection initialization operation is performed in the initialization period (hereinafter, the subfield for performing the selection initialization operation is abbreviated as “selection initialization subfield”).
- sustain pulses of the number obtained by multiplying the luminance weight of each subfield by a predetermined luminance magnification are applied to each of display electrode pairs 28.
- the number of subfields and the luminance weight of each subfield are not limited to the above values, and the configuration of subfields may be switched based on an image signal or the like.
- FIG. 4 is a drive voltage waveform diagram applied to each electrode of panel 10 in accordance with the exemplary embodiment of the present invention.
- FIG. 4 shows drive voltage waveforms of two subfields, an all-cell initialization subfield and a selective initialization subfield! /, But the drive voltage waveforms in the other subfields are almost the same.
- the first SF which is an all-cell initialization subfield, will be described.
- 0 (V) is applied to data electrodes Dl to Dm and sustain electrodes SUl to SUn, and scan electrodes SCl to SCn are applied to sustain electrodes SUl to SUn. From the voltage Vil below the firing voltage to the voltage Vi2 exceeding the firing voltage, a ramp waveform voltage gradually rising toward the voltage Vi2 is applied.
- the wall voltage on the upper part of the electrode means the voltage generated by the wall charge accumulated on the dielectric layer covering the electrode, on the protective layer, on the phosphor layer and the like.
- the negative wall voltage at the top of scan electrodes SC1 to SCn and the positive wall voltage at the top of sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on the top of data electrodes D1 to Dm is adjusted to a value suitable for write operation. Be done.
- the all-cell initializing operation for performing the initializing discharge for all discharge cells is completed.
- voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SCl to SCn.
- m Apply positive write pulse voltage Vd.
- the voltage difference at the intersection of data electrode Dk and scan electrode SC1 is the difference between the wall voltage on data electrode Dk and the wall voltage on scan electrode SC1 due to the difference in externally applied voltage (Vd-Va). Is added and exceeds the discharge start voltage.
- an address discharge occurs between data electrode Dk and scan electrode SC1 and between sustain electrode SU1 and scan electrode SC1, and a positive wall voltage is accumulated on scan electrode SC1, and a negative voltage is generated on sustain electrode SU1.
- the wall voltage is accumulated, and the negative wall voltage is also accumulated on the data electrode Dk.
- the address operation is performed in which the address discharge is caused in the discharge cells to be lit in the first row and the wall voltage is accumulated on each electrode.
- the voltage at the intersection of data electrodes D1 to Dm to which address pulse voltage Vd is not applied and scan electrode SC1 does not exceed the discharge start voltage, and therefore address discharge does not occur.
- the above address operation is performed up to the nth row of discharge cells, and the address period is completed.
- a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and occurs at this time
- the phosphor layer 35 emits light due to the ultraviolet light.
- negative wall voltage is accumulated on scan electrode SCi
- positive wall voltage is accumulated on sustain electrode SUi.
- a positive wall voltage is also accumulated on the data electrode Dk.
- a sustain discharge does not occur in a discharge cell in which no address discharge occurs in the address period, and the wall voltage at the end of the initialization period is maintained.
- sustain pulses of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU 1 to SUn, and a potential difference is applied between the electrodes of the display electrode pair. Sustain discharge is continuously performed in the discharge cell in which the write discharge occurred in the write period.
- Vs is applied to scan electrodes SCl to SCn
- voltage Vel is applied to sustain electrodes SUl to SUn after force predetermined time Thl, thereby scan electrodes SC1 to SCn and sustain electrodes.
- a part of the wall voltage on scan electrode SCi and sustain electrode SUi is provided while giving a so-called narrow pulse voltage difference between SUl and SUn, leaving a positive wall voltage on data electrode Dk. Or I have erased all.
- the sustain pulse voltage Vs is applied to the scan electrodes SCl to SCn.
- the voltage Vs for generating the final sustain discharge ie, the erase discharge
- the voltage Ve 1 for reducing the potential difference between the electrodes of the display electrode pair Is applied to sustain electrodes SU 1 to SUn the voltage Ve 1 for reducing the potential difference between the electrodes of the display electrode pair Is applied to sustain electrodes SU 1 to SUn.
- the selective initialization operation is an operation to selectively perform the initialization discharge with respect to the discharge cells which have performed the sustain operation in the sustain period of the immediately preceding subfield.
- the operation of the subsequent write period is the same as the operation of the write period of the all-cell initialization sub-field, and therefore the description thereof is omitted.
- the operation of the subsequent sustain period is similar except for the number of sustain pulses.
- the sustaining pulse is denoted as "second sustaining pulse”
- the other sustaining pulse is denoted as "first sustaining pulse”.
- the luminance weight is a subfield immediately before the first SF, which is an all-cell initialization subfield, which is a fifth SF or more in the present embodiment (the fifth SF or more in the present embodiment).
- the second sustain pulse is applied to the scan electrodes SC1 to SCn five times in succession. This generates a stable address discharge without increasing the voltage required for the address.
- FIG. 5 shows the first sustaining pulse and the second sustaining pulse in the embodiment of the present invention. It is a wave form diagram showing an outline.
- “rising time” and “falling time” refer to a power recovery unit 110 or a power recovery unit described later in order to raise the sustain pulse or to lower the sustain pulse.
- a period during which the power recovery unit 110 or the power recovery unit 210 is operated is short when it is short, and it is long when it is long.
- the rise time of the first sustain pulse as a reference is about 550 nsec
- the rise time of the second sustain pulse is about 300 nsec.
- the second sustain pulse has a steeper rise than the first sustain pulse.
- the fall time is equal to each other between the first sustaining pulse and the second sustaining pulse, and both are about 550 nsec.
- FIG. 6 is a schematic diagram showing how a first sustaining pulse and a second sustaining pulse are applied to display electrode pair 28 in the sustaining period according to the embodiment of this invention.
- the first sustaining pulse and the second sustaining pulse whose rising edge is steeper than the first sustaining pulse are generated in the sustaining period, and the display electrode pair 28 is generated.
- the second sustain pulse is applied to scan electrodes SCl to SCn continuously five times at the end of the sustain period.
- this drive circuit has a power recovery unit and a voltage clamp unit. Controls the rising of the sustain pulse.
- the main cause of the instability of the address discharge is that the wall charge formed in the discharge cell is not sufficient, or the variation of the wall charge formed in the discharge cell with each discharge cell. Has been confirmed.
- the wall charge formed is dependent on the intensity of the sustaining discharge, so that weak! ⁇
- the wall charge formed in the discharge cell is also insufficient I will leave.
- the wall charge also has a variation for each discharge cell.
- the address discharge depends on the wall charge formed in the sustain period of the immediately preceding sub-field. That is, an unstable address discharge is generated due to the occurrence of a sustain discharge having an insufficient discharge intensity or a variation in discharge cells among the sustain discharges.
- One of the causes of the occurrence of the sustain discharge with insufficient discharge intensity and the variation of the sustain discharge among the discharge cells is as follows.
- the driving load for each display electrode pair differs according to the display image.
- the impedance of the voltage application means is high, the rise waveform of the sustain pulse is dispersed, and the timing (discharge start time) at which the discharge between the discharge cells is generated is dispersed.
- the discharge start voltage between the display electrode pair is also increased, so that the variation in the timing of occurrence of discharge tends to be further increased.
- the discharge intensity is different between the discharge cell in which the discharge occurs first and the discharge cell in which the discharge occurs later.
- This is started, for example, by decreasing the wall charge of the discharge cell to be discharged later by the influence of the discharge cell to be discharged first and weakening the discharge, or by being affected by the discharge of the adjacent discharge cell. The reason is that the discharge is temporarily stopped, and the discharge is weakened because the discharge is generated again by the increase of the applied voltage.
- the change in voltage is steep, as in the discharge cell of the sustain discharge does not vary. It is effective to generate a discharge at When discharge occurs with a sharp change in voltage, variations in the discharge start voltage are absorbed, and a discharge occurs between discharge cells. This is also a force that can reduce the variation of the ringing. As a result, variations in discharge intensity can be suppressed, and wall charges formed by sustain discharge can be made uniform.
- the effect of forming sufficient wall charge in the discharge cell can be reduced by merely reducing the variation in the timing at which the discharge occurs. Have.
- the second sustaining pulse is generated for the purpose of forming sufficient wall charges in the discharge cell while suppressing the variation in the timing of occurrence of the discharge. That is, by generating the second sustaining pulse whose rising edge is steeper than that of the first sustaining pulse, the discharge is generated in a state where the change of the voltage applied to the panel is sharp. As a result, the variation in discharge start voltage is absorbed, the timings at which discharges occur between discharge cells are made uniform, the variation in wall charge between discharge cells is reduced, and sufficient wall charges are formed in the discharge cells.
- the inventor conducted an experiment to examine the rise and the number of times of application of the second sustain pulse capable of reducing the scan pulse voltage required to generate a normal address discharge.
- FIG. 7 is a diagram showing the relationship between the second sustain pulse and the scan pulse voltage in the embodiment of the present invention.
- the horizontal axis indicates the number of times of application of the second sustain pulse
- the vertical axis indicates the scan pulse voltage required to generate a normal address discharge in the address period of the subsequent sub-field (hereinafter simply referred to as “necessary scan (Abbreviated as “pulse voltage”).
- pulse voltage the scan pulse voltage required to generate a normal address discharge in the address period of the subsequent sub-field
- the number of application of the second sustain pulse is increased by sequentially switching the first sustain pulse to the second sustain pulse based on the drive by the first sustain pulse. It was in addition, the first sustaining pulse force and the second sustaining force are stronger because the directionality of the sustaining pulse applied to the end of the sustaining period and the address discharge in the subsequent sub-field are strongly affected The switching to the pulse was sequentially performed at the end of the sustain period.
- the number of times of application of the second sustain pulse “7” in 7 is the second sustain pulse of the sustain period among the sustain pulses applied to each of scan electrodes SCl to SCn and sustain electrodes SUl to SUn.
- the number of times of application of the second sustaining pulse “8” similarly indicates that the last four sustaining pulses are respectively used as the second sustaining pulse.
- the numerical values for the application of the second sustain pulse shown in the following description represent the number of applications from the end of the sustain period.
- the luminance weight has a predetermined value (this embodiment except for the target power to which the second sustain pulse is applied) in the subfields having small luminance weights (in the present embodiment, the first SF to the fourth SF).
- the second sustain pulse is applied to the 10 or more subfields (fifth SF or more in the present embodiment).
- the all-cell initialization subfield the initialization operation is performed on all discharge cells during the initialization period, and the wall charges are re-formed on all discharge cells, so that all-cell initialization is performed.
- the sub-field immediately before the sub-field (the first SF in the present embodiment) (the tenth SF in the present embodiment) is also excluded from the target to which the second sustain pulse is applied.
- the fifth to ninth SFs are targets to which the second sustaining pulse is applied, and sustaining pulses applied to the display electrode pair 28 are maintained in the sustaining period of those sub-fields.
- the second sustain pulse By switching to the second sustain pulse in order of the last direction of the period, the number of applications of the second sustain pulse was increased!].
- the required scanning pulse voltage changes as the number of times of application of the second sustaining pulse increases.
- the rise time of the second sustain pulse is switched in three ways of 250 nsec, 300 nsec, and 350 nsec, and the same experiment as described above is performed at each rise time to change the steepness of the rise of the second sustain pulse.
- the force is remarkable at a rise time of 350 nsec and 300 nsec. While the difference occurs, the difference between the rise time of 300 nsec and 250 nsec was small!
- the second sustaining pulse may be generated as few as possible, and the rise time of the second sustaining pulse may be as slow as possible within the range in which the required scanning pulse voltage can be reduced.
- the selective discharge is performed to the discharge cell on which the sustaining operation is performed in the sustain period of the immediately preceding subfield, and therefore the sustaining discharge is performed in the immediately preceding subfield.
- the wall charge at the end of the setup period of the sub-field immediately before the discharge is used for writing. Therefore, if the wall charge in the discharge cell not causing light emission decreases due to the strong address discharge generated in the adjacent discharge cell, the next subfield is a sub-field to be subjected to the selective initializing operation, the sub-field is selected. There is a risk that the wall voltage necessary for writing will be insufficient in the field, causing a discharge failure during the writing operation.
- the present inventor can generate stable address discharge without weakening the necessary reduction effect of scan pulse voltage at the time of address operation, and the discharge intensity of the address discharge can be An experiment was conducted to examine whether there is no method that can reduce the wall charge of adjacent discharge cells to a certain extent.
- FIG. 8 is a diagram showing the relationship between the number of applications of the second sustain pulse and the scan pulse voltage in the embodiment of the present invention.
- the horizontal axis indicates the number of times of application of the second sustain pulse
- the vertical axis indicates the necessary scan pulse voltage in the writing period of the subsequent sub-field.
- the rise time S of the second sustain pulse was set to 300 nsec based on the experiment result shown in FIG. Similarly, from the experimental result that the sufficient effect can be obtained by applying the second sustain pulse to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn five times respectively, the second sustain pulse is applied to scan electrode SC. It was investigated what kind of difference occurs in the required scanning pulse voltage when the voltage was applied five times only to 1 to SCn and when it was applied five times only to sustain electrodes SUl to SUn.
- the sustain period of the 5th to 9th SFs was a target to which the second sustain pulse was applied.
- a panel having the same configuration as the panel used in the experiment of FIG. 7 was used under the same conditions.
- FIG. 8 one in which the rise time of the second sustain pulse is 300 nsec among the experimental results shown in FIG. 7 is also shown for comparison with the present experimental results.
- the necessary scan pulse voltage in the next sub-field was about 111 (V) when the second sustain pulse was applied to only sustain electrodes SUl to SUn
- the second sustaining pulse was applied only to the electrodes SCl to SCn
- the value of about 106 (V) is obtained by applying the second sustaining pulse four times each to scan electrodes SCl to SCn and sustain electrodes SUl to SUn. Almost equal to the reduction effect. That is, from this experiment, it was found that sufficient effects can be obtained only by applying the second sustaining pulse to the scan electrodes SCl to SCn.
- a voltage necessary for generating a discharge is applied between scan electrode SCi and data electrode Dk to generate a discharge, and the discharge is made sharp.
- a discharge is generated between SCl to SCn and sustain electrodes SUl to SUn. That is, the wall charges formed on scan electrodes SCl to SCn have a greater effect on the generation of the write discharge than the wall charges formed on sustain electrodes SU1 to SUn.
- the effect of reducing the necessary scan pulse voltage can be further enhanced, in which more wall charges are formed on scan electrodes SCl to SCn. That is, even if the application of the second sustain pulse is only to scan electrodes SCl to SCn, sufficient wall charges on scan electrodes SCl to SCn are generated which affect the generation of the address discharge. Scan pulse voltage can be sufficiently reduced.
- the wall charges formed on sustain electrodes SUl to SUn affect the discharge generated between scan electrodes SCl to SCn and sustain electrodes SUl to SUn at the time of the address discharge. That is, the effect of reducing the required scanning pulse voltage is more influenced by increasing the discharge intensity. Therefore, if the second sustaining pulse is not applied to sustaining electrodes SUl to SUn, the wall charge formed on sustaining electrodes SUl to SUn can be suppressed, and the effect of reducing the discharge intensity of the address discharge can be expected.
- the inventor conducted an experiment to examine how much the writing failure caused by the charge loss is improved when the second sustaining pulse is applied only to scan electrodes SCl to SCn.
- FIG. 9 shows the case where the application condition of the second sustain pulse in the embodiment of the present invention is changed. It is a figure showing change of voltage Ve2 of.
- the horizontal axis shows the conditions for application of the second sustain pulse
- the vertical axis shows the upper limit value of voltage Ve2 at which the writing failure due to the charge loss does not occur in the writing period of the subsequent subfield.
- the voltage applied to the discharge cells increases, and the address discharge is generated stably.
- the higher the voltage Ve2 the stronger the write discharge and the more likely the charge removal.
- the voltage Ve2 applied to the sustain electrodes SU1 to SUn is lowered, the discharge intensity of the address discharge is lowered and charge leakage occurs, but the discharge itself becomes unstable.
- the voltage Ve2 shown in FIG. 9 indicates the upper limit value of the voltage Ve2 applied to the discharge cell which does not cause the charge loss. If the voltage Ve2 is low, charge dropout is likely to occur, and therefore the voltage applied to the discharge cell can not be increased, and the address discharge tends to be unstable. On the other hand, if the voltage Ve2 is high, charge loss is unlikely to occur, so that the voltage applied to the discharge cell can be increased, and a stable address discharge can be generated.
- the second sustaining pulse is applied to each of scan electrodes SCl to SCn and sustaining electrodes SUl to SUn in the normal driving (driving using only the first sustaining pulse) and the 5th to 9th SF address periods.
- the second sustain pulse is applied 5 times only to scan electrodes SCl to SCn in the 5th to 9th SF address periods when 5 times each is applied, scan electrode SCl to 7th SF to 9th S F address periods.
- the second sustaining pulse was applied 5 times only to SCn, the panel was driven under four conditions. Then, under each driving condition, while the voltage Ve2 was gradually raised, the presence or absence of the occurrence of the writing defect due to the charge loss was examined. The charge loss did not occur by the ⁇ ⁇ method, and the upper limit value of the voltage Ve2 was examined. .
- the rise time of the second sustain pulse is set to 300 nsec, as in the experiment shown in FIG.
- panels with the same configuration as the panels used in Figures 7 and 8 were used under the same conditions.
- voltage Ve2 at which no writing failure due to charge loss occurs is determined by the first sustain pulse.
- the second sustain pulse is applied to each of scan electrodes SCl to SCn and sustain electrodes SU1 to SUn in the writing period of the 5th SF to 9th SF, which was about 180 (V) in the case of normal driving using only a scan pulse.
- V voltage
- the result was about 161 (V), which is about 19 (V) lower than that in the normal driving. This indicates that the charge loss is more likely to occur.
- the second sustaining pulse is applied to scan electrodes SCl to SCn and sustain electrodes SUl to SUn, the necessary scan pulse voltage can be reduced, but charge loss is likely to occur.
- the sub-field to which the second sustain pulse is applied is further restricted.
- the voltage Ve2 at which the writing failure due to the charge loss does not occur is about 180 (V), and the result is almost the same as in the normal driving.
- FIG. 10 is a diagram showing a change in scan pulse voltage when the sub field to which the second sustain pulse is applied in the embodiment of the present invention is changed.
- the horizontal axis indicates the subfield to which the second sustain pulse is applied
- the vertical axis indicates the necessary scan pulse voltage in the writing period of the subsequent subfield.
- the rise time of the second sustain pulse was set to 300 nsec, as in the experiments shown in FIG. 8 and FIG.
- panels having the same configuration as the panels used in FIGS. 7 to 9 were used under the same conditions.
- the tenth SF which is the subfield immediately before the all-cell initialization sub-field (the first SF in the present embodiment), is excluded from the target to which the second sustain pulse is applied. .
- the subfields to which the second sustain pulse is applied are the 5th to the 9th SF, the 6th to the 9th SF, the 7th to the 9th SF, and the 8th to the 9th SF.
- the panel was driven under six conditions of normal drive using only the 9th SF and using only the first sustain pulse.
- the necessary scan pulse voltages are set to the fifth SF to the ninth SF and to the sixth SF to the ninth SF in the subfields to which the second sustain pulse is applied.
- the required scanning pulse voltage rises as the number of sub-fields to which the second sustain pulse is applied is reduced thereafter.
- the second sustaining pulse having a steep rising edge is continuously displayed for a predetermined number of times at the end of the sustaining period of a predetermined sub-field.
- the second sustain pulse having a rise time of about 300 nsec is applied to the scan electrodes SC1 to SCn five times consecutively at the end of the sustain period of the 7th to 9th SFs.
- a strong sustain discharge is generated at the end of the sustain period to form sufficient wall charges in the discharge cells, and the address discharge is stabilized without increasing the voltage required for the write in the subsequent write period in the subfield.
- Each of the above-mentioned numerical values is a numerical value depending on the characteristics of the panel used in the experiment, the sub-field configuration, etc., and the characteristics of the panel, sub-field configuration, etc. which are not limited to these numerical values. It is desirable to set the optimum value according to the specifications of the plasma display device. Next, the circuit configuration of the plasma display device in the present embodiment will be described.
- FIG. 11 is a circuit block diagram of a drive circuit for driving a panel in the embodiment of the present invention.
- the plasma display apparatus 1 includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, and a power supply for supplying necessary power to each circuit block. It has a circuit (not shown).
- the image signal processing circuit 51 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield.
- the data electrode drive circuit 52 converts the image data of each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.
- Timing generation circuit 55 generates various timing signals for controlling the operation of each circuit block based on horizontal synchronization signal H and vertical synchronization signal V, and supplies the generated timing signals to each circuit block. Then, as described above, in the present embodiment, two types of sustain pulses are generated which are applied to scan electrodes SCl to SCn and sustain electrodes SUl to SUn in the sustain period, and the timing signal corresponding thereto is generated. Output to scan electrode drive circuit 53 and sustain electrode drive circuit 54. Thus, control is performed to stabilize the write operation.
- Scan electrode drive circuit 53 has a sustain pulse generation circuit 100 for generating sustain pulses to be applied to scan electrodes SCl to SCn in the sustain period, and each scan electrode SCl ⁇ is generated based on the timing signal. Drive SCn respectively.
- Sustain electrode drive circuit 54 includes a circuit for applying voltage Ve1 to sustain electrodes SU1 to SUn in the setup period, a circuit for applying voltage Ve2 to sustain electrodes SU1 to SUn in the write period, and a sustain period.
- a sustain pulse generation circuit 200 for generating a sustain pulse to be applied to the sustain electrodes SU1 to SUn, and drives the sustain electrodes SU1 to SUn based on the timing signal.
- FIG. 12 is a circuit diagram of sustain pulse generating circuit 100 and sustain pulse generating circuit 200 according to the embodiment of the present invention.
- the interelectrode capacitance of panel 10 is indicated as Cp, and the circuit for generating the scanning pulse and the initializing voltage waveform is omitted! Ru.
- Sustain pulse generation circuit 100 includes a power recovery unit 110 and a clamp unit 120.
- the power recovery unit 110 includes a capacitor C10 for power recovery, switching elements Q11 and Q12, a diode D11 for backflow prevention, a diode D12, and an inductor L10 for resonance.
- the clamp unit 120 also includes a switching element Q13 for clamping the scan electrodes SCl to SCn to the power supply VS having a voltage value Vs, and a switching element Q14 for clamping the scan electrodes SCl to SCn to the ground potential. doing.
- Power recovery unit 110 and clamp unit 120 receive scan electrode SCl to SCn, which is one end of inter-electrode capacitance Cp of panel 10, via a scan pulse generation circuit (not shown because it is short-circuited during the sustain period). It is connected to the.
- the power recovery unit 110 performs LC resonance of the interelectrode capacitance Cp and the inductor L10 to perform rise and fall of the sustain pulse.
- the charge stored in the capacitor C10 for power recovery is transferred to the interelectrode capacitance Cp via the switching element Q11, the diode D11 and the inductor L10.
- the charge stored in the interelectrode capacitance Cp is returned to the power recovery capacitor C10 through the inductor L10, the diode D12 and the switching element Q12.
- sustain pulses are applied to scan electrodes SCl to SCn.
- the power recovery capacitor C10 has a sufficiently large capacity compared to the inter-electrode capacity, and is charged to about VsZ2, which is half the voltage value Vs of the power supply VS, so that it works as a power source for the power recovery unit 110! .
- Voltage clamp unit 120 connects scan electrodes SCl to SCn to power supply VS via switching element Q13, and clamps scan electrodes SCl to SCn to voltage Vs. Further, the scan electrodes SCl to SCn are grounded via the switching element Q14 and clamped to O (V). Thus, the voltage clamp unit 120 drives the scan electrodes SCl to SCn. Therefore, the impedance at the time of voltage application by the voltage clamp unit 120 can be small, and a large discharge current due to strong sustain discharge can be stably flowed.
- sustain pulse generating circuit 100 includes switching element Ql l and switching element Q12. By controlling switching element Q13 and switching element Q14, a sustain pulse is applied to scan electrodes SCl to SCn using power recovery unit 110 and voltage clamp unit 120.
- switching elements can be configured using generally known elements such as MOSFETs and IGBTs.
- Sustain pulse generation circuit 200 includes: power recovery unit 210 having capacitor C20 for power recovery, switching element Q21, switching element Q22, diode D21 for backflow prevention, diode D22, and inductor L20 for resonance. And a clamp portion 220 having switching element Q23 for clamping electrodes SU1 to SUn at voltage Vs and switching element Q24 for clamping sustain electrodes SU1 to SUn at the ground potential, and the interelectrode capacitance Cp of panel 10 It is connected to the sustain electrodes SU1 to SUn which are one end of.
- the operation of sustain pulse generating circuit 200 is the same as that of sustain pulse generating circuit 100, and therefore the description thereof is omitted.
- a power supply VE1 that generates a voltage Vel for relieving a potential difference between the display electrode pair
- a power supply VE2 that generates a voltage Ve2
- a voltage Vel to sustain electrodes SU1 to SU n Also shown are a switching element Q26 for application, a switching element Q27, a switching element Q28 for applying the voltage Ve2 to the sustain electrodes SU1 to SUn, and a switching element Q29.
- the cycle of LC resonance between inductor L10 of power recovery unit 110 and inter-electrode capacitance Cp of panel 10, and LC resonance cycle between inductor L20 of power recovery unit 210 and inter-electrode capacitance Cp (hereinafter referred to as The “resonance period” can be obtained by the formula “2 ⁇ f (LCp)”, where L is the inductance of the inductor L10 and the inductance L20 of the inductor L20. Then, in the present embodiment, the inductor L10 and the inductor L20 are set so that the resonance period in the power recovery unit 110 and the power recovery unit 210 is approximately 110 Onsec! /.
- FIG. 13 is a waveform diagram of a first sustain pulse in the embodiment of the present invention.
- the sustaining pulse generating circuit 100 on the side of scan electrodes SC1 to SCn will be described.
- Force sustaining electrodes SU1 to SUn The sustain pulse generating circuit 200 on the side has a similar circuit configuration, and its operation is also substantially the same. Further, in the following description of the operation of the switching element, the operation for conducting is denoted as “ON”, and the operation for blocking is denoted as “OFF”.
- the switching element Q11 is turned on at time tl. Then, charges start to move from the capacitor C10 for power recovery to the scan electrodes SCI to SCn through the switching element Q11, the diode D11, and the inductor L10, and the voltage of the scan electrodes SCl to SCn starts to rise. Since the inductor L10 and the interelectrode capacitance Cp form a resonant circuit, the voltage of the scan electrodes SCl to SCn ascends to near Vs at the time when about 1Z2 of the resonant period has elapsed from time t1.
- the resonance period of inductor L10 and interelectrode capacitance Cp is set to about 1 lOOnsec, and the first sustain pulse is applied to scan electrodes SCl to SCn.
- the rise time of the sustain pulse that is, the time period between the time t1 and the time t21, is set to about 550 nsec of 1Z2 of the resonance period.
- scan electrodes SCl to SCn are connected to power supply VS through switching element Q13, scan electrodes SCl to SCn are clamped to voltage Vs.
- the voltage difference between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn exceeds the firing voltage in the discharge cell in which the address discharge has occurred, and sustain discharge occurs. Occur. If the clamp period to the power supply VS is too short, the wall voltage formed along with the sustain discharge will be insufficient, and the sustain discharge can not be generated continuously. On the contrary, if it is too long, the repetition cycle of the sustaining pulse becomes long, and it becomes impossible to apply the required number of sustaining pulses to the display electrode pair. Therefore, practically, it is desirable to set the clamp period to the power supply VS to about 800 nsec to 1500 nsec. And, in the present embodiment, the period T21 is set to about 1 Opnsec! / Scold.
- Period T31 At time t31, the switching element Q12 is turned on. Then, a charge starts moving from the scan electrodes SCl to SCn to the capacitor CIO through the inductor L10, the diode D12, and the switching element Q12, and the voltage of the scan electrodes SCl to SCn starts to decrease.
- the resonance period of the inductor L10 and the interelectrode capacitance Cp is set to about 1 lOOnsec, and in the first sustain pulse, the fall time of the sustain pulse applied to the scan electrodes SCl to SCn. That is, the time period T31 from time t31 to time t4 is set to about 550 nsec of 1Z2 of the resonance period.
- the switching element Q14 is turned on at time t4 when approximately 1Z2 of the resonance period has elapsed from time t31. Then, since scan electrodes SCl to SCn are directly grounded through switching element Q14, scan electrodes SCl to SCn are clamped at O (V).
- the rise time and fall time of the first sustain pulse are about 550 nsec, and are set to about 1 Z 2 of about 1 1 lOOnsec of the resonance period of the inductor L 10 and the interelectrode capacitance Cp.
- FIG. 14 is a waveform diagram of the second sustain pulse in the embodiment of the present invention.
- the switching element Q11 is turned on at time tl. Then, charges start to move from the capacitor C10 for power recovery to the scan electrodes SCI to SCn through the switching element Q11, the diode D11, and the inductor L10, and the voltage of the scan electrodes SCl to SCn starts to rise.
- the rise time of the sustain pulse applied to scan electrodes SCl to SCn that is, the period T12 from time tl to time t22 is shorter than 1Z2 of its resonance period, about 300 nsec. Is set to!
- the switching element Q13 is turned ON. Then, since scan electrodes SC1 to SCn are directly connected to power supply VS through switching element Q13, scan electrodes SC1 to SCn are clamped to voltage Vs, and sustain discharge occurs.
- the period T22 is shorter than the period T21 by an amount corresponding to a shorter rise time than the first sustain pulse. Also, the pulse width from rising to falling is changed in the first sustaining pulse and the second sustaining pulse so as to be approximately 1150 nsec.
- the rise time of the second sustain pulse is set to about 300 nsec, which is shorter than the first sustain pulse, and is steeper than that of the first sustain pulse.
- the above is the operation of the sustain pulse generating circuit for generating the first sustain pulse and the second sustain pulse in the present embodiment, and as described above, to the display electrode pair by the power recovery unit.
- the switching elements specifically, switching elements Ql l and Q21
- two types of sustain pulses with different rise are generated.
- the description is given by taking a sub-field configuration in which the first SF is the all-cell initialization sub-field and the second SF to the tenth SF are the selection initialization sub-fields as an example.
- the present invention is not necessarily limited to this sub-field configuration, and may have other sub-field configurations.
- the configuration has been described in which the second sustaining pulse is applied to scan electrodes SC 1 to SCn continuously five times at the end of the sustaining period, but this configuration is limited to this value. It is desirable to set the optimum number of times according to the characteristics of the panel to be removed.
- only the first sustaining pulse may be applied to scan electrodes SCl to SCn and sustaining electrodes SU1 to SUn, or the first sustaining pulse and the second sustaining pulse may be applied.
- the sustain pulses may be periodically switched and applied so as to have a predetermined ratio, for example, a ratio of 2: 1.
- the force applied to the target subfield to which the second sustain pulse is continuously applied is the fifth SF or more, which is a subfield having a luminance weight of a predetermined value (for example, 10) or more.
- a predetermined value for example, 10
- the second sustain pulse is applied according to the total number of sustain pulses in one sub-field period.
- a subfield for which the total number of sustaining pulses in one subfield period is 50 or more is taken as a subfield to which a second sustaining pulse is applied.
- the configuration using the same inductor for power supply and for power recovery has been described, but a plurality of inductors having different inductances may be switched without being limited to this configuration. It is good also as composition used. In this configuration, for example, when making the rising or falling of the sustain pulse steep, it is possible to switch to the inductor with higher resonance frequency and drive.
- the voltage waveform of the last sustain pulse in the sustain period is not limited to the above-described voltage waveform.
- the xenon partial pressure of the discharge gas may be 10%, or any other xenon partial pressure may be used.
- the generation ratio of each sustain pulse is set according to the panel. do it.
- each experiment is conducted using a 50-inch panel of 1080 display pairs of log, and the specific numerical values mentioned in the present embodiment are the same as those of the panel. And are merely an example. In the present embodiment, it is desirable to set the value to an optimum value appropriately in accordance with the characteristics of the panel, the specification of the plasma display device, and the like which are not limited to these numerical values.
- the second sustaining pulse having a steep rise is continuously applied to one of the display electrode pairs a predetermined number of times at the end of the sustain period of the predetermined sub-field.
- the second sustain pulse whose rise time is about 300 nsec is applied to scan electrodes S Cl to SC n continuously five times at the end of the sustain period of seventh SF to ninth SF.
- a strong sustain discharge is generated at the end of the sustain period to form sufficient wall charges in the discharge cells, and the address discharge is stabilized without increasing the voltage required for the write in the subsequent write period in the subfield.
- the discharge intensity in the adjacent discharge cell due to charge It becomes possible to control to such an extent that a defect does not occur.
- the present invention can generate a stable address discharge without increasing the voltage required for writing even in a high definition / brightness panel, and is useful as a driving method of a plasma display device and a panel. .
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Description
Claims
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JP2008502769A JP5062169B2 (ja) | 2006-07-14 | 2007-07-06 | プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 |
CN2007800012064A CN101356568B (zh) | 2006-07-14 | 2007-07-06 | 等离子体显示器装置及等离子体显示器面板的驱动方法 |
US12/092,188 US20090284446A1 (en) | 2006-07-14 | 2007-07-06 | Plasma display device and plasma-display-panel driving method |
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JP2006-193824 | 2006-07-14 | ||
JP2006193824 | 2006-07-14 |
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US (1) | US20090284446A1 (ja) |
JP (1) | JP5062169B2 (ja) |
KR (1) | KR100941222B1 (ja) |
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WO2008132781A1 (ja) * | 2007-04-20 | 2008-11-06 | Panasonic Corporation | プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 |
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KR20110026615A (ko) * | 2009-09-08 | 2011-03-16 | 삼성전자주식회사 | 잔상을 저감시키는 디스플레이장치 및 그 구동방법 |
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JP2004206094A (ja) * | 2002-12-13 | 2004-07-22 | Matsushita Electric Ind Co Ltd | プラズマディスプレイパネルの駆動方法 |
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US4866349A (en) * | 1986-09-25 | 1989-09-12 | The Board Of Trustees Of The University Of Illinois | Power efficient sustain drivers and address drivers for plasma panel |
JP3681029B2 (ja) * | 1997-08-25 | 2005-08-10 | 三菱電機株式会社 | プラズマディスプレイパネルの駆動方法 |
JP3642689B2 (ja) * | 1998-12-08 | 2005-04-27 | 富士通株式会社 | プラズマディスプレイパネル装置 |
JP2001013913A (ja) * | 1999-06-30 | 2001-01-19 | Hitachi Ltd | 放電式表示装置及びその駆動方法 |
JP4293397B2 (ja) * | 1999-06-30 | 2009-07-08 | 株式会社日立プラズマパテントライセンシング | 発光効率を向上させた表示パネルの駆動回路 |
KR20020060807A (ko) * | 2001-01-12 | 2002-07-19 | 주식회사 유피디 | 면방전 플라즈마 디스플레이 패널 구동장치 및 그 방법 |
KR100396164B1 (ko) * | 2001-01-18 | 2003-08-27 | 엘지전자 주식회사 | 플라즈마 디스플레이 패널의 구동방법 및 장치 |
JP4606612B2 (ja) * | 2001-02-05 | 2011-01-05 | 日立プラズマディスプレイ株式会社 | プラズマディスプレイパネルの駆動方法 |
JP4147760B2 (ja) * | 2001-10-15 | 2008-09-10 | 松下電器産業株式会社 | プラズマディスプレイパネルの駆動方法およびプラズマディスプレイ装置 |
JP4061927B2 (ja) * | 2002-03-11 | 2008-03-19 | 松下電器産業株式会社 | プラズマディスプレイ装置 |
JP2003271089A (ja) * | 2002-03-15 | 2003-09-25 | Fujitsu Hitachi Plasma Display Ltd | プラズマディスプレイパネルおよびその駆動方法 |
KR100472372B1 (ko) * | 2002-08-01 | 2005-02-21 | 엘지전자 주식회사 | 플라즈마 디스플레이 패널의 구동방법 |
KR100574124B1 (ko) * | 2002-12-13 | 2006-04-26 | 마츠시타 덴끼 산교 가부시키가이샤 | 플라즈마 디스플레이 패널의 구동 방법 |
JP2004271877A (ja) * | 2003-03-07 | 2004-09-30 | Matsushita Electric Ind Co Ltd | 表示装置およびその駆動方法 |
KR100582205B1 (ko) * | 2004-05-06 | 2006-05-23 | 엘지전자 주식회사 | 플라즈마 디스플레이 패널의 구동방법 |
KR100578975B1 (ko) * | 2004-05-28 | 2006-05-12 | 삼성에스디아이 주식회사 | 플라즈마 표시 장치와 플라즈마 표시 패널의 구동 방법 |
KR100542772B1 (ko) * | 2004-07-16 | 2006-01-20 | 엘지전자 주식회사 | 플라즈마 디스플레이 패널 구동방법 및 장치 |
KR100667550B1 (ko) * | 2005-01-10 | 2007-01-12 | 엘지전자 주식회사 | 플라즈마 디스플레이 패널의 구동방법 |
JP4479796B2 (ja) * | 2006-07-11 | 2010-06-09 | パナソニック株式会社 | プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 |
JP4946593B2 (ja) * | 2007-04-20 | 2012-06-06 | パナソニック株式会社 | プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 |
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2007
- 2007-07-06 JP JP2008502769A patent/JP5062169B2/ja not_active Expired - Fee Related
- 2007-07-06 KR KR1020087010448A patent/KR100941222B1/ko not_active IP Right Cessation
- 2007-07-06 CN CN2007800012064A patent/CN101356568B/zh not_active Expired - Fee Related
- 2007-07-06 WO PCT/JP2007/063558 patent/WO2008007619A1/ja active Application Filing
- 2007-07-06 US US12/092,188 patent/US20090284446A1/en not_active Abandoned
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004206094A (ja) * | 2002-12-13 | 2004-07-22 | Matsushita Electric Ind Co Ltd | プラズマディスプレイパネルの駆動方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2008132781A1 (ja) * | 2007-04-20 | 2008-11-06 | Panasonic Corporation | プラズマディスプレイ装置およびプラズマディスプレイパネルの駆動方法 |
US8379007B2 (en) | 2007-04-20 | 2013-02-19 | Panasonic Corporation | Plasma display device and method for driving plasma display panel |
Also Published As
Publication number | Publication date |
---|---|
KR100941222B1 (ko) | 2010-02-10 |
CN101356568A (zh) | 2009-01-28 |
US20090284446A1 (en) | 2009-11-19 |
JPWO2008007619A1 (ja) | 2010-04-22 |
CN101356568B (zh) | 2011-12-14 |
KR20080054432A (ko) | 2008-06-17 |
JP5062169B2 (ja) | 2012-10-31 |
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