WO2007142172A1 - procédé de fabrication de câblage multicouche, structure DE CÂBLAGE MULTICOUCHE, et appareil DE FABRICATION DE CÂBLAGE MULTICOUCHE - Google Patents

procédé de fabrication de câblage multicouche, structure DE CÂBLAGE MULTICOUCHE, et appareil DE FABRICATION DE CÂBLAGE MULTICOUCHE Download PDF

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Publication number
WO2007142172A1
WO2007142172A1 PCT/JP2007/061253 JP2007061253W WO2007142172A1 WO 2007142172 A1 WO2007142172 A1 WO 2007142172A1 JP 2007061253 W JP2007061253 W JP 2007061253W WO 2007142172 A1 WO2007142172 A1 WO 2007142172A1
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Prior art keywords
film
dielectric constant
low dielectric
wiring
constant film
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PCT/JP2007/061253
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English (en)
Japanese (ja)
Inventor
Hiroto Ohtake
Munehiro Tada
Masayoshi Tagami
Yoshihiro Hayashi
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Nec Corporation
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Priority to JP2008520553A priority Critical patent/JPWO2007142172A1/ja
Publication of WO2007142172A1 publication Critical patent/WO2007142172A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Multilayer wiring manufacturing method, multilayer wiring structure, and multilayer wiring manufacturing apparatus The present invention is based on Japanese Patent Application No. 2 0 0 6-1 6 1 2 0 4 filed on June 9, 2000, And claims the benefit of that priority, the disclosure of which is hereby incorporated by reference in its entirety.
  • the present invention relates to a multilayer wiring manufacturing method manual having a trench wiring, a multilayer wiring structure, and a multilayer wiring manufacturing apparatus.
  • Background technology :
  • a method using copper as a wiring material and a film having a dielectric constant lower than that of a silicon oxide film as an interlayer dielectric film is used. Furthermore, the dual damascene method is adopted to reduce the process and wiring resistance. In the dual damascene method, the process of copper embedding and the mechanical and chemical polishing process of copper can be reduced compared to single damascene. In addition, since there is no barrier film above the via, the via resistance can be reduced.
  • a low dielectric constant film such as Cu cap film, Si OCH, etc., formed of material such as Si CN on lower layer wiring 1 Via interlayer low dielectric constant film formed by, etching stopper film formed by inorganic film such as S i O 2, wiring interlayer low dielectric constant film formed by low dielectric constant film such as porous S i OCH, S i Hard mask made of inorganic film such as O 2 , S i C In the insulating film structure of the Cu cap film formed of materials such as copper, wiring novia composed of copper, Ta / TaN, and other copper barrier films is embedded. .
  • This structure is formed by a dual damascene method described in Japanese Patent Application No. 2006-001864 (hereinafter referred to as Reference 1).
  • Reference 1 Japanese Patent Application No. 2006-001864
  • it is effective to replace the Cu cap film, etching stopper film, and hard mask made of inorganic film with a low dielectric constant film.
  • etch stopper film is eliminated, there is no layer that stops etching during groove etching, resulting in in-plane variations and pattern variations. If there is an etching stopper, the stop of etching can be automatically stopped by using the end point detection program of emission spectroscopy, but the end point detection program cannot be used without the etching stopper. Variations in depth between wafers and mouths are likely to occur.
  • a plasma CVD—Si001 ⁇ film is used as a low dielectric constant film between vias. 11 rora TM film, and an MP S film that is a molecular pore film is used as a low dielectric constant film between wiring layers.
  • a tack membrane is used.
  • an object of the present invention is to provide a manufacturing method in etching processing that suppresses in-plane variation and pattern variation during groove etching and enables end point detection in dual damascene wiring formed in a low dielectric constant film.
  • Another object of the present invention is to provide a multilayer wiring structure having high insulation between wirings as a result.
  • Another object of the present invention is to provide a multilayer wiring manufacturing apparatus that enables manufacturing of a multilayer wiring structure by implementing the method for manufacturing a multilayer wiring. Means to solve the problem:
  • a S i OCH film continuum in which a first S i OCH low dielectric constant film located in a lower layer and a second S i OCH low dielectric constant film located in an upper layer are directly laminated
  • the carbon silicon ratio of the second S i OCH low dielectric constant film is larger than the carbon Z silicon ratio of the first S i OCH low dielectric constant film
  • the second S i OCH low dielectric constant film located in the upper layer is grooved and stopped on the first S i OCH low dielectric constant film located in the lower layer, at least N 2 and CHX F 7 are included It is characterized by processing using end point detection by emission spectroscopy of mixed gas plasma.
  • the carbon / silicon ratio of the second Si OCH low dielectric constant film located in the upper layer is 2 as compared with the carbon silicon ratio of the first Si OCH low dielectric constant film located in the lower layer. It is characterized by being at least twice as large.
  • CH x F y in the mixing force plasma is CF 4 , CHF 3 , CH 2 F 2 or a mixed gas thereof, and the nitrogen content is preferably 20 to 50%.
  • a barrier insulating film on a lower layer wiring, a via interlayer low dielectric constant film made of the first S i OCH low dielectric constant film, and a wiring interlayer low dielectric constant film made of the second Si OCH low dielectric constant film A step of sequentially forming a hard mask film, a step of forming a via hole resist pattern on the hard mask film, a step of forming a via hole in the insulating film structure, and removing the via hole resist by oxygen plasma ashing
  • the second S i O while performing end point detection by emission spectroscopy using a mixed gas plasma containing N 2 and CHXF y. It is characterized by a step of forming a groove in a low dielectric constant film between via layers made of a CH low dielectric constant film.
  • the second porous S i OCH film may be composed of a plurality of S i OCH films.
  • the multilayer wiring structure shown in the present invention is characterized in that the carbon / silicon ratio in the wiring interlayer low dielectric constant film is larger than that in the via interlayer low dielectric constant film. At this time, it is preferable that the carbonosilicon ratio in the wiring interlayer low dielectric constant film is at least twice as large as that in the via interlayer low dielectric constant film. In addition, at least one of the wiring interlayer low dielectric constant film and the via interlayer low dielectric constant film is a porous film containing pores.
  • the wiring interlayer low dielectric constant film is made of Si O C H and has a carbon silicon ratio of 15 or more, may have a 6-membered silica skeleton, or may contain unsaturated hydrocarbons in the film.
  • a structure in which a silicon oxide film is laminated on a wiring interlayer low dielectric constant film may be used. Another feature is that the thickness of the oxidized modified layer formed on the sidewall of the low-dielectric-constant interlayer between the wiring layers is smaller than the thickness of the oxidized modified layer formed on the sidewall of the low-dielectric-layered via layer. It is.
  • the multilayer wiring manufacturing apparatus shown in the present invention is used for forming an opening in an interlayer insulating film having a laminated structure containing Si OCH as a main component, and the end point from the time variation of the emission intensity of Si F in plasma.
  • a microcomputer having a program for detecting and automatically stopping the processing having the inside of the interlayer insulating film of the laminated structure as an end point.
  • FIG. 1A shows a conventional dual damascene wiring.
  • Figure 1B shows the structure of the conventional dual damascene interconnect with a lower effective relative permittivity.
  • Fig. 2 shows the N 2 flow rate dependence of the etching rate of MP S and Aurora TM .
  • FIG. 3A shows a light emission spectrum in Ar / N 2 / CF 4 plasma.
  • FIG. 3B shows the emission spectrum in Ar / Ns / C Fs plasma.
  • Fig. 4 shows the time variation of the emission spectrum at 440 nm during MPS etching.
  • Figure 6 shows the TDS spectrum after exposing MPS to the etching plasma.
  • Figure 7 shows the N 1 s (XP S) spectrum after exposing MP S and Aurora TM to the etching plasma.
  • Fig. 8A shows the result of TEM-EEL S mapping observed from MPS sidewall after wiring processing.
  • Fig. 8B is the result of TEM-EELS matbing observation of the composition analysis from the A urora TM sidewall after wiring processing.
  • Fig. 8C is a cross-sectional view of the sample for TEM-EEL S matbing to analyze the composition from the side walls of MP S and Aurora TM after wiring processing in Fig. 8A and 8B .
  • Figure 9 shows the oxide layer on the side wall of MP S, Au rora TM after wiring processing. It is an electron micrograph investigated by a computer.
  • FIG. 10A is a cross-sectional view showing a step of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
  • FIG. 10B is a sectional view showing a step subsequent to the first OA diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
  • FIG. 1 OC is a sectional view showing a step subsequent to the first OB diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
  • FIG. 1 OD is a cross-sectional view showing a step subsequent to the first OC diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
  • FIG. 1 OE is a sectional view showing a step subsequent to the first OD diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
  • FIG. 10F is a sectional view showing a step subsequent to the first OE diagram of the method for manufacturing the multilayer wiring according to the first example of the present invention.
  • FIG. 1 OG is a sectional view showing a step subsequent to the first OF diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
  • FIG. 10H is a sectional view showing a step subsequent to the first OG diagram of the method for manufacturing the multilayer wiring according to the first embodiment of the present invention.
  • FIG. 10I is a cross-sectional view showing the next step of FIG. 10H in the method for manufacturing the multilayer wiring according to the first embodiment of the present invention.
  • FIG. 11A is a cross-sectional view showing one step of a method for manufacturing a multilayer wiring according to a second embodiment of the present invention.
  • FIG. 11B is a sectional view showing a step subsequent to FIG. 11A of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
  • FIGS. 11C to 11H are cross-sectional views showing the next step of FIG. 11B in the multilayer wiring manufacturing method according to the second embodiment of the present invention.
  • FIG. 11D is a sectional view showing a step subsequent to FIG. 11C of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
  • FIG. 11 E is a view of FIG. 11D of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention. It is sectional drawing which shows the next process.
  • FIG. 11 F is a cross-sectional view showing the next step of FIG. 11 E in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
  • FIG. 11 G is a cross-sectional view showing the next step of FIG. 11 F in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
  • FIG. 11 H is a cross-sectional view showing the next step of FIG. 11 G in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
  • FIG. 11 I is a cross-sectional view showing a step subsequent to FIG. 11 H of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
  • FIG. 12 is a view showing a multilayer wiring structure according to a third embodiment of the present invention. Best Mode for Carrying Out the Invention:
  • a Cu cap film formed on the lower wiring 1 with a material such as SiCN. 2 Via interlayer low dielectric constant film formed with low dielectric constant film such as S i OCH 3, Etching stopper film formed with inorganic film such as S i 0 2 , Low dielectric constant film such as porous S i OCH
  • a material such as SiCN. 2 Via interlayer low dielectric constant film formed with low dielectric constant film such as S i OCH 3, Etching stopper film formed with inorganic film such as S i 0 2 , Low dielectric constant film such as porous S i OCH
  • Cu cap film 7 formed of material such as Si CN The main wiring is made up of copper 8, Ding 3 Ding 3 ⁇ , etc. 11 Barrier membrane
  • the wiring via consisting of 9 is embedded in the structure.
  • This structure is formed by a dual damascene method described in Japanese Patent Application Laid-Open No. 2 004-0 4 7 8 7 3 (hereinafter referred to as Patent Document 1).
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2 004-0 4 7 8 7 3
  • the etching stopper film 4 and the hard mask 6 exist between the electrodes, the effective relative dielectric constant can be reduced by replacing with a low dielectric constant film. Therefore, as shown in Fig. IB, a structure in which there is no etching stopper and the hard mask is a low dielectric constant hard mask 6, is being studied.
  • the present invention relates to a continuous S i OCH film in which a first S i OCH low dielectric constant film located in a lower layer and a second S i OCH low dielectric constant film located in an upper layer are directly laminated.
  • the upper S i OCH film is etched with two kinds of S i OCH low dielectric constant films with different carbon silicon ratios (CZS i ratio) in N 2 ZCH x F y mixed gas system, the upper and lower S i OCH films This is based on the discovery that the etching selectivity can be secured and the end point can be detected by emission spectroscopy.
  • a plasma CVD-Si001 "1 film is used as a low dielectric constant film between vias, 11 rora TM film, and a molecular thin film is formed as a wiring interlayer low dielectric constant film.
  • MP S _ S i OCH film Mo 1 ecu 1 ar Por S tack film, hereinafter simply referred to as “MP S”
  • carbon in the MP S _ S i O CH film Silicon ratio 2.7
  • carbon silicon ratio in Aurora TM film plasma CVD—Si OCH film
  • film 2 is used as a hard mask.
  • etching is performed using a mixed gas plasma composed of fluorocarbon made of single carbon atoms such as CF 4 and 20 to 50% nitrogen gas.
  • FIG. 2 is a graph showing the dependency of Si OCH (Au rora TM, MPS) etching rate on a nitrogen addition amount evaluated with a blanket wafer.
  • the distance between electrodes is 35 mm
  • the pressure is 6.65 5 Pa (5 OmTorr)
  • the upper electrode power is 1 ⁇ 0 0 W
  • the lower electrode power is 100 W
  • It was determined etching rate under the conditions of a r / N 2 / CF 4 /0 2 3 0 0/1 0 0/2 5/6 sccm.
  • Au rora TM the etching rate decreases due to the nitrogen content, whereas with MP S, the etching rate increases.
  • FIG. 3A and 3B are diagrams showing a 440 nm emission spectrum when the MPS substrate and the silicon substrate are etched by adding C 4 F 8 gas or CF 4 gas.
  • C 4 F 8 has a molecular emission spectrum from a polymer fluorocarbon over a wide band, so the emission at 440 nm tends to be buried. If CF 4 is used, it can be clearly confirmed.
  • Fig. 5A shows Fig. 5B
  • Fig. 5C shows the structure of S i 0 2 / MP s / S i OCH
  • the results of observing the temporal change of the 440 nm emission spectrum are shown.
  • the C / Si ratio of MP S is 27.
  • the lower the 3 i ratio of Si i 011 in the lower layer the larger the time change of the spectrum at 440 nm.
  • the C / Si ratio is 1.4 or less, the time change is particularly large.
  • the C / Si ratio of the upper S i OCH (here MP S) is preferably about twice that of the lower layer in the S i OCH film continuum.
  • etching of MP S with a gas such as Ar / N 2 / CF 4 can secure a selection ratio with the lower layer of Au rora TM film, and the S i OCH film can be obtained by emission spectroscopy. Because it is a continuum, for example, it is possible to detect the end point of etching of two types of Si OCH low dielectric constant films made of the same material, so there is little pattern variation if there is in-plane variation, and variation between wafers and mouths. Fewer grooves can be machined.
  • Ar N 2 / / CF 4 is superior ArZ N2 Bruno C 4 F 8.
  • ⁇ 4 compared to the Flip 4
  • CF 4 is preferable because when fluorine is incorporated into the Si OCH film, adhesion is deteriorated or HF is formed by moisture absorption to form a void in the film.
  • CF 3 ions are known to be higher than CF 2 and CF ion, CF 4 is added to generate a CF 3 ions.
  • a carbonitride film is formed on the side wall when plasma etching is performed with a C x H y ZN 2 gas.
  • Figure 7 shows the N 1 s spectrum observed on the surface after irradiation with etching plasma using XPS.
  • the MP S film ie, in the S i OCH film with a C / Si ratio> 1
  • a spectrum of N 1 s is observed after irradiation.
  • This carbonitride film is completely removed in the oxygen ashing process that follows the etching process, but it has the effect of suppressing carbon extraction from the side walls of the Si OCH film. That is, the amount of oxidation of the side wall after oxygen ashing is suppressed.
  • This effect increases as the amount of carbon in the S i OCH film increases. This was remarkable, and the one containing unsaturated hydrocarbons in the film was even more remarkable.
  • the carbon skeleton has a CZSi ratio> 1 S i OCH film with a silica skeleton in a ring, or a 6-membered ring (S i 3 O 3 ). There was also a tendency to suppress the amount of oxidation on the side walls.
  • the wiring interlayer low dielectric constant film which is a carbon-rich S i OCH film characteristic of the present invention
  • the via interlayer low dielectric constant film which is a silicon-rich (CZS i 1) S i OCH film
  • CZS i 1 S i OCH film silicon-rich (CZS i 1) S i OCH film
  • FIGS. 8A and 8B are diagrams showing the results of analyzing the composition of the MPS film and the Aurora TM film by TEM_EELS mapping after forming Cu wiring on the pattern exposed to the assin plasma after etching.
  • Figure 8C is a cross-sectional view of the sample for TEM-EEL S mapping.
  • Fig. 9 is an electron micrograph of Cu wiring formed on the pattern exposed to ashing plasma after etching, and the oxide layer on the side wall of MPS, Aurora TM after wiring processing was investigated by hydrofluoric acid dip.
  • FIGS. 1A to 1H are cross-sectional views illustrating a manufacturing process of a multilayer wiring structure according to the first embodiment of the present invention.
  • via processing was performed in forming a so-called dual damascene Cu wiring in which a via and a wiring trench were formed in an insulating film structure of a silicon oxide film ZMPS film Au rora TM / SiCN.
  • a resist pattern for the wiring trench is formed, and the MPS film is etched by using Ar ZN 2 ZC F 4 plasma to detect the end point by light emission. ⁇ It is possible to perform grooving with little variation between the mouthpieces.
  • An MPS film 204, which is an index film, and a silicon oxide film 205, which is a hard mask, are formed in this order by, for example, a plasma CVD method, and an antireflection film 206 and a via resist 2007 are formed thereon.
  • via resist patterns 2 0 7 a and 2 0 7 b are formed.
  • via hole patterns 2 0 3 a and 2 0 3 b are formed.
  • an organic film 2 08 is applied on the silicon oxide film 2 05 and a silicon oxide film 2 09 is formed by, eg, CVD.
  • silicon on the oxide film 209 an antireflection film 210 and a wiring groove resist 211 are applied in this order to form wiring groove resist patterns 21 1a and 21 1b.
  • the antireflection film 210, the silicon oxide film 209, the organic film 208, and the silicon oxide film 205 are etched using the wiring groove resist patterns 21 1a and 21 1b as masks.
  • the interconnect trench resist 211 and the antireflection film 210 disappear, and when the silicon oxide film 205 is etched, the silicon oxide film 209 disappears. Therefore, the etching shown in FIG. 10E After the addition, the organic film 208 becomes the top layer.
  • wiring groove hard mask patterns 205a and 205b to which the wiring groove pattern is transferred can be formed.
  • the MPS film 204 is etched using Ar ZNzZC F 4 plasma using the wiring groove hard mask patterns 205a and 205b as a mask.
  • the manufacturing process according to the present invention and an interlayer insulating film structure in which Si OCH films having different chemical compositions are directly stacked are used. It becomes. Thereafter, as shown in FIG. 10I, noria 'Cu seed sputtering and Cu plating are performed, and Cu wiring 212 is formed by CMP. Furthermore, a silicon carbonitride film is deposited as a Cu cap film by, for example, the CVD method. By repeating this, multilayer wiring can be formed.
  • the MPS film is shown as the wiring interlayer low dielectric constant film in this example, a sufficient difference in carbonosilicon ratio from the via interlayer low dielectric constant film can be secured.
  • the same materials as above can be applied.
  • the carbon silicon ratio of the low dielectric constant film between the wiring layers should be at least twice the carbon silicon ratio of the low dielectric constant film between the vias.
  • the CZS i ratio in the S i OCH film is 1.5 to suppress the oxidation of the wiring trench sidewall due to the oxygen-ashing process. The above is desirable.
  • CZS i ratio in via interlayer low dielectric constant film is 1 or less Japan ASM Aurora series, Tricon Orion, A pp 1 ied Materials BD / BD II, Novellus Cora 1 C VD_ S i OCH film, Dow—Chica ica 1 Porous S i LK: Can be applied to NCS, etc.
  • a Si OCH film formed by plasma polymerization as shown in Patent Document 1 may be used. Considering mounting resistance, the low dielectric constant film between via layers is lower than the low dielectric constant film between wiring layers. It is preferred to select a material with a high density.
  • the silicon carbonitride film was used as the Cu cap film, but the etching selectivity with the low dielectric constant film has been secured, and there is no particular limitation as long as the material has a Cu barrier property.
  • Any material can be used.
  • a silicon carbide film, a silicon nitride film, etc. can be mentioned.
  • An organic film formed by plasma polymerization is a siloxane-containing organic film such as dibutylsiloxane 'benzoclobutene (DVS-BCB). Also good.
  • DVDS-BCB dibutylsiloxane 'benzoclobutene
  • an example in which the MPS film is processed using a hard mask as a mask is shown, but the MPS may be etched before the resist is stripped.
  • FIGS. 11A to 11H are cross-sectional views illustrating a manufacturing process of the multilayer wiring structure according to the second embodiment of the present invention.
  • the second example is a so-called dual damascene C in which vias and wiring trenches are formed in an insulating film structure of silicon oxide film / B lack Diamond TM / MP S film / Au rora TM / Si CN.
  • via processing is performed, a resist pattern for the wiring groove is formed, and the MPS film is etched using Arno N 2 ZCF 4 plasma while detecting the end point by light emission.
  • the MPS film is etched using Arno N 2 ZCF 4 plasma while detecting the end point by light emission.
  • An MPS film 204 to be an interlayer low dielectric constant film is formed in this order by plasma CVD or the like.
  • a B 1 ack Diamond TM film 305 as a first hard mask and a silicon oxide film 306 as a second hard mask are formed in this order by, for example, a plasma CVD method, and an antireflection film is formed thereon.
  • 307 and via resist 308 are applied in this order to form via resist patterns 308a and 308b.
  • the antireflection film 307 using the via resist patterns 308a and 308b as masks, the antireflection film 307, the silicon oxide film 306, the B lack Diamond TM film 305, the MPS film 204, Au The rora TM membrane 203 is etched in this order.
  • via holes 203a and 203b are formed when ashing is performed using, for example, oxygen plasma.
  • an organic film 309 is applied on the silicon oxide film 306, and a silicon oxide film 310 is formed by, for example, a CVD method.
  • An antireflection film 3 11 and a wiring groove resist 312 are applied in this order on the silicon oxide film 310 to form wiring groove resist patterns 312 a and 312 b.
  • resist patterns 312a and 312b for wiring trenches are used as masks, antireflection film 31 1, silicon oxide film 3 10, organic film 309, silicon oxide film 306, B lack D l Etch the amo nd TM film 305.
  • the wiring groove resist 312 and the antireflection film 311 disappear, and when the silicon oxide film 306 is etched, the silicon oxide film 310 disappears. After the etching process shown, the organic film 309 becomes the top layer.
  • the plasma source is a parallel plate electrode
  • the distance between the electrodes is 35 mm
  • the pressure is 10.6 Pa (80 mTorr)
  • the upper electrode power is 1000 W
  • the bias power is 100 W
  • 2 300/100/25 / 6 sc cm.
  • What is important here is the use of a single carbon atom fluorocarbon and the use of 20% or more and less than 50% nitrogen.
  • the difference in oxide thickness between the wiring side wall and the via side wall is proved by using an interlayer insulating film structure in which Si OCH films having different manufacturing processes and chemical compositions according to the present invention are directly stacked. It becomes.
  • a copper “Cu seed spuck” and Cu plating are performed, and Cu wiring 313 is formed by CMP.
  • the effective dielectric constant can be reduced by scraping the silicon oxide film.
  • a silicon carbonitride film is deposited as a Cu cap film by, for example, the CVD method. By repeating this, multilayer wiring can be formed.
  • the MPS film is shown as the wiring interlayer low dielectric constant film of this example, it is not particularly limited as long as it is a Si OCH film that can secure a sufficient difference in carbon silicon ratio from the via interlayer low dielectric constant film.
  • the carbon silicon ratio of the low dielectric constant film between the wiring layers should be twice or more the carbon Z silicon ratio of the via interlayer low dielectric constant film.
  • the CZS i ratio in the S i OCH film is 1.5 to suppress the oxidation of the wiring trench side wall due to the oxygen ashing process. The above is desirable.
  • an aurora TM film is shown as a low dielectric constant film between via layers.
  • a carbon Z ratio of a low dielectric constant film between wiring layers and a carbon Z ratio of a low dielectric constant film between vias that is, ⁇ (C / S i) Piano (C / S i) wiring ⁇
  • the ratio is preferably 0.5 times or less, and the CZS i ratio in the low dielectric constant film between vias is 1 or less.
  • Si OCH film can be used to apply NCS and other films. Furthermore, a Si OCH film formed by plasma polymerization as shown in Patent Document 1 may be used. In consideration of mounting resistance, it is preferable to select a material having a higher density for the via interlayer low dielectric constant film than for the wiring interlayer low dielectric constant film. Any of the above materials can be used as a low dielectric constant hard mask. Any film that has CMP resistance can be used.
  • the example of using a silicon charcoal kiln film as a Cu cap film shows the etching selection ratio with the low dielectric constant film, and there is no particular limitation as long as it is a Cu barrier material. Any material can be used. Examples include silicon carbide films and silicon nitride films, but even organic films formed by plasma polymerization or siloxane-containing organic films such as divinylsiloxane benzoclobutene (DVS-BCB). Good.
  • the MPS etching may be performed before the resist is stripped.
  • FIG. 12 is a view showing an embodiment in which a copper multilayer wiring is formed on a carbon-containing low dielectric constant insulating film on a MOS FET 403 separated by an element isolation oxide film 402 on a silicon substrate 401.
  • the structural features are shown below. Also in this example, by using mixed gas plasma of Ar / N 2 / CF 4 for MP S etching, in-plane variation, pattern dependence, and wafer-to-wafer 'lot-to-lot variation with less variation Is possible is there.
  • Si OCH film for coating. Further, an Si OCH film formed by plasma polymerization as shown in Patent Document 1 may be used.
  • a silicon oxide film 405 having a W contact plug 404 is formed on the MOSFET 403.
  • the silicon oxide film 405 has a thickness of 30 nm as an etch stop film for a wiring groove corresponding to the first-layer copper wiring 406.
  • a silicon carbon nitride film 413 is formed.
  • a 110 nm thick MPS film 414 and a 30 nm thick BD film 415 are formed as a hard mask on the silicon carbonitride film.
  • the silver wiring of the first layer has a Ta (1 O nm) / TaN (5 nm) barrier in the wiring trench that penetrates the laminated insulating film made of such BD film 41 5 MP S film 414 / silicon carbonitride film 413.
  • a Cu film 421 covered with a film 420 is embedded.
  • This first layer Cu wiring 406 is connected to a W contact plug 404.
  • a 30 nm thick silicon carbonitride film 416 is formed on the first layer Cu wiring 406 as a via etching stop layer. Furthermore, a 150 nm thick Aurora TM film 417 is formed.
  • the Au rora TM film 417 may be planarized by CMP or the like. Further, a 130 nm-thick MPS film 418 and a 30 nm-thick BD film 419 are formed as a hard mask on the Aurora TM film 417. A second Cu wiring 408 in which a Cu film is embedded is formed in the wiring groove that penetrates the BD film 419ZMPS film 418 with respect to the laminated structure insulating film. From the bottom of the second copper wiring 408, a first Cu via plug 407 penetrating through the Aurora TM film 417 and the silicon carbonitride film 416 is formed and connected to the first-layer Cu wiring 406. Yes.
  • the multilayer wiring manufacturing method, multilayer wiring structure, and multilayer wiring manufacturing apparatus of the present invention are applied to semiconductor devices, electronic devices, and their manufacture.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

L'invention concerne une structure de câblage multicouche, dans laquelle on trouve stratifié au moins un élément de circuit formé dans un substrat semi-conducteur ou une couche semi-conductrice, et une pluralité de structures de câblage unitaire ainsi formées sur le substrat semi-conducteur ou la couche semi-conductrice qui sont connectées électriquement avec ledit ou lesdits éléments de circuit mentionnés ci-dessus, et possédant un fil et un bouchon à trou traversant constitué par remplissage d'une rainure de câblage et un trou traversant formé dans un film isolant, avec un fil de métal. Dans cette structure de câblage multicouche, le rapport carbone/silicium dans un film de faible constante diélectrique de couche de câblage intermédiaire est supérieur au rapport carbone/silicium dans un film de faible constante diélectrique de couche traversante intermédiaire. Pour fabriquer la structure de câblage multicouche, un second film de faible constante diélectrique SiOCH superposé est usiné, pour être rainuré et arrêté sur un premier film de faible constante diélectrique SiOCH sous-jacent, en utilisant une détection de point d'extrémité selon une spectroscopie d'émission d'un plasma de gaz mélangé contenant au moins N2 et CHxFy.
PCT/JP2007/061253 2006-06-09 2007-05-29 procédé de fabrication de câblage multicouche, structure DE CÂBLAGE MULTICOUCHE, et appareil DE FABRICATION DE CÂBLAGE MULTICOUCHE WO2007142172A1 (fr)

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JP2010171081A (ja) * 2009-01-20 2010-08-05 Toshiba Corp 半導体装置及びその製造方法
CN102237272A (zh) * 2010-05-07 2011-11-09 瑞萨电子株式会社 半导体装置和半导体装置制造方法
WO2013045854A1 (fr) 2011-09-29 2013-04-04 Ecole Normale Superieure De Lyon Substrat de peptidase fluorogene

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JP2003133411A (ja) * 2001-10-30 2003-05-09 Nec Corp 半導体装置およびその製造方法
WO2005053009A1 (fr) * 2003-11-28 2005-06-09 Nec Corporation Film isolant poreux, son procede de production, et dispositif a semi-conducteur l'utilisant
JP2005191254A (ja) * 2003-12-25 2005-07-14 Fujitsu Ltd 半導体装置の製造方法

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JP4173454B2 (ja) * 1999-06-24 2008-10-29 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
JP2003347279A (ja) * 2002-05-24 2003-12-05 Renesas Technology Corp 半導体装置の製造方法

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JPH07240405A (ja) * 1994-02-25 1995-09-12 Tokyo Electron Ltd エッチング終点検出方法
JPH10261624A (ja) * 1997-03-19 1998-09-29 Nec Corp エッチング方法及び多層配線構造
JP2001093975A (ja) * 1999-09-21 2001-04-06 Toshiba Corp 半導体装置及びその製造方法
JP2003012776A (ja) * 2001-06-29 2003-01-15 Nec Corp 共重合高分子膜の作製方法、前記形成方法で作製される共重合高分子膜、共重合高分子膜を利用する半導体装置
JP2003133411A (ja) * 2001-10-30 2003-05-09 Nec Corp 半導体装置およびその製造方法
WO2005053009A1 (fr) * 2003-11-28 2005-06-09 Nec Corporation Film isolant poreux, son procede de production, et dispositif a semi-conducteur l'utilisant
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JP2010171081A (ja) * 2009-01-20 2010-08-05 Toshiba Corp 半導体装置及びその製造方法
CN102237272A (zh) * 2010-05-07 2011-11-09 瑞萨电子株式会社 半导体装置和半导体装置制造方法
JP2011238704A (ja) * 2010-05-07 2011-11-24 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
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WO2013045854A1 (fr) 2011-09-29 2013-04-04 Ecole Normale Superieure De Lyon Substrat de peptidase fluorogene

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