WO2007142172A1

WO2007142172A1 - Multi-layered wiring manufacturing method, multi-layered wiring structure, and multi-layered wiring manufacturing apparatus

Info

Publication number: WO2007142172A1
Application number: PCT/JP2007/061253
Authority: WO
Inventors: Hiroto Ohtake; Munehiro Tada; Masayoshi Tagami; Yoshihiro Hayashi
Original assignee: Nec Corporation
Priority date: 2006-06-09
Filing date: 2007-05-29
Publication date: 2007-12-13
Also published as: JPWO2007142172A1

Abstract

Provided is a multi-layered wiring structure, in which there are laminated at least one circuit element formed in a semiconductor substrate or a semiconductor layer, and a plurality of unit wiring structures so formed on the semiconductor substrate or the semiconductor layer as are electrically connected with the aforementioned at least one circuit element, and having a wire and a via hole plug formed by filling a wiring groove and a via hole formed in an insulating film, with a metal wire. In this multi-layered wiring structure, the carbon/silicon ratio in an inter-wiring-layer low-dielectric-constant film is higher than the carbon/siliconratio in an inter-via-layer low-dielectric-constant film. In order to manufacture the multi-layered wiring structure, an overlying second SiOCH low-dielectric-constant film is worked, when it is grooved and stopped on an underlying first SiOCH low-dielectric-constant film, by using an end point detection according to an emission spectroscopy of a mixed gas plasma containing at least N2 and CHxFy.

Description

Multilayer wiring manufacturing method, multilayer wiring structure, and multilayer wiring manufacturing apparatus The present invention is based on Japanese Patent Application No. 2 0 0 6-1 6 1 2 0 4 filed on June 9, 2000, And claims the benefit of that priority, the disclosure of which is hereby incorporated by reference in its entirety.

Light

Technical field:

The present invention relates to a multilayer wiring manufacturing method manual having a trench wiring, a multilayer wiring structure, and a multilayer wiring manufacturing apparatus. Background technology:

In recent ultra-LS I devices, since it is necessary to integrate millions of elements on a chip of several mm square, it is indispensable to make the elements finer and multilayer. In particular, reducing the wiring resistance and interlayer capacitance is an important issue in order to increase the device operating speed.

In order to reduce wiring resistance and interlayer capacitance, a method using copper as a wiring material and a film having a dielectric constant lower than that of a silicon oxide film as an interlayer dielectric film is used. Furthermore, the dual damascene method is adopted to reduce the process and wiring resistance. In the dual damascene method, the process of copper embedding and the mechanical and chemical polishing process of copper can be reduced compared to single damascene. In addition, since there is no barrier film above the via, the via resistance can be reduced.

For example, in a typical dual damascene wiring composed of copper low dielectric constant film, a low dielectric constant film such as Cu cap film, Si OCH, etc., formed of material such as Si CN on lower layer wiring 1 Via interlayer low dielectric constant film formed by, etching stopper film formed by inorganic film such as S i O _2, wiring interlayer low dielectric constant film formed by low dielectric constant film such as porous S i OCH, S i Hard mask made of inorganic film such as O ₂ , S i C In the insulating film structure of the Cu cap film formed of materials such as copper, wiring novia composed of copper, Ta / TaN, and other copper barrier films is embedded. .

This structure is formed by a dual damascene method described in Japanese Patent Application No. 2006-001864 (hereinafter referred to as Reference 1). However, in order to lower the dielectric constant between the wiring layers and via layers, it is effective to replace the Cu cap film, etching stopper film, and hard mask made of inorganic film with a low dielectric constant film.

In particular, since an etching stopper film and a hard mask exist between the electrodes, the effective relative permittivity can be reduced by replacing it with a low dielectric constant film. In view of this, studies have been made on a case where there is no etching stopper and the hard mask is a low dielectric constant film hard mask.

However, if the etch stopper film is eliminated, there is no layer that stops etching during groove etching, resulting in in-plane variations and pattern variations. If there is an etching stopper, the stop of etching can be automatically stopped by using the end point detection program of emission spectroscopy, but the end point detection program cannot be used without the etching stopper. Variations in depth between wafers and mouths are likely to occur. For example, a plasma CVD—Si001 ^ film is used as a low dielectric constant film between vias. 11 rora ^TM film, and an MP S film that is a molecular pore film is used as a low dielectric constant film between wiring layers. Consider the case where a tack membrane is used. Using a parallel plate type plasma source, the distance between electrodes 45 m m, the pressure 25mTo rr (3. 33 P a) , the upper electrode power 1 kW, lower electrode Pawa one _{_{150W, N 2 / C 4 F}} 8/0 2 = When grooving MP S using the 150/8/30 sccm condition, the MP S etching end point could not be detected by emission spectroscopy. The same was true for large dilutions with Ar. Disclosure of the invention:

Problems to be solved by the invention: Accordingly, an object of the present invention is to provide a manufacturing method in etching processing that suppresses in-plane variation and pattern variation during groove etching and enables end point detection in dual damascene wiring formed in a low dielectric constant film. Another object of the present invention is to provide a multilayer wiring structure having high insulation between wirings as a result.

Another object of the present invention is to provide a multilayer wiring manufacturing apparatus that enables manufacturing of a multilayer wiring structure by implementing the method for manufacturing a multilayer wiring. Means to solve the problem:

Specifically, a S i OCH film continuum in which a first S i OCH low dielectric constant film located in a lower layer and a second S i OCH low dielectric constant film located in an upper layer are directly laminated, In the multilayer wiring manufacturing method, wherein the carbon silicon ratio of the second S i OCH low dielectric constant film is larger than the carbon Z silicon ratio of the first S i OCH low dielectric constant film, When the second S i OCH low dielectric constant film located in the upper layer is grooved and stopped on the first S i OCH low dielectric constant film located in the lower layer, at least N ₂ and CHX F ₇ are included It is characterized by processing using end point detection by emission spectroscopy of mixed gas plasma. Preferably, the carbon / silicon ratio of the second Si OCH low dielectric constant film located in the upper layer is 2 as compared with the carbon silicon ratio of the first Si OCH low dielectric constant film located in the lower layer. It is characterized by being at least twice as large. CH _x F _y in the mixing force plasma is CF ₄ , CHF ₃ , CH ₂ F ₂ or a mixed gas thereof, and the nitrogen content is preferably 20 to 50%.

Further, a barrier insulating film on a lower layer wiring, a via interlayer low dielectric constant film made of the first S i OCH low dielectric constant film, and a wiring interlayer low dielectric constant film made of the second Si OCH low dielectric constant film A step of sequentially forming a hard mask film, a step of forming a via hole resist pattern on the hard mask film, a step of forming a via hole in the insulating film structure, and removing the via hole resist by oxygen plasma ashing A step of forming a wiring groove resist pattern on the via hole, a step of transferring the wiring groove resist pattern to the hard mask film by dry etching, and removing the wiring groove resist by oxygen plasma ashing. And the second S i O while performing end point detection by emission spectroscopy using a mixed gas plasma containing N ₂ and CHXF y. It is characterized by a step of forming a groove in a low dielectric constant film between via layers made of a CH low dielectric constant film. At this time, the second porous S i OCH film may be composed of a plurality of S i OCH films.

The multilayer wiring structure shown in the present invention is characterized in that the carbon / silicon ratio in the wiring interlayer low dielectric constant film is larger than that in the via interlayer low dielectric constant film. At this time, it is preferable that the carbonosilicon ratio in the wiring interlayer low dielectric constant film is at least twice as large as that in the via interlayer low dielectric constant film. In addition, at least one of the wiring interlayer low dielectric constant film and the via interlayer low dielectric constant film is a porous film containing pores. The wiring interlayer low dielectric constant film is made of Si O C H and has a carbon silicon ratio of 15 or more, may have a 6-membered silica skeleton, or may contain unsaturated hydrocarbons in the film. Further, a structure in which a silicon oxide film is laminated on a wiring interlayer low dielectric constant film may be used. Another feature is that the thickness of the oxidized modified layer formed on the sidewall of the low-dielectric-constant interlayer between the wiring layers is smaller than the thickness of the oxidized modified layer formed on the sidewall of the low-dielectric-layered via layer. It is.

Furthermore, the multilayer wiring manufacturing apparatus shown in the present invention is used for forming an opening in an interlayer insulating film having a laminated structure containing Si OCH as a main component, and the end point from the time variation of the emission intensity of Si F in plasma. And a microcomputer having a program for detecting and automatically stopping the processing having the inside of the interlayer insulating film of the laminated structure as an end point.

The invention's effect:

In accordance with the present invention, in a multilayer wiring using a low dielectric constant film as a wiring Z via interlayer film, there is little in-plane variation and pattern dependency, and there is little variation between wafers and mouths, and the effective dielectric constant is low. Is realized.

Furthermore, according to the present invention, in a multilayer wiring using a low dielectric constant film as a wiring / via interlayer low dielectric constant film, it is possible to form a multilayer wiring with low in-plane variation and pattern dependency and low effective relative dielectric constant. become. Brief description of the drawings: FIG. 1A shows a conventional dual damascene wiring.

Figure 1B shows the structure of the conventional dual damascene interconnect with a lower effective relative permittivity.

Fig. 2 shows the N ₂ flow rate dependence of the etching rate of MP S and Aurora ^™ .

FIG. 3A shows a light emission spectrum in Ar / N ₂ / CF ₄ plasma. FIG. 3B shows the emission spectrum in Ar / Ns / C Fs plasma. Fig. 4 shows the time variation of the emission spectrum at 440 nm during MPS etching.

Fig. 5A shows the CZS i ratio dependence of the lower layer CH of the 440-nm emission spectrum during MPS etching, showing the case of C / S i = 2.22.

Fig. 5B shows the CZS i ratio dependence of the lower layer CH of the 440 nm emission spectrum during MPS etching, showing the case of CZS i = 120.

Fig. 5C shows the CZS i ratio dependence of the time course of the emission spectrum at 440 nm during MPS etching in the lower layer CH, and shows the case of CZS i = 1.41.

Figure 5D shows the CZS i ratio dependence of the lower layer CH of the time change of the emission spectrum of 440 nm during MPS etching, showing the case of CZS i = 1.20.

Figure 6 shows the TDS spectrum after exposing MPS to the etching plasma. Figure 7 shows the N 1 s (XP S) spectrum after exposing MP S and Aurora ^™ to the etching plasma.

Fig. 8A shows the result of TEM-EEL S mapping observed from MPS sidewall after wiring processing.

Fig. 8B is the result of TEM-EELS matbing observation of the composition analysis from the A urora ^TM sidewall after wiring processing.

Fig. 8C is a cross-sectional view of the sample for TEM-EEL S matbing to analyze the composition from the side walls of MP S and Aurora ^TM after wiring processing in Fig. 8A and 8B .

Figure 9 shows the oxide layer on the side wall of MP S, Au rora ^TM after wiring processing. It is an electron micrograph investigated by a computer.

FIG. 10A is a cross-sectional view showing a step of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.

FIG. 10B is a sectional view showing a step subsequent to the first OA diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.

FIG. 1 OC is a sectional view showing a step subsequent to the first OB diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.

FIG. 1 OD is a cross-sectional view showing a step subsequent to the first OC diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.

FIG. 1 OE is a sectional view showing a step subsequent to the first OD diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.

FIG. 10F is a sectional view showing a step subsequent to the first OE diagram of the method for manufacturing the multilayer wiring according to the first example of the present invention.

FIG. 1 OG is a sectional view showing a step subsequent to the first OF diagram of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.

FIG. 10H is a sectional view showing a step subsequent to the first OG diagram of the method for manufacturing the multilayer wiring according to the first embodiment of the present invention.

FIG. 10I is a cross-sectional view showing the next step of FIG. 10H in the method for manufacturing the multilayer wiring according to the first embodiment of the present invention.

FIG. 11A is a cross-sectional view showing one step of a method for manufacturing a multilayer wiring according to a second embodiment of the present invention.

FIG. 11B is a sectional view showing a step subsequent to FIG. 11A of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.

FIGS. 11C to 11H are cross-sectional views showing the next step of FIG. 11B in the multilayer wiring manufacturing method according to the second embodiment of the present invention.

FIG. 11D is a sectional view showing a step subsequent to FIG. 11C of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.

FIG. 11 E is a view of FIG. 11D of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention. It is sectional drawing which shows the next process.

FIG. 11 F is a cross-sectional view showing the next step of FIG. 11 E in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.

FIG. 11 G is a cross-sectional view showing the next step of FIG. 11 F in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.

FIG. 11 H is a cross-sectional view showing the next step of FIG. 11 G in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.

FIG. 11 I is a cross-sectional view showing a step subsequent to FIG. 11 H of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.

FIG. 12 is a view showing a multilayer wiring structure according to a third embodiment of the present invention. Best Mode for Carrying Out the Invention:

Prior to describing the embodiments of the present invention, dual damascene wiring according to the prior art will be described.

Referring to Fig. 1A, in a typical dual damascene wiring structure composed of a copper low dielectric constant film, a Cu cap film formed on the lower wiring 1 with a material such as SiCN. 2, Via interlayer low dielectric constant film formed with low dielectric constant film such as S i OCH 3, Etching stopper film formed with inorganic film such as S i 0 ₂ , Low dielectric constant film such as porous S i OCH In the insulating film structure of the wiring interlayer low dielectric constant film 5, hard mask 6 formed of inorganic film such as Si 0 _2, and Cu cap film 7 formed of material such as Si CN The main wiring is made up of copper 8, Ding 3 Ding 3 ^^, etc. 11 Barrier membrane

The wiring via consisting of 9 is embedded in the structure. This structure is formed by a dual damascene method described in Japanese Patent Application Laid-Open No. 2 004-0 4 7 8 7 3 (hereinafter referred to as Patent Document 1). However, in order to further reduce the dielectric constant between the wiring layers and via layers, it is necessary to replace the Cu cap films 2 and 7 made of inorganic films, the ethine dustper film 4 and the hard mask 6 with low dielectric constant films. It is effective. In particular, since the etching stopper film 4 and the hard mask 6 exist between the electrodes, the effective relative dielectric constant can be reduced by replacing with a low dielectric constant film. Therefore, as shown in Fig. IB, a structure in which there is no etching stopper and the hard mask is a low dielectric constant hard mask 6, is being studied.

Now, an embodiment of the present invention will be described with reference to FIG. 2 to FIG.

The present invention relates to a continuous S i OCH film in which a first S i OCH low dielectric constant film located in a lower layer and a second S i OCH low dielectric constant film located in an upper layer are directly laminated. When the upper S i OCH film is etched with two kinds of S i OCH low dielectric constant films with different carbon silicon ratios (CZS i ratio) in N ₂ ZCH _x F _y mixed gas system, the upper and lower S i OCH films This is based on the discovery that the etching selectivity can be secured and the end point can be detected by emission spectroscopy.

In the multilayer wiring manufacturing method of the present invention, for example, a plasma CVD-Si001 "1 film is used as a low dielectric constant film between vias, 11 rora ^TM film, and a molecular thin film is formed as a wiring interlayer low dielectric constant film. MP S _ S i OCH film (Mo 1 ecu 1 ar Por S tack film, hereinafter simply referred to as “MP S”) is used, where carbon in the MP S _ S i O CH film Silicon ratio = 2.7, carbon silicon ratio in Aurora ^™ film (plasma CVD—Si OCH film) is larger than 0.7, and film 2 is used as a hard mask.

In the method for forming a multilayer wiring according to the present invention, etching is performed using a mixed gas plasma composed of fluorocarbon made of single carbon atoms such as CF ₄ and 20 to 50% nitrogen gas.

FIG. 2 is a graph showing the dependency of Si OCH (Au rora ™, MPS) etching rate on a nitrogen addition amount evaluated with a blanket wafer. Referring to Fig. 2, using a parallel plate etching apparatus, the distance between electrodes is 35 mm, the pressure is 6.65 5 Pa (5 OmTorr), the upper electrode power is 1 ◦ 0 0 W, the lower electrode power is 100 W, It was determined etching rate under the conditions of _{_{a r / N 2 / CF 4}} /0 2 = 3 0 0/1 0 0/2 5/6 sccm. With Au rora ^TM , the etching rate decreases due to the nitrogen content, whereas with MP S, the etching rate increases. Further, when etching a groove pattern in S i 0 ₂ hardmask 1 as MP S / Au rora ^TM etching selectivity. It is confirmed that 7 or more can be secured. By controlling the nitrogen gas flow rate in this way, MPS etching can be stopped on Aurora ^™ . In this way, it is found that even a Si OCH film continuum can detect a change in the CZSi ratio, and the etching end point can be detected. Furthermore, when a single carbon atom such as CF ₄ (C _x F _y : x = 1) is used as the fluorocarbon gas, the emission spectrum such as SiF becomes clear and the end point by emission spectroscopy is obtained. Detection is easy. FIGS. 3A and 3B are diagrams showing a 440 nm emission spectrum when the MPS substrate and the silicon substrate are etched by adding C ₄ F ₈ gas or CF 4 gas. Referring to Fig. 3A and Fig. 3B, C ₄ F ₈ has a molecular emission spectrum from a polymer fluorocarbon over a wide band, so the emission at 440 nm tends to be buried. If CF 4 is used, it can be clearly confirmed.

Figure 4 performs a groove exposed on the structure of _{S i 0 2 / MP S /} Au rora TM, and Regis Toatsushingu after etching the S i O 2 hard mask, and MP S etched by S i O ₂ Hadomasu click It is a diagram observing the time change of the 440 nm emission spectrum. Referring to FIG. 4, etching is performed using a parallel plate etching apparatus, the distance between electrodes is 35 mm, the pressure is 6.65 Pa (50 mTorr), the upper electrode power is 1 000 W, the lower electrode power is 1 00W, were carried out under the conditions of _{_{a r / N 2 / CF 4}} / O 2 = 300/1 00/25/6 secm. When the MP S etching is completed, the emission spectrum at 440 nm indicating Si F increases. This is because Aurora ^TM has a smaller C / Si ratio than MP S. The value obtained by differentiating the 440 nm emission spectrum is also shown. By adjusting the etching time using this light emission spectrum or its differential value, variations in etching depth between wafers and mouths can be suppressed.

Fig. 5A shows Fig. 5B, Fig. 5C, Fig. 5D shows the structure of S i 0 ₂ / MP s / S i OCH, and the CZS i ratio of S i OCH is C / S i = 2.22 , 1. 5 3, 1. 4 1, 1. 20 groove exposure was performed on each sample, S i O ₂ hard mask was etched, resist ashing was performed, and S i 0 ₂ MP S etch with hard mask The results of observing the temporal change of the 440 nm emission spectrum are shown. The C / Si ratio of MP S is 27. The lower the 3 i ratio of Si i 011 in the lower layer, the larger the time change of the spectrum at 440 nm. When the C / Si ratio is 1.4 or less, the time change is particularly large.

From this result, it is understood that the C / Si ratio of the upper S i OCH (here MP S) is preferably about twice that of the lower layer in the S i OCH film continuum.

For these reasons, etching of MP S with a gas such as Ar / N ₂ / CF ₄ can secure a selection ratio with the lower layer of Au rora ^TM film, and the S i OCH film can be obtained by emission spectroscopy. Because it is a continuum, for example, it is possible to detect the end point of etching of two types of Si OCH low dielectric constant films made of the same material, so there is little pattern variation if there is in-plane variation, and variation between wafers and mouths. Fewer grooves can be machined.

Further, as shown in FIG. 6, in terms of F occlusion, Ar N ₂ ^/ / CF ₄ is superior ArZ N2 Bruno C ₄ F _8. 〇 ₄ compared to the Flip _4?! Is (weak binding energy) showing the easy dissociation reaction for, from C ₄ F ₈ is for CF ₂ Ya CF, F radicals in a large amount occurs. It can be seen that addition of CF ₄ is preferable because when fluorine is incorporated into the Si OCH film, adhesion is deteriorated or HF is formed by moisture absorption to form a void in the film. Furthermore, in the etching efficiency of the film, CF ₃ ions are known to be higher than CF ₂ and CF ion, CF ₄ is added to generate a CF ₃ ions.

By the way, in a carbon-rich CZSi ratio> 1 S i OCH film, a carbonitride film is formed on the side wall when plasma etching is performed with a C _x H _y ZN ₂ gas.

Figure 7 shows the N 1 s spectrum observed on the surface after irradiation with etching plasma using XPS. In the MP S film (ie, in the S i OCH film with a C / Si ratio> 1), a spectrum of N 1 s is observed after irradiation. This carbonitride film is completely removed in the oxygen ashing process that follows the etching process, but it has the effect of suppressing carbon extraction from the side walls of the Si OCH film. That is, the amount of oxidation of the side wall after oxygen ashing is suppressed. This effect increases as the amount of carbon in the S i OCH film increases. This was remarkable, and the one containing unsaturated hydrocarbons in the film was even more remarkable. This is presumably because the unsaturated hydrocarbons in the film react with the N radicals in the etching plasma, making it easy to form a carbonitride film. Moreover, the detailed cause is not clear, but the carbon skeleton has a CZSi ratio> 1 S i OCH film with a silica skeleton in a ring, or a 6-membered ring (S i ₃ O ₃ ). There was also a tendency to suppress the amount of oxidation on the side walls.

The wiring interlayer low dielectric constant film, which is a carbon-rich S i OCH film characteristic of the present invention, and the via interlayer low dielectric constant film, which is a silicon-rich (CZS i 1) S i OCH film, are directly laminated. For each of the structures, an opening made of a wiring groove and a via is formed. The wiring interlayer low dielectric constant film, which is a carbon-rich S i OCH film, suppresses the amount of oxidation on the side walls, and is thinner than the amount of oxidation on the via sidewalls.

8A and 8B are diagrams showing the results of analyzing the composition of the MPS film and the Aurora ^TM film by TEM_EELS mapping after forming Cu wiring on the pattern exposed to the assin plasma after etching. Figure 8C is a cross-sectional view of the sample for TEM-EEL S mapping.

Fig. 9 is an electron micrograph of Cu wiring formed on the pattern exposed to ashing plasma after etching, and the oxide layer on the side wall of MPS, Aurora ^™ after wiring processing was investigated by hydrofluoric acid dip.

From MP S sidewall at up to about 10 nm while changing the C and O is within, deep C or 〇 up to about 30 nm has changed in the case of using the Au RORA ^TM, oxidation reforming layer It can be seen that the thickness of is large. Such a difference in the amount of oxidation can be easily confirmed by dibbing the device cross section with a dilute hydrofluoric acid solution. Characteristic carbon structure of this structure S i OCH, silicon rich S i OCH laminated structure Resist is embedded after dual damascene processing, after forming the cross section of the wiring, in an aqueous solution containing 6% HF, 30% NH ₄ F for 5 seconds The result of dibbing is shown. An oxide layer can be observed on the Au rora ^TM side wall and the bottom of the trench. In MPS, almost no modified layer is confirmed. Since the amount of oxidation of the low dielectric constant film between wiring layers can be reduced, it is possible to form a Cu / 1 ow-k wiring while suppressing an increase in effective dielectric constant. According to the present invention, in multi-layer wiring using a low dielectric constant film as a wiring layer opening film, groove depth pattern variation, in-plane variation, wafer-to-lot variation, and low effective relative dielectric constant are reduced. Wiring can be formed.

Example:

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First example)

In the first embodiment, an Sio ₂ hard mask will be described.

FIGS. 1A to 1H are cross-sectional views illustrating a manufacturing process of a multilayer wiring structure according to the first embodiment of the present invention. In the first example, via processing was performed in forming a so-called dual damascene Cu wiring in which a via and a wiring trench were formed in an insulating film structure of a silicon oxide film ZMPS film Au rora ™ / SiCN. After that, a resist pattern for the wiring trench is formed, and the MPS film is etched by using Ar ZN ₂ ZC F ₄ plasma to detect the end point by light emission. · It is possible to perform grooving with little variation between the mouthpieces.

First, as shown in Fig. 10A, the silicon carbonitride film 202 to be the copper cap film on the lower wiring 201, the Aurora ^TM film 203 to be the low dielectric constant film between the vias, and the wiring interlayer low dielectric An MPS film 204, which is an index film, and a silicon oxide film 205, which is a hard mask, are formed in this order by, for example, a plasma CVD method, and an antireflection film 206 and a via resist 2007 are formed thereon. By sequentially coating, via resist patterns 2 0 7 a and 2 0 7 b are formed.

Next, as shown in FIG. 10 B, using the via resist patterns 2 0 7 a and 2 0 7 b as masks, the antireflection film 2 0 6, silicon oxide film 2 0 5, MPS film 2 04, A The urora ^TM film 203 is etched in this order.

Thereafter, as shown in FIG. 10C, for example, by performing ashing with oxygen plasma or the like, via hole patterns 2 0 3 a and 2 0 3 b are formed.

Thereafter, as shown in FIG. 10D, an organic film 2 08 is applied on the silicon oxide film 2 05 and a silicon oxide film 2 09 is formed by, eg, CVD. silicon On the oxide film 209, an antireflection film 210 and a wiring groove resist 211 are applied in this order to form wiring groove resist patterns 21 1a and 21 1b.

As shown in FIG. 10E, the antireflection film 210, the silicon oxide film 209, the organic film 208, and the silicon oxide film 205 are etched using the wiring groove resist patterns 21 1a and 21 1b as masks. When etching the organic film 208, the interconnect trench resist 211 and the antireflection film 210 disappear, and when the silicon oxide film 205 is etched, the silicon oxide film 209 disappears. Therefore, the etching shown in FIG. 10E After the addition, the organic film 208 becomes the top layer.

Thereafter, as shown in FIG. 10F, when the organic film 208 is etched by, for example, oxygen plasma, wiring groove hard mask patterns 205a and 205b to which the wiring groove pattern is transferred can be formed.

Further, as shown in FIG. 10G, the MPS film 204 is etched using Ar ZNzZC F ₄ plasma using the wiring groove hard mask patterns 205a and 205b as a mask. At this time, the plasma source was a parallel plate electrode, the distance between the electrodes was 35 mm, the pressure was 10.6 Pa (80 mTorr), the upper electrode power was 1000 W, the bias power was 100 W, Ar / N ₂ / CF ₄ / For example, 0 ₂ = 300/100/25 6 sc cm. What is important here is the use of a single carbon atom fluorocarbon and the use of 20% or more and less than 50% nitrogen. This is because the use of a single carbon atom fluorocarbon makes it easier to detect the end point by emission spectroscopy, and the inclusion of nitrogen makes it possible to secure a selection ratio with the lower layer Aurora ^™ film. Using these conditions, it is possible to easily observe changes in light emission such as Si F = 440 nm, so that the end point can be detected, and processing with less in-plane variation, pattern variations, wafer-to-lot, and lot-to-lot variations is possible. It becomes possible. Also, the Cu cap film 202 disappears during this etching.

Thereafter, as shown in 10H diagram for removing deposition material, slightly irradiating the cleaning plasma containing 0 _2. At this time, a thin oxide layer is formed on the MPS side wall 204 'with C / S i = 2.7 and carbon rich, compared to C / S i = 0.7 and the aurora ^TM side wall 203' with silicon rich. The Low dielectric constant film between wiring layers Since the oxidation-modified layer is thin, the relative dielectric constant can be kept low. Such a difference in the amount of oxidation between the wiring part and the via part can be easily confirmed by dipping in a dilute hydrofluoric acid solution with respect to the fracture surface of the device. For example, it can be confirmed by dubbing for 3 seconds for 5 seconds in an aqueous solution containing 6% HF and 30% NH ₄ F. Conversely, the difference in oxide thickness between the wiring side wall and the via side wall is evidence that the manufacturing process according to the present invention and an interlayer insulating film structure in which Si OCH films having different chemical compositions are directly stacked are used. It becomes. Thereafter, as shown in FIG. 10I, noria 'Cu seed sputtering and Cu plating are performed, and Cu wiring 212 is formed by CMP. Furthermore, a silicon carbonitride film is deposited as a Cu cap film by, for example, the CVD method. By repeating this, multilayer wiring can be formed.

Although the MPS film is shown as the wiring interlayer low dielectric constant film in this example, a sufficient difference in carbonosilicon ratio from the via interlayer low dielectric constant film can be secured. The same materials as above can be applied. Desirably, the carbon silicon ratio of the low dielectric constant film between the wiring layers should be at least twice the carbon silicon ratio of the low dielectric constant film between the vias.

In addition, in the case of dual damascene opening pattern formation using the end point detection method that monitors this plasma emission, the CZS i ratio in the S i OCH film is 1.5 to suppress the oxidation of the wiring trench sidewall due to the oxygen-ashing process. The above is desirable.

On the other hand, as a via interlayer low dielectric constant film of this example exhibited A urora ^TM film, via interlayer low dielectric constant film carbon emissions silicon ratio to carbon / silicon ratio of wiring interlayer low dielectric constant film, i.e. {( C / S i) Piano (CZS i) Wiring} The ratio is preferably 0.5 times or less. CZS i ratio in via interlayer low dielectric constant film is 1 or less Japan ASM Aurora series, Tricon Orion, A pp 1 ied Materials BD / BD II, Novellus Cora 1 C VD_ S i OCH film, Dow—Chica ica 1 Porous S i LK: Can be applied to NCS, etc. Furthermore, a Si OCH film formed by plasma polymerization as shown in Patent Document 1 may be used. Considering mounting resistance, the low dielectric constant film between via layers is lower than the low dielectric constant film between wiring layers. It is preferred to select a material with a high density.

In this example, the silicon carbonitride film was used as the Cu cap film, but the etching selectivity with the low dielectric constant film has been secured, and there is no particular limitation as long as the material has a Cu barrier property. Any material can be used. For example, a silicon carbide film, a silicon nitride film, etc. can be mentioned. An organic film formed by plasma polymerization is a siloxane-containing organic film such as dibutylsiloxane 'benzoclobutene (DVS-BCB). Also good. Furthermore, in this embodiment, an example in which the MPS film is processed using a hard mask as a mask is shown, but the MPS may be etched before the resist is stripped.

(Second embodiment)

In the second embodiment of the present invention, a 1 ow-k hard mask will be described.

FIGS. 11A to 11H are cross-sectional views illustrating a manufacturing process of the multilayer wiring structure according to the second embodiment of the present invention. The second example is a so-called dual damascene C in which vias and wiring trenches are formed in an insulating film structure of silicon oxide film / B lack Diamond ™ / MP S film / Au rora ™ / Si CN. In forming the wiring, via processing is performed, a resist pattern for the wiring groove is formed, and the MPS film is etched using Arno N ₂ ZCF ₄ plasma while detecting the end point by light emission. In addition to performing groove processing with little pattern dependency, and lowering the dielectric constant of the hard mask, we further confirmed the decrease in effective dielectric constant.

First, as shown in FIG. 11A, as in the first embodiment, a silicon carbonitride film 202 serving as a copper cap film on the lower layer wiring 201, Aurora ™ S1203 serving as a low dielectric constant film between vias, wiring An MPS film 204 to be an interlayer low dielectric constant film is formed in this order by plasma CVD or the like. Furthermore, a B 1 ack Diamond ^™ film 305 as a first hard mask and a silicon oxide film 306 as a second hard mask are formed in this order by, for example, a plasma CVD method, and an antireflection film is formed thereon. 307 and via resist 308 are applied in this order to form via resist patterns 308a and 308b. Next, as shown in FIG. 11B, using the via resist patterns 308a and 308b as masks, the antireflection film 307, the silicon oxide film 306, the B lack Diamond ^TM film 305, the MPS film 204, Au The rora ^TM membrane 203 is etched in this order.

Thereafter, as shown in FIG. 11C, via holes 203a and 203b are formed when ashing is performed using, for example, oxygen plasma.

Thereafter, as shown in FIG. 11D, an organic film 309 is applied on the silicon oxide film 306, and a silicon oxide film 310 is formed by, for example, a CVD method. An antireflection film 3 11 and a wiring groove resist 312 are applied in this order on the silicon oxide film 310 to form wiring groove resist patterns 312 a and 312 b.

As shown in Fig. 11 E, resist patterns 312a and 312b for wiring trenches are used as masks, antireflection film 31 1, silicon oxide film 3 10, organic film 309, silicon oxide film 306, B lack D l Etch the amo nd ^TM film 305. When etching the organic film 309, the wiring groove resist 312 and the antireflection film 311 disappear, and when the silicon oxide film 306 is etched, the silicon oxide film 310 disappears. After the etching process shown, the organic film 309 becomes the top layer.

Thereafter, as shown in FIG. 11F, when the organic film 309 is ashed by, for example, oxygen plasma, wiring groove hard mask patterns 305a and 305b to which the wiring groove pattern is transferred can be formed.

Furthermore, as shown in 1 1 G diagram, the interconnection trench hard mask Pas Kuhn 305 a, 305 b as a mask, the MPS film 204 eight 1: Roh ^ ₂ Ji? ₄ Etch using plasma. At this time, the plasma source is a parallel plate electrode, the distance between the electrodes is 35 mm, the pressure is 10.6 Pa (80 mTorr), the upper electrode power is 1000 W, the bias power is 100 W, Ar N ₂ / CF ₄ / O _{For example, 2} = 300/100/25 / 6 sc cm. What is important here is the use of a single carbon atom fluorocarbon and the use of 20% or more and less than 50% nitrogen. Using single carbon atom fluorocarbon makes it easier to detect the end point by emission spectroscopy, This is because the selection ratio with the lower layer Aurora ^™ membrane can be ensured by containing nitrogen. Using these conditions, it is possible to easily observe changes in light emission such as Si F = 440 nm, so that the end point can be detected, and processing with less in-plane variation, pattern variations, wafer-to-lot, and lot-to-lot variations is possible. It becomes possible.

Further, as shown in FIG. 1 1 H, the Cu cap film 202 disappears during this etching. Then, to remove the deposition was slightly irradiating the cleaning plasmas containing 0 _2. At this time, a thin oxide layer is formed on the C / S i = 2.7 and carbon-rich MP S side wall 204 ′, compared to CZS i = 0.7 and silicon-rich Aurora ^TM side wall 203 ′. The Since the oxidized modified layer in the low dielectric constant film between the wiring layers is thin, an increase in the effective relative dielectric constant can be suppressed. Such a difference in the oxidation amount between the wiring portion and the via portion can be easily confirmed by dipping in a dilute hydrofluoric acid solution with respect to the fracture surface of the device. For example, it can be confirmed by dipping for 3 to 5 seconds in an aqueous solution containing 6% HF and 30% NH ₄ F. On the other hand, the difference in oxide thickness between the wiring side wall and the via side wall is proved by using an interlayer insulating film structure in which Si OCH films having different manufacturing processes and chemical compositions according to the present invention are directly stacked. It becomes.

After this, as shown in FIG. 11 I, a copper “Cu seed spuck” and Cu plating are performed, and Cu wiring 313 is formed by CMP. At this time, the effective dielectric constant can be reduced by scraping the silicon oxide film. Furthermore, a silicon carbonitride film is deposited as a Cu cap film by, for example, the CVD method. By repeating this, multilayer wiring can be formed.

Although the MPS film is shown as the wiring interlayer low dielectric constant film of this example, it is not particularly limited as long as it is a Si OCH film that can secure a sufficient difference in carbon silicon ratio from the via interlayer low dielectric constant film. The same material as above can be applied. Desirably, the carbon silicon ratio of the low dielectric constant film between the wiring layers should be twice or more the carbon Z silicon ratio of the via interlayer low dielectric constant film. In addition, in the case of dual damascene opening pattern formation using the final inspection method that monitors this plasma emission, the CZS i ratio in the S i OCH film is 1.5 to suppress the oxidation of the wiring trench side wall due to the oxygen ashing process. The above is desirable. As an example, an aurora ^TM film is shown as a low dielectric constant film between via layers. For example, a carbon Z ratio of a low dielectric constant film between wiring layers and a carbon Z ratio of a low dielectric constant film between vias, that is, {(C / S i) Piano (C / S i) wiring} The ratio is preferably 0.5 times or less, and the CZS i ratio in the low dielectric constant film between vias is 1 or less. Trion's Orion, Ap p 1 ied Materials BD ^ BDII, Novella's Cora 1 etc. C VD—S i OCH film, Dow—Ch em ica 1 杜 Porous S i LK: Si OCH film can be used to apply NCS and other films. Furthermore, a Si OCH film formed by plasma polymerization as shown in Patent Document 1 may be used. In consideration of mounting resistance, it is preferable to select a material having a higher density for the via interlayer low dielectric constant film than for the wiring interlayer low dielectric constant film. Any of the above materials can be used as a low dielectric constant hard mask. Any film that has CMP resistance can be used.

In this example, the example of using a silicon charcoal kiln film as a Cu cap film shows the etching selection ratio with the low dielectric constant film, and there is no particular limitation as long as it is a Cu barrier material. Any material can be used. Examples include silicon carbide films and silicon nitride films, but even organic films formed by plasma polymerization or siloxane-containing organic films such as divinylsiloxane benzoclobutene (DVS-BCB). Good.

Further, in this embodiment, an example in which the MPS film is processed using a hard mask as a mask is shown, but the MPS etching may be performed before the resist is stripped.

(Third embodiment)

In the third embodiment, a multilayer structure will be described.

FIG. 12 is a view showing an embodiment in which a copper multilayer wiring is formed on a carbon-containing low dielectric constant insulating film on a MOS FET 403 separated by an element isolation oxide film 402 on a silicon substrate 401. The structural features are shown below. Also in this example, by using mixed gas plasma of Ar / N ₂ / CF ₄ for MP S etching, in-plane variation, pattern dependence, and wafer-to-wafer 'lot-to-lot variation with less variation Is possible is there. This shows the case where an Au rora ^TM film is used as a low dielectric constant film between via layers, an MPS film is used as an interlayer film for wiring trenches, and a BD ^TM film is used as a low-k pad mask. Oricon from ricon, BD / BD II from Applied Materials, CORA 1 from Novella's COR-Si OCH film, Dow-Chemica 1 porous S i LK, NCS from Catalytic Chemicals It is also possible to use a Si OCH film for coating. Further, an Si OCH film formed by plasma polymerization as shown in Patent Document 1 may be used. A silicon oxide film 405 having a W contact plug 404 is formed on the MOSFET 403. The silicon oxide film 405 has a thickness of 30 nm as an etch stop film for a wiring groove corresponding to the first-layer copper wiring 406. A silicon carbon nitride film 413 is formed. A 110 nm thick MPS film 414 and a 30 nm thick BD film 415 are formed as a hard mask on the silicon carbonitride film. The silver wiring of the first layer has a Ta (1 O nm) / TaN (5 nm) barrier in the wiring trench that penetrates the laminated insulating film made of such BD film 41 5 MP S film 414 / silicon carbonitride film 413. A Cu film 421 covered with a film 420 is embedded. This first layer Cu wiring 406 is connected to a W contact plug 404. A 30 nm thick silicon carbonitride film 416 is formed on the first layer Cu wiring 406 as a via etching stop layer. Furthermore, a 150 nm thick Aurora ™ film 417 is formed. The Au rora ^™ film 417 may be planarized by CMP or the like. Further, a 130 nm-thick MPS film 418 and a 30 nm-thick BD film 419 are formed as a hard mask on the Aurora ^™ film 417. A second Cu wiring 408 in which a Cu film is embedded is formed in the wiring groove that penetrates the BD film 419ZMPS film 418 with respect to the laminated structure insulating film. From the bottom of the second copper wiring 408, a first Cu via plug 407 penetrating through the Aurora ^™ film 417 and the silicon carbonitride film 416 is formed and connected to the first-layer Cu wiring 406. Yes.

Au rora ^TM film 41 7 Oxide modified layer 422 exists on the side wall of the oxygen plasma cleaning process, and MP S film 418 side wall has an oxidized modified layer 4 thinner than 422. There are 23. Such a difference in the amount of oxidation between the wiring portion and the via portion can be easily confirmed by dibbing with a dilute hydrofluoric acid aqueous solution on the fracture surface of the device. For example, it can be confirmed by dipping for 3 to 5 seconds in an aqueous solution containing 6% HF and 30% NH ₄ F. Conversely, the difference in oxide thickness between the wiring side wall and the via side wall is evidence that the manufacturing process according to the present invention and an interlayer insulating film structure in which Si OCH films having different chemical compositions are directly laminated are used. Become. The same structure as the second wiring layer 408 and the via plug 40 7 can be formed for the Cu wiring layer 410 of the third layer and the Cu via plug 409 connecting the third layer and the second layer. Multi-layer wiring can be formed by overlapping. Industrial applicability:

As described above, the multilayer wiring manufacturing method, multilayer wiring structure, and multilayer wiring manufacturing apparatus of the present invention are applied to semiconductor devices, electronic devices, and their manufacture.

Claims

The scope of the claims

1. A continuous S i OCH film in which a first S i OCH low dielectric constant film located in a lower layer and a second S i OCH low dielectric constant film located in an upper layer are directly laminated, In the multilayer wiring manufacturing method, the carbon / silicon ratio of the second S i OCH low dielectric constant film is larger than the carbon silicon ratio of the S i OCH low dielectric constant film of When the second S i OCH low dielectric constant film is grooved and stopped on the first S i OCH low dielectric constant film located in the lower layer, a mixed gas plasma containing at least N ₂ and CH _x F _y A method of manufacturing a multilayer wiring, characterized by processing using end point detection by emission spectroscopy.

2. The method for manufacturing a multilayer wiring according to claim 1, wherein a carbon silicon ratio of a second Si OCH low dielectric constant film located in the upper layer of the two types of low dielectric constant films is Multilayer wiring manufacturing method characterized by being at least twice as large as the carbon silicon ratio of the first S i OCH low dielectric constant film located in the lower layer

3. The method for producing a multilayer wiring according to claim 1 or 2, wherein the mixed gas plasma has a nitrogen content of 20% to 50%.

4. The method for manufacturing a multilayer wiring according to any one of claims 1 to 3, wherein CH _x F _y is CF ₄ , CHF ₃ , CH ₂ F _{2 or} these in the mixed gas plasma. A method for producing a multilayer wiring, wherein the mixed gas is a mixed gas.

5. The method for manufacturing a multilayer wiring according to claim 1, wherein a barrier insulating film is formed on a lower wiring, and the via interlayer low dielectric is formed of the first Si OCH low dielectric constant film. An insulating film, a wiring interlayer low dielectric constant film made of the second S i OCH low dielectric constant film, a step of forming a hard mask film, a step of forming a via hole resist pattern on the hard mask film, A step of forming a via hole in the film structure; a step of removing a via hole resist by oxygen plasma ashing; a step of forming a wiring groove resist pattern on the via hole; and the wiring groove resist pattern by dry etching. Transferring to the hard mask film, and oxygen plasma atssin And a via layer formed of the second Si OCH low dielectric constant film while performing end point detection by emission spectroscopy using a mixed gas plasma containing N ₂ and CH _x F _y. A method of manufacturing a multilayer wiring, characterized by a step of performing a groove force check in a low dielectric constant film.

6. The method for manufacturing a multilayer wiring according to any one of claims 1 to 5, wherein a barrier insulating film is formed on a lower wiring, and the via interlayer low dielectric is formed of the first Si OCH low dielectric constant film. A step of sequentially forming a dielectric constant film, a wiring interlayer low dielectric constant film made of the second S i OCH low dielectric constant film, a hard mask film made of the third S i OCH low dielectric constant film, and an inorganic hard mask film; A step of forming a via hole resist pattern on the inorganic hard mask, a step of forming a via hole in the insulating film structure, a step of removing the via hole resist by oxygen plasma ashing, and a wiring on the via hole A step of forming a groove resist pattern, a step of transferring the wiring groove resist pattern to the hard mask film made of the inorganic and third Si OCH low dielectric constant films by dry etching, and an oxygen plasma etching process. Thing Thus removing the wiring trench resist, N ₂ and CH _x F end point detection by emission spectroscopy using a mixed gas plasma containing _y rows Rere while 1 Ji said second S I_〇 low dielectric 3 i OCH low A method of manufacturing a multilayer wiring, characterized by comprising a step of forming a groove in a low dielectric constant film between via layers made of a dielectric constant film.

7. At least one circuit element formed on a semiconductor substrate or semiconductor layer, and a multilayer wiring structure formed on the semiconductor substrate or on the semiconductor layer in a state of being electrically connected to the at least one circuit element In a multilayer wiring structure in which a plurality of unit wiring structures having wiring grooves formed in an insulating film and via holes filled with metal wiring and via hole plugs are stacked, a low dielectric constant between wiring layers A multilayer wiring structure characterized in that the carbon silicon ratio in the film is larger than the carbon silicon ratio in the low dielectric constant film between the via layers.

8. The multilayer wiring structure according to claim 7, wherein a carbon z silicon ratio in the wiring interlayer low dielectric constant film is at least twice as large as a carbon no silicon ratio in the via interlayer low dielectric constant film. A multilayer wiring structure characterized by that.

9. The multilayer wiring structure according to any one of claims 7 and 8, wherein the wiring layer A multilayer wiring structure characterized in that at least one of a low dielectric constant film and a low dielectric constant film between vias is a porous film containing pores.

10. The multilayer wiring structure according to any one of claims 7 to 9, wherein the wiring interlayer low dielectric constant film is made of Si OCH, and a carbon Z silicon ratio thereof is 15 or more. Multi-layer wiring structure characterized by

1 1. The multilayer wiring structure according to any one of claims 7 to 10, wherein the wiring interlayer low dielectric constant film is made of Si OCH, the carbon Z silicon ratio is 1 or more, and A multilayer wiring structure characterized by having a silica skeleton.

1 2. The multilayer wiring structure according to any one of claims 7 to 11, wherein the wiring interlayer low dielectric constant film is made of Si OCH, and the carbon / silicon ratio is 15 or more. A multilayer wiring structure characterized by having a six-membered cyclic silica skeleton composed of three silicon atoms and three oxygen atoms.

13. The multilayer wiring structure according to any one of claims 7 to 12, wherein the wiring interlayer low dielectric constant film contains an unsaturated hydrocarbon.

14. The multilayer wiring structure according to any one of claims 7 to 13, wherein a silicon oxide film is laminated on the wiring interlayer low dielectric constant film. Construction.

15. The multilayer wiring structure according to any one of claims 7 to 14, wherein the thickness between the wiring layers is lower than a thickness of an oxidation modified layer formed on a sidewall of the via interlayer low dielectric constant film. A multilayer wiring structure characterized in that an oxidation-modified layer formed on a side wall of a dielectric constant film is thin.

16 6. For the opening process starting from the inside of the interlayer insulating film directly laminated with Si OCH films with different chemical compositions, the final inspection is performed automatically from the time variation of the emission intensity of Si F in the plasma. A multilayer wiring manufacturing apparatus provided with a microcomputer having a program to be stopped automatically.