JPWO2007142172A1 - Multilayer wiring manufacturing method, multilayer wiring structure and multilayer wiring manufacturing apparatus - Google Patents
Multilayer wiring manufacturing method, multilayer wiring structure and multilayer wiring manufacturing apparatus Download PDFInfo
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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Abstract
多層配線構造は、半導体基板又は半導体層に形成された少なくとも１つの回路素子と、前記少なくとも１つの回路素子に電気的に接続された状態で前記半導体基板上又は前記半導体層上に形成され、絶縁膜に形成される配線溝およびビア孔に金属配線を充填して形成された配線およびビア孔プラグを有する単位配線構造が複数積層される。この多層配線構造において、配線層間低誘電率膜中のカーボン／シリコン比がビア層間低誘電率膜中のカーボン／シリコン比に比べて大きい。この多層配線構造を製造するには、上層に位置する第２のＳｉＯＣＨ低誘電率膜を溝加工して前記下層に位置する第１のＳｉＯＣＨ低誘電率膜上で停止させる際、Ｎ２とＣＨｘＦｙを少なくとも含む混合ガスプラズマの発光分光による終点検出を用いて加工する。The multilayer wiring structure is formed on the semiconductor substrate or on the semiconductor layer in a state of being electrically connected to the at least one circuit element formed on the semiconductor substrate or the semiconductor layer. A plurality of unit wiring structures having wiring and via hole plugs formed by filling the wiring grooves and via holes formed in the film with metal wiring are stacked. In this multilayer wiring structure, the carbon / silicon ratio in the wiring interlayer low dielectric constant film is larger than the carbon / silicon ratio in the via interlayer low dielectric constant film. In order to manufacture this multilayer wiring structure, when the second SiOCH low dielectric constant film located in the upper layer is grooved and stopped on the first SiOCH low dielectric constant film located in the lower layer, N2 and CHxFy are Processing is performed using endpoint detection by emission spectroscopy of at least mixed gas plasma.
Description
本発明は、２００６年６月９日に提出された日本国特許出願第２００６−１６１２０４号に基づき、且つ、その優先権の恩恵を主張するものであり、その開示は、参照することによりここにその全体を組み入れる。
技術分野：
本発明は溝配線を有する多層配線製造方法と多層配線構造と多層配線製造装置に関する。The present invention is based on Japanese Patent Application No. 2006-161204 filed on June 9, 2006 and claims the benefit of its priority, the disclosure of which is hereby incorporated by reference. Incorporate the whole.
Technical field:
The present invention relates to a multilayer wiring manufacturing method having a trench wiring, a multilayer wiring structure, and a multilayer wiring manufacturing apparatus.
近年の超ＬＳＩデバイスでは、数ｍｍ角のチップに数百万個以上の素子を集積する必要があるため、素子を微細化、多層化することが不可欠である。特にデバイス動作速度の高速化のため、配線抵抗および層間容量の低減が重要な課題となる。
配線抵抗および層間容量の低減のために、銅を配線材料に、シリコン酸化膜より誘電率の低い膜を層間絶線膜に用いる方法が用いられている。さらには、工程の低減、配線抵抗低減のため、デュアルダマシン工法が採用されている。デュアルダマシン工法では、シングルダマシンに比べて銅の埋め込み工程や銅の機械的化学的研磨工程が削減できるなど、工程が大きく短縮される。また、ビア上部のバリア膜が存在しないため、ビア抵抗が低減できる。
例えば、銅／低誘電率膜で構成された一般的なデュアルダマシン配線では、下層配線１の上にＳｉＣＮなどの材料で形成されるＣｕキャップ膜、ＳｉＯＣＨなどの低誘電率膜で形成されるビア層間低誘電率膜、ＳｉＯ２などの無機膜で形成されるエッチングストッパー膜、ポーラスＳｉＯＣＨなどの低誘電率膜で形成される配線層間低誘電率膜、ＳｉＯ２などの無機膜で形成されるハードマスク、ＳｉＣＮなどの材料で形成されるＣｕキャップ膜の絶縁膜構造内に、主たる配線を構成する銅、Ｔａ／ＴａＮなどのＣｕバリア膜で構成される配線／ビアが埋め込まれた構造になっている。
この構造は特願２００６−００１８６４号公報（以下、参考文献１と呼ぶ）などに記載されているデュアルダマシン方法によって形成される。しかし、さらに配線層間やビア層間の誘電率を下けるには、無機膜で構成されているＣｕキャップ膜や、エッチングストッパー膜、ハードマスクを低誘電率膜に置き換えるのが効果的である。
特にエッチングストッパー膜やハードマスクは電極間に存在するため、低誘電率膜に置き換えると実効的な比誘電率が低減できる。そこで、エッチングストッパーがなく、ハードマスクも低誘電率膜ハードマスクになっているものも検討されている。
しかしながら、エッチストッパー膜をなくすと、溝エッチング時のエッチングを停止する層がなく、結果として面内ばらつきやパターンばらつきを生じやすい。また、エッチングストッパーがある場合には、エッチングの停止を発光分光の終点検出プログラムを用いることで自動的に停止することができるが、エッチングストッパーがないと終点検出プログラムを用いることができず、ウエハ間やロット間の深さばらつきが生じやすくなる。例えば、ビア層間低誘電率膜としてプラズマＣＶＤ−ＳｉＯＣＨ膜であるＡｕｒｏｒａＴＭ膜、配線層間低誘電率膜として分子細孔膜であるＭＰＳ膜（Ｍｏｌｅｃｕｌａｒ Ｐｏｒｅ Ｓｔａｃｋ 膜）を使用する場合を考える。平行平板型のプラズマ源を用いて、電極間距離４５ｍｍ、圧力２５ｍＴｏｒｒ（３．３３Ｐａ）、上部電極パワー１ｋＷ、下部電極パワー１５０Ｗ、Ｎ２／Ｃ４Ｆ８／Ｏ２＝１５０／８／３０ｓｃｃｍの条件を用いてＭＰＳに溝加工を行う場合、ＭＰＳエッチング終点を発光分光で検出することはできなかった。Ａｒで大量希釈した場合にも同じであった。In recent VLSI devices, since it is necessary to integrate several million elements or more on a chip of several mm square, it is indispensable to miniaturize and multilayer the elements. In particular, reduction of wiring resistance and interlayer capacitance is an important issue in order to increase device operation speed.
In order to reduce wiring resistance and interlayer capacitance, a method of using copper as a wiring material and a film having a dielectric constant lower than that of a silicon oxide film as an interlayer dielectric film is used. Furthermore, a dual damascene method is employed to reduce processes and reduce wiring resistance. In the dual damascene method, the copper embedding process and the copper mechanical chemical polishing process can be reduced compared to the single damascene process. In addition, since there is no barrier film above the via, the via resistance can be reduced.
For example, in a general dual damascene wiring composed of a copper / low dielectric constant film, a via cap formed of a Cu cap film formed of a material such as SiCN on the lower wiring 1 and a low dielectric constant film of SiOCH or the like. Interlayer low dielectric constant film, etching stopper film formed of inorganic film such as SiO 2 , wiring interlayer low dielectric constant film formed of low dielectric constant film such as porous SiOCH, hard formed of inorganic film such as SiO 2 In the insulating film structure of the Cu cap film formed of a material such as a mask or SiCN, a structure in which wirings / vias composed of copper and Ta barrier layers such as Ta / TaN are embedded in the main wirings. Yes.
This structure is formed by a dual damascene method described in Japanese Patent Application No. 2006-001864 (hereinafter referred to as Reference Document 1). However, in order to further lower the dielectric constant between the wiring layers and via layers, it is effective to replace the Cu cap film, the etching stopper film, and the hard mask made of an inorganic film with a low dielectric constant film.
In particular, since an etching stopper film and a hard mask exist between the electrodes, the effective relative dielectric constant can be reduced by replacing with a low dielectric constant film. In view of this, studies have been made on a case in which there is no etching stopper and the hard mask is a low dielectric constant film hard mask.
However, when the etch stopper film is eliminated, there is no layer that stops the etching at the time of groove etching, and as a result, in-plane variations and pattern variations are likely to occur. If there is an etching stopper, the etching stop can be automatically stopped by using an end point detection program of emission spectroscopy. However, if there is no etching stopper, the end point detection program cannot be used, and the wafer is stopped. Variations in depth between lots and lots are likely to occur. For example, consider a case where an Aurora ™ film, which is a plasma CVD-SiOCH film, is used as a low interlayer dielectric film, and an MPS film (Molecular Pore Stack film), which is a molecular pore film, is used as a low interlayer dielectric film. Using a parallel plate type plasma source, the distance between the electrodes is 45 mm, the pressure is 25 mTorr (3.33 Pa), the upper electrode power is 1 kW, the lower electrode power is 150 W, and N 2 / C 4 F 8 / O 2 = 150/8/30 sccm. When groove processing was performed on MPS using conditions, the MPS etching end point could not be detected by emission spectroscopy. The same was true when diluted in large quantities with Ar.
そこで、本発明の一目的は、低誘電率膜中に形成されるデュアルダマシン配線において、溝エッチング時の面内ばらつきやパターンばらつきを抑制し、かつ、終点検出を可能にするエッチング加工における製造方法と、結果として形成される配線間絶縁性の高い多層配線構造とを提供することにある。
また、本発明のもう一つの目的は、前記多層配線の製造方法を実施することによって多層配線構造の製造を可能にする多層配線製造装置を提供することにある。Accordingly, an object of the present invention is to provide a manufacturing method in etching processing that suppresses in-plane variation and pattern variation during groove etching and enables end point detection in dual damascene wiring formed in a low dielectric constant film. Another object of the present invention is to provide a multilayer wiring structure having high insulation between wirings as a result.
Another object of the present invention is to provide a multi-layer wiring manufacturing apparatus that enables a multi-layer wiring structure to be manufactured by carrying out the multi-layer wiring manufacturing method.
具体的には、下層に位置する第１のＳｉＯＣＨ低誘電率膜と上層に位置する第２のＳｉＯＣＨ低誘電率膜とが直接積層されたＳｉＯＣＨ膜連続体であって、前記第１のＳｉＯＣＨ低誘電率膜のカーボン／シリコン比よりも前記第２のＳｉＯＣＨ低誘電率膜のカーボン／シリコン比が大きいことを特徴とする多層配線の製造方法において、前記上層に位置する第２のＳｉＯＣＨ低誘電率膜を溝加工して前記下層に位置する第１のＳｉＯＣＨ低誘電率膜上で停止させる際、Ｎ２とＣＨＸＦ７を少なくとも含む混合ガスプラズマの発光分光による終点検出を用いて加工することを特徴とする。好ましくは、前記上層に位置する第２のＳｉＯＣＨ低誘電率膜のカーボン／シリコン比が、前記下層に位置する第１のＳｉＯＣＨ低誘電率膜のカーボン／シリコン比に比べて２倍以上大きいことを特徴とする。混合カスプラズマ中のＣＨｘＦｙはＣＦ４、ＣＨＦ３、ＣＨ２Ｆ２あるいはこれらの混合ガスであって、窒素の含有量は２０から５０％であるのが好ましい。
さらには、下層配線上にバリア絶縁膜、前記第１のＳｉＯＣＨ低誘電率膜からなるビア層間低誘電率膜、前記第２のＳｉＯＣＨ低誘電率膜からなる配線層間低誘電率膜、ハードマスク膜を順に形成する工程と、前記ハードマスク膜上にビア孔レジストパターンを形成する工程と、絶縁膜構造内にビア孔を形成する工程と、酸素プラズマアッシングによってビア孔レジストを除去する工程と、前記ビア孔上に配線溝レジストパターンを形成する工程と、前記配線溝レジストパターンをドライエッチングによって前記ハードマスク膜に転写する工程と、酸素プラズマアッシングによって配線溝レジストを除去する工程と、Ｎ２とＣＨｘＦｙを含む混合ガスプラズマを用いて発光分光による終点検出を行いながら前記第２のＳｉＯＣＨ低誘電率膜からなるビア層間低誘電率膜内に溝加工を行う工程とを特徴とする。このとき、第２のポーラスＳｉＯＣＨ膜は複数のＳｉＯＣＨ膜から構成されていても良い。
また、本発明で示される多層配線構造は、配線層間低誘電率膜中のカーボン／シリコン比がビア層間低誘電率膜中に比べて大きいことを特徴とする。このとき、配線層間低誘電率膜中のカーボン／シリコン比がビア層間低誘電率膜中に比べて２倍以上大きいことが好ましい。また、記配線層間低誘電率膜およびビア層間低誘電率膜の少なくとも１種類は空孔を内含するポーラス膜であることを特徴とする。配線層間低誘電率膜はＳｉＯＣＨから構成され、そのカーボン／シリコン比が１５以上であり、６員環シリカ骨格を有したり、膜中に不飽和炭化水素を含んでいてもよい。さらには、配線層間低誘電率膜の上にシリコン酸化膜が積層されている構造でも良い。また、ビア層間低誘電率膜の側壁に形成される酸化改質層の厚さよりも前記配線層間低誘電率膜の側壁に形成される酸化改質層の厚さが薄いことも特徴のひとつである。
さらには、本発明で示される多層配線製造装置は、ＳｉＯＣＨを主成分とする積層構造の層間絶縁膜に開口部形成に用いられ、プラズマ中のＳｉＦの発光強度の時間変化から終点検出を行って、前記積層構造の層間絶縁膜内部を終点とする加工を自動的に停止させるプログラムを有するマイクロコンピュータを備えていることを特徴とする。Specifically, the first SiOCH low dielectric constant film located in the lower layer and the second SiOCH low dielectric constant film located in the upper layer are directly laminated, and the first SiOCH low dielectric constant is formed. In the method of manufacturing a multilayer wiring, wherein the carbon / silicon ratio of the second SiOCH low dielectric constant film is larger than the carbon / silicon ratio of the dielectric constant film, the second SiOCH low dielectric constant located in the upper layer When the film is grooved and stopped on the first SiOCH low dielectric constant film positioned in the lower layer, the film is processed using end point detection by emission spectroscopy of mixed gas plasma containing at least N 2 and CHXF 7 And Preferably, the carbon / silicon ratio of the second SiOCH low dielectric constant film located in the upper layer is at least twice as large as the carbon / silicon ratio of the first SiOCH low dielectric constant film located in the lower layer. Features. CH x F y in the mixed casplasm is CF 4 , CHF 3 , CH 2 F 2 or a mixed gas thereof, and the nitrogen content is preferably 20 to 50%.
Furthermore, a barrier insulating film on the lower layer wiring, a via interlayer low dielectric constant film made of the first SiOCH low dielectric constant film, a wiring interlayer low dielectric constant film made of the second SiOCH low dielectric constant film, and a hard mask film Forming a via hole resist pattern on the hard mask film, forming a via hole in the insulating film structure, removing the via hole resist by oxygen plasma ashing, Forming a wiring groove resist pattern on the via hole; transferring the wiring groove resist pattern to the hard mask film by dry etching; removing the wiring groove resist by oxygen plasma ashing; and N 2 and CHxFy The second SiOCH low dielectric constant film while detecting the end point by emission spectroscopy using a mixed gas plasma containing And a step of forming a groove in the via interlayer low dielectric constant film. At this time, the second porous SiOCH film may be composed of a plurality of SiOCH films.
The multilayer wiring structure shown in the present invention is characterized in that the carbon / silicon ratio in the wiring interlayer low dielectric constant film is larger than that in the via interlayer low dielectric constant film. At this time, the carbon / silicon ratio in the wiring interlayer low dielectric constant film is preferably at least twice as large as that in the via interlayer low dielectric constant film. In addition, at least one of the wiring interlayer low dielectric constant film and the via interlayer low dielectric constant film is a porous film including pores. The wiring interlayer low dielectric constant film is made of SiOCH, has a carbon / silicon ratio of 15 or more, may have a six-membered silica skeleton, or may contain unsaturated hydrocarbons in the film. Further, a structure in which a silicon oxide film is laminated on a wiring interlayer low dielectric constant film may be used. Another feature is that the thickness of the oxidation-modified layer formed on the sidewall of the low-dielectric-constant interlayer between the wiring layers is smaller than the thickness of the oxidation-modified layer formed on the sidewall of the low-dielectric-layer interlayer. is there.
Furthermore, the multilayer wiring manufacturing apparatus shown in the present invention is used for forming an opening in an interlayer insulating film having a laminated structure mainly composed of SiOCH, and performs end point detection from time variation of the emission intensity of SiF in plasma. And a microcomputer having a program for automatically stopping processing having the inside of the interlayer insulating film of the laminated structure as an end point.
本発明により、低誘電率膜を配線／ビア層間膜に用いた多層配線において、面内ばらつきやパターン依存性が少なく、ウエハ間・ロット間ばらつきも少なく、実効比誘電率が低い多層配線が実現される。
さらに、本発明によれば、低誘電率膜を配線／ビア層間低誘電率膜に用いた多層配線において、面内ばらつきやパターン依存性が少なく、実効比誘電率が低い多層配線形成が可能になる。In accordance with the present invention, multilayer wiring using a low dielectric constant film as a wiring / via interlayer film has less in-plane variation and pattern dependency, less wafer-to-lot and lot-to-lot variation, and realizes a multilayer wiring with a low effective relative dielectric constant. Is done.
Furthermore, according to the present invention, in multilayer wiring using a low dielectric constant film as a wiring / via interlayer low dielectric constant film, it is possible to form a multilayer wiring with low in-plane variation and pattern dependency and low effective relative dielectric constant. Become.
第１Ａ図は従来のデュアルダマシン配線を示す図である。
第１Ｂ図は従来の従来のデュアルダマシン配線のより実効比誘電率を下げた構造を示す図である。
第２図はＭＰＳ、ＡｕｒｏｒａＴＭのエッチング速度のＮ２流量依存性を示した図である。
第３Ａ図はＡｒ／Ｎ２／ＣＦ４プラズマ中の発光スペクトルを示す図である。
第３Ｂ図はＡｒ／Ｎ２／Ｃ４Ｆ８プラズマ中の発光スペクトルを示す図である。
第４図はＭＰＳエッチング時の発光スペクトル４４０ｎｍの時間変化を示す図である
第５Ａ図はＭＰＳエッチング時の発光スペクトル４４０ｎｍの時間変化の下層膜ＣＨのＣ／Ｓｉ比依存性を示す図で、Ｃ／Ｓｉ＝２．２２の場合を示す。
第５Ｂ図はＭＰＳエッチング時の発光スペクトル４４０ｎｍの時間変化の下層膜ＣＨのＣ／Ｓｉ比依存性を示す図で、Ｃ／Ｓｉ＝１．２０の場合を示す。
第５Ｃ図はＭＰＳエッチング時の発光スペクトル４４０ｎｍの時間変化の下層膜ＣＨのＣ／Ｓｉ比依存性を示す図で、Ｃ／Ｓｉ＝１．４１の場合を示す。
第５Ｄ図はＭＰＳエッチング時の発光スペクトル４４０ｎｍの時間変化の下層膜ＣＨのＣ／Ｓｉ比依存性を示す図で、Ｃ／Ｓｉ＝１．２０の場合を示す。
第６図はＭＰＳをエッチングプラズマに曝した後のＴＤＳスペクトルである。
第７図はＭＰＳ，ＡｕｒｏｒａＴＭをエッチングプラズマに曝した後のＮｌｓ（ＸＰＳ）スペクトルである。
第８Ａ図は配線加工後のＭＰＳ側壁からの組成分析をＴＥＭ−ＥＥＬＳマッピングによって観察した結果の図である。
第８Ｂ図は配線加工後のＡｕｒｏｒａＴＭ側壁からの組成分析をＴＥＭ−ＥＥＬＳマッピングによって観察した結果の図である。
第８Ｃ図は第８Ａ図及び第８Ｂ図の配線加工後のＭＰＳ，ＡｕｒｏｒａＴＭの各側壁からの組成分析を行うためのＴＥＭ−ＥＥＬＳマッピングの為の試料の断面図である。
第９図は配線加工後のＭＰＳ，ＡｕｒｏｒａＴＭの側壁の酸化層をフッ酸ディップによって調査した電子顕微鏡写真である。
第１０Ａ図は本発明の第１の実施例による多層配線の製造方法の一工程を示す断面図である。
第１０Ｂ図は本発明の第１の実施例による多層配線の製造方法の第１０Ａ図の次の工程を示す断面図である。
第１０Ｃ図は本発明の第１の実施例による多層配線の製造方法の第１０Ｂ図の次の工程を示す断面図である。
第１０Ｄ図本発明の第１の実施例による多層配線の製造方法の第１０Ｃ図の次の工程を示す断面図である。
第１０Ｅ図は本発明の第１の実施例による多層配線の製造方法の第１０Ｄ図の次の工程を示す断面図である。
第１０Ｆ図本発明の第１の実施例による多層配線の製造方法の第１０Ｅ図の次の工程を示す断面図である。
第１０Ｇ図は本発明の第１の実施例による多層配線の製造方法の第１０Ｆ図の次の工程を示す断面図である。
第１０Ｈ図は本発明の第１の実施例による多層配線の製造方法の第１０Ｇ図の次の工程を示す断面図である。
第１０Ｉ図は本発明の第１の実施例による多層配線の製造方法の第１０Ｈ図の次の工程を示す断面図である。
第１１Ａ図は本発明の第２の実施例による多層配線の製造方法の一工程を示す断面図である。
第１１Ｂ図は本発明の第２の実施例による多層配線の製造方法の第１１Ａ図の次の工程を示す断面図である。
第１１Ｃ図乃至第１１Ｈ図は本発明の第２の実施例による多層配線の製造方法を第１１Ｂ図の次の工程を示す断面図である。
第１１Ｄ図は本発明の第２の実施例による多層配線の製造方法の第１１Ｃ図の次の工程を示す断面図である。
第１１Ｅ図は本発明の第２の実施例による多層配線の製造方法の第１１Ｄ図の次の工程を示す断面図である。
第１１Ｆ図は本発明の第２の実施例による多層配線の製造方法の第１１Ｅ図の次の工程を示す断面図である。
第１１Ｇ図は本発明の第２の実施例による多層配線の製造方法の第１１Ｆ図の次の工程を示す断面図である。
第１１Ｈ図は本発明の第２の実施例による多層配線の製造方法の第１１Ｇ図の次の工程を示す断面図である。
第１１Ｉ図は本発明の第２の実施例による多層配線の製造方法の第１１Ｈ図の次の工程を示す断面図である。
第１２図は本発明の第３の実施例による多層配線構造を示す図である。FIG. 1A shows a conventional dual damascene wiring.
FIG. 1B is a diagram showing a structure in which the effective relative dielectric constant is lowered than that of a conventional conventional dual damascene wiring.
FIG. 2 is a graph showing the N 2 flow rate dependency of the etching rate of MPS and Aurora ™ .
FIG. 3A is a diagram showing an emission spectrum in Ar / N 2 / CF 4 plasma.
FIG. 3B is a diagram showing an emission spectrum in Ar / N 2 / C 4 F 8 plasma.
FIG. 4 is a diagram showing the time change of the emission spectrum 440 nm at the time of MPS etching. FIG. 5A is a diagram showing the C / Si ratio dependency of the time change of the emission spectrum 440 nm at the time of MPS etching of the lower layer film CH. The case of /Si=2.22 is shown.
FIG. 5B is a graph showing the C / Si ratio dependency of the lower layer film CH of the time change of the emission spectrum of 440 nm during the MPS etching, and shows the case of C / Si = 1.20.
FIG. 5C is a graph showing the C / Si ratio dependency of the lower layer film CH of the time change of the emission spectrum of 440 nm during the MPS etching, and shows the case of C / Si = 1.41.
FIG. 5D is a diagram showing the C / Si ratio dependence of the lower layer film CH of the time change of the emission spectrum of 440 nm during MPS etching, and shows the case where C / Si = 1.20.
FIG. 6 is a TDS spectrum after exposing MPS to etching plasma.
FIG. 7 is a Nls (XPS) spectrum after exposing MPS, Aurora ™ to etching plasma.
FIG. 8A is a diagram showing a result of TEM-EELS mapping observing composition analysis from the MPS side wall after wiring processing.
FIG. 8B is a diagram showing the result of TEM-EELS mapping observing the composition analysis from the Aurora TM side wall after wiring processing.
FIG. 8C is a cross-sectional view of a sample for TEM-EELS mapping for performing composition analysis from each side wall of MPS and Aurora ™ after wiring processing of FIGS. 8A and 8B.
FIG. 9 is an electron micrograph in which the oxide layer on the side wall of MPS, Aurora ™ after wiring processing is examined by hydrofluoric acid dip.
FIG. 10A is a cross-sectional view showing a step of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 10B is a sectional view showing a step subsequent to FIG. 10A of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 10C is a sectional view showing a step subsequent to FIG. 10B of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 10D is a sectional view showing a step subsequent to FIG. 10C of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 10E is a sectional view showing a step subsequent to FIG. 10D of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 10F is a sectional view showing a step subsequent to FIG. 10E in the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 10G is a sectional view showing a step subsequent to FIG. 10F of the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 10H is a sectional view showing a step subsequent to FIG. 10G in the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 10I is a sectional view showing a step subsequent to FIG. 10H in the method for manufacturing a multilayer wiring according to the first embodiment of the present invention.
FIG. 11A is a cross-sectional view showing one step of a method for manufacturing a multilayer wiring according to a second embodiment of the present invention.
FIG. 11B is a sectional view showing a step subsequent to FIG. 11A in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
FIGS. 11C to 11H are cross-sectional views showing the next step of FIG. 11B in the multilayer wiring manufacturing method according to the second embodiment of the present invention.
FIG. 11D is a sectional view showing a step subsequent to FIG. 11C in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
FIG. 11E is a sectional view showing a step subsequent to FIG. 11D in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
FIG. 11F is a sectional view showing a step subsequent to FIG. 11E in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
FIG. 11G is a sectional view showing a step subsequent to FIG. 11F of the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
FIG. 11H is a sectional view showing a step subsequent to FIG. 11G in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
FIG. 11I is a cross-sectional view showing the next step of FIG. 11H in the method for manufacturing a multilayer wiring according to the second embodiment of the present invention.
FIG. 12 shows a multilayer wiring structure according to the third embodiment of the present invention.
本発明の実施例を説明する前に、従来技術によるデュアルダマシン配線について説明する。
第１Ａ図を参照すると、銅／低誘電率膜で構成された一般的なデュアルダマシン配線の構造では、下層配線１の上にＳｉＣＮなどの材料で形成されるＣｕキャップ膜２、ＳｉＯＣＨなどの低誘電率膜で形成されるビア層間低誘電率膜３、ＳｉＯ２などの無機膜で形成されるエッチングストッパー膜４、ポーラスＳｉＯＣＨなどの低誘電率膜で形成される配線層間低誘電率膜５、ＳｉＯ２などの無機膜で形成されるハードマスク６、ＳｉＣＮなどの材料で形成されるＣｕキャンプ膜７の絶縁膜構造内に、主たる配線を構成する銅８、Ｔａ／ＴａＮなどのＣｕバリア膜９で構成される配線／ビアが埋め込まれた構造になっている。この構造は特開２００４−０４７８７３号公報（以下、特許文献１と呼ぶ）などに記載されているデュアルダマシン方法によって形成される。しかし、さらに配線層間やビア層間の誘電率を下げるには、無機膜で構成されているＣｕキャップ膜２と７や、エッチングストッパー膜４、ハードマスク６を低誘電率膜に置き換えるのが効果的である。特にエッチングストッパー膜４やハードマスク６は電極間に存在するため、低誘電率膜に置き換えると実効的な比誘電率が低減できる。
そこで、第１Ｂ図に示すように、エッチングストッパーがなく、ハードマスクも低誘電率膜ハードマスク６’になっている構造が検討されている。
それでは、本発明の実施例について第２図乃至第１２図を参照しながら説明する。
本発明は、下層に位置する第１のＳｉＯＣＨ低誘電率膜と上層に位置する第２のＳｉＯＣＨ低誘電率膜とが直接積層されたＳｉＯＣＨ膜連続体において、膜中のカーボン／シリコン比（Ｃ／Ｓｉ比）が異なる２種類のＳｉＯＣＨ低誘電率膜をＮ２／ＣＨｘＦｙ混合ガス系で上層のＳｉＯＣＨ膜をエッチングすると、上層と下層のＳｉＯＣＨ膜のエッチング選択比が確保できるとともに、発光分光による終点検出が可能であるという発見に基づく。
また、本発明の多層配線の製造方法では、例えばビア層間低誘電率膜としてプラズマＣＶＤ−ＳｉＯＣＨ膜であるＡｕｒｏｒａＴＭ膜、配線層間低誘電率膜として分子細孔膜であるＭＰＳ−ＳｉＯＣＨ膜（Ｍｏｌｅｃｕｌａｒ Ｐｏｒｅ Ｓｔａｃｋ膜、以後単に“ＭＰＳ”と記す）を使用する。ここで、ＭＰＳ−ＳｉＯＣＨ膜中のカーボン／シリコン比＝２．７であり、ＡｕｒｏｒａＴＭ膜（プラズマＣＶＤ−ＳｉＯＣＨ膜）中のカーボン／シリコン比＝０．７よりも大きい。ハードマスクとしては膜２を使用する。
本発明の多層配線の形成方法では、ＣＦ４などの単炭素原子からなるフルオロカーボンと２０から５０％の窒素ガスからなる混合ガスプラズマを用いてエッチング加工を行う。
第２図は、ブランケットウエハーで評価したＳｉＯＣＨ（ＡｕｒｏｒａＴＭ、ＭＰＳ）エッチング速度の窒素添加量依存性を示す図である。第２図を参照すると、平行平板のエッチング装置を用いて、電極間距離３５ｍｍ、圧力６．６５Ｐａ（５０ｍＴｏｒｒ）、上部電極パワー１０００Ｗ、下部電極パワー１００Ｗ、Ａｒ／Ｎ２／ＣＦ４／Ｏ２＝３００／１００／２５／６ｓｃｃｍの条件でエッチング速度を求めた。ＡｕｒｏｒａＴＭでは窒素含有によりエッチング速度が低下するのに対し、ＭＰＳではエッチング速度が増加する。また、ＳｉＯ２ハードマスクで溝パターンをエッチングした場合には、ＭＰＳ／ＡｕｒｏｒａＴＭエッチング選択比として１．７以上が確保できることを確認している。このように窒素ガス流量を制御することにより、ＭＰＳエッチングをＡｕｒｏｒａＴＭ上で停止させることが可能になる。このように、ＳｉＯＣＨ膜連続体であっても、そのＣ／Ｓｉ比の変化を検出しうることを見出し、エッチングの終点検出が可能となる。さらには、ＣＦ４などの単炭素原子（ＣｘＦｙ：ｘ＝１）をフルオロカーボンガスとして用いた場合、ＳｉＦなどの発光スペクトルが明瞭になり、発光分光による終点検出が容易になる。
第３Ａ図及び第３Ｂ図は、ＭＰＳ基板とシリコン基板のエッチングを、Ｃ４Ｆ８ガスあるいはＣＦ４ガス添加で行った場合の４４０ｎｍ発光スペクトルを示す図である。第３Ａ図及び第３Ｂ図を参照すると、Ｃ４Ｆ８では高分子フルオロカーボンからの分子性発光スペクトルが広い帯域にわたり存在するため、４４０ｎｍの発光も埋もれてしまいやすいが、ＣＦ４を用いた場合には、はっきりと確認できる。
第４図はＳｉＯ２／ＭＰＳ／ＡｕｒｏｒａＴＭの構造上に溝露光を行い、ＳｉＯ２ハードマスクをエッチングした後レジストアッシングして、ＳｉＯ２ハードマスクでＭＰＳエッチングした場合の４４０ｎｍ発光スペクトルの時間変化を観察した図である。第４図を参照すると、エッチングは、平行平板のエッチング装置を用いて、電極間距離３５ｍｍ、圧力６．６５Ｐａ（５０ｍＴｏｒｒ）、上部電極パワー１０００Ｗ、下部電極パワー１００Ｗ、Ａｒ／Ｎ２／ＣＦ４／Ｏ２＝３００／１００／２５／６ｓｃｃｍの条件で行った。ＭＰＳのエッチングが終了すると、ＳｉＦを示す４４０ｎｍの発光スペクトルは増大する。これは、ＭＰＳよりもＡｕｒｏｒａＴＭの方がＣ／Ｓｉ比が小さいためである。４４０ｎｍの発光スペクトルを微分した値も併記したが、大きく変化している。この発光スペクトル、あるいはその微分値を用いてエッチング時間を調整することで、エッチング深さのウエハ間ばらつきやロットばらつきを抑制できる。
第５Ａ図は、第５Ｂ図、第５Ｃ図、第５Ｄ図はＳｉＯ２／ＭＰｓ／ＳｉＯＣＨの構造でＳｉＯＣＨのＣ／Ｓｉ比をＣ／Ｓｉ＝２．２２、１．５３，１．４１，１．２０と夫々変化させたサンプル上に溝露光を行い、ＳｉＯ２ハードマスクをエッチングした後レジストアッシングして、ＳｉＯ２ハードマスクでＭＰＳエッチングした場合の４４０ｎｍ発光スペクトルの時間変化を観察した結果を夫々示している。ＭＰＳのＣ／Ｓｉ比は２７である。下層のＳｉＯＣＨのＣ／Ｓｉ比が低いほど４４０ｎｍのスペクトルの時間変化は大きい。Ｃ／Ｓｉ比が１．４以下では特に時間変化が大きく観察される。
この結果から、ＳｉＯＣＨ膜連続体において上層のＳｉＯＣＨ（ここではＭＰＳ）のＣ／Ｓｉ比が下層の約２倍程度であるのが好ましいことがわかる。
これらのことから、ＭＰＳのエッチングをＡｒ／Ｎ２／ＣＦ４などのガスでエッチングすると、下層ＡｕｒｏｒａＴＭ膜との選択比が確保できるとともに、発光分光により、ＳｉＯＣＨ膜連続体であり、たとえば同質材料からなる２種類のＳｉＯＣＨ低誘電率膜のエッチングの終点検出も可能になるため、面内ばらつきやパターンばらつきが少なく、ウエハ間・ロット間ばらつきの少ない溝加工が可能になる。
また、第６図に示すように、Ｆ吸蔵の観点からも、Ａｒ／Ｎ２／ＣＦ４がＡｒ／Ｎ２／Ｃ４Ｆ８よりも優れている。ＣＦ４に比べてＣ４ＦＲは容易に解離反応を示す（結合エネルギーが弱い）ため、Ｃ４Ｆ８からはＣＦ２やＣＦ、Ｆラジカルが多量に発生するためである。ＳｉＯＣＨ膜中にフッ素が取り込まれると密着性を劣化させたり、膜吸湿によりＨＦが形成され膜中にボイドを形成させたりするため、ＣＦ４添加が好ましいことがわかる。さらには、膜のエッチング効率においては、ＣＦ３イオンがＣＦ２やＣＦイオンよりも高いことが知られており、ＣＦ３イオンを発生させるＣＦ４添加が好ましい。
ところで、カーボンリッチのＣ／Ｓｉ比＞１のＳｉＯＣＨ膜では、ＣｘＨｙ／Ｎ２系ガスでプラズマエッチングを行うと側壁に炭窒化皮膜が形成される。
第７図はエッチングプラズマに照射後の表面をＸＰＳを用いてＮ１ｓスペクトルを観察した図を示す。ＭＰＳ膜では、（すなわちＣ／Ｓｉ比＞１のＳｉＯＣＨ膜では）Ｎ１ｓのスペクトルが照射後に観察される。この炭窒化皮膜はエッチング工程後に続く酸素アッシング工程において完全に除去されるが、ＳｉＯＣＨ膜側壁からの炭素引き抜きを抑制する効果がある。すなわち、酸素アッシング後の側壁の酸化量が抑制される。この効果は、ＳｉＯＣＨ膜中のカーボン量が多いほど顕著であり、膜中に不飽和炭化水素が含まれている方がさらに顕著であった。これは、膜中の不飽和炭化水素がエッチングプラズマ中のＮラジカルと反応しやすく、炭窒化被膜が形成しやすいためと推察される。また、その詳細な原因は明らかではないが、カーボンリッチのＣ／Ｓｉ比＞１のＳｉＯＣＨ膜のシリカ骨格が環状、さらには６員環（Ｓｉ３Ｏ３）の場合酸素アッシング後の側壁の酸化量が抑制される傾向も認められた。
さて、本願発明で特徴的なカーボンリッチなＳｉＯＣＨ膜である配線層間低誘電率膜とシリコンリッチ（Ｃ／Ｓｉ＜１）のＳｉＯＣＨ膜であるビア層間低誘電率膜とを直接積層した構造に対して、それぞれ配線溝とビアとからなる開口部を形成する。カーボンリッチなＳｉＯＣＨ膜である配線層間低誘電率膜ではその側壁の酸化量が抑制され、ビア側壁の酸化量よりも薄くなる。
第８Ａ図及び第８Ｂ図はエッチング後にアッシングプラズマを曝したパターン上にＣｕ配線を形成し、ＴＥＭ−ＥＥＬＳマッピングによりＭＰＳ膜及びＡｕｒｏｒａＴＭ膜を組成分析した結果を夫々示す図で、第８Ｃ図はＴＥＭ−ＥＥＬＳマッピングのための試料の断面図ある。
第９図はエッチング後にアッシングプラズマを曝したパターン上にＣｕ配線を形成し、配線加工後のＭＰＳ，ＡｕｒｏｒａＴＭの側壁の酸化層をフッ酸ディップによって調査した電子顕微鏡写真である。
ＭＰＳでは側壁から１０ｎｍ程度までにＣやＯの変化が収まっているのに対し、ＡｕｒｏｒａＴＭを用いた場合には３０ｎｍ程度まで深くＣや○が変化しており、酸化改質層の厚みが大きいことがわかる。このような酸化量の違いはデバイスの被断面に対して希フッ酸水溶液にディッピングすることで容易に確認できる。本構造で特徴的なカーボンリッチＳｉＯＣＨ／シリコンリッチＳｉＯＣＨ積層構造でデュアルダマシン加工後にレジストを埋め込み、配線の被断面形成後、６％ＨＦ，３０％ＮＨ４Ｆを含む水溶液に５秒ディッピングした結果を示す。ＡｕｒｏｒａＴＭ側壁やトレンチ底面には酸化層が確認できる。ＭＰＳではほとんど改質層は確認されない。配線層間低誘電率膜の酸化量が少なく形成できるため、実効比誘電率の増加を抑制しつつ、Ｃｕ／ｌｏｗ−ｋ配線を形成できる構造になっている。
本発明によれば、低誘電率膜を配線層開膜に用いた多層配線において、溝深さのパターンばらつき、面内ばらつき、ウエハ間・ロット間ばらつきを低く抑え、実効比誘電率が低い多層配線が形成できる。Prior to describing embodiments of the present invention, dual damascene wiring according to the prior art will be described.
Referring to FIG. 1A, in a general dual damascene wiring structure composed of a copper / low dielectric constant film, a Cu cap film 2 formed of a material such as SiCN on a lower wiring 1 and a low thickness of SiOCH or the like. Via interlayer low dielectric constant film 3 formed of a dielectric constant film, etching stopper film 4 formed of an inorganic film such as SiO 2 , wiring interlayer low dielectric constant film 5 formed of a low dielectric constant film such as porous SiOCH, In a hard mask 6 formed of an inorganic film such as SiO 2 and an insulating film structure of a Cu camp film 7 formed of a material such as SiCN, copper 8 constituting a main wiring, Cu barrier film 9 such as Ta / TaN, etc. It is a structure in which a wiring / via formed by is embedded. This structure is formed by a dual damascene method described in Japanese Unexamined Patent Application Publication No. 2004-047873 (hereinafter referred to as Patent Document 1). However, in order to further reduce the dielectric constant between the wiring layers and via layers, it is effective to replace the Cu cap films 2 and 7 made of an inorganic film, the etching stopper film 4 and the hard mask 6 with a low dielectric constant film. It is. In particular, since the etching stopper film 4 and the hard mask 6 exist between the electrodes, the effective relative dielectric constant can be reduced by replacing with the low dielectric constant film.
Therefore, as shown in FIG. 1B, a structure in which there is no etching stopper and the hard mask is a low dielectric constant film hard mask 6 ′ has been studied.
Now, an embodiment of the present invention will be described with reference to FIGS.
The present invention relates to a carbon / silicon ratio (C) in a SiOCH film continuum in which a first SiOCH low dielectric constant film located in a lower layer and a second SiOCH low dielectric constant film located in an upper layer are directly laminated. Etching the upper SiOCH film with two types of SiOCH low dielectric constant films with different / Si ratios in a N 2 / CH x F y mixed gas system can ensure the etching selectivity of the upper and lower SiOCH films and emit light Based on the discovery that end point detection by spectroscopy is possible.
In the multilayer wiring manufacturing method of the present invention, for example, an Aurora ™ film which is a plasma CVD-SiOCH film as a via interlayer low dielectric constant film, and an MPS-SiOCH film (Molecular) which is a molecular pore film as a wiring interlayer low dielectric constant film. Pore Stack film, hereinafter simply referred to as “MPS”). Here, the carbon / silicon ratio in the MPS-SiOCH film = 2.7, which is larger than the carbon / silicon ratio in the Aurora ™ film (plasma CVD-SiOCH film) = 0.7. The film 2 is used as a hard mask.
In the method for forming a multilayer wiring of the present invention, etching is performed using a mixed gas plasma composed of a fluorocarbon composed of a single carbon atom such as CF 4 and 20 to 50% nitrogen gas.
FIG. 2 is a graph showing the dependency of SiOCH (Aurora ™ , MPS) etching rate on nitrogen addition amount evaluated with a blanket wafer. Referring to FIG. 2, using a parallel plate etching apparatus, the distance between electrodes is 35 mm, the pressure is 6.65 Pa (50 mTorr), the upper electrode power is 1000 W, the lower electrode power is 100 W, Ar / N 2 / CF 4 / O 2 = The etching rate was determined under the conditions of 300/100/25/6 sccm. In Aurora ™ , the etching rate decreases due to nitrogen content, whereas in MPS, the etching rate increases. Further, it has been confirmed that when the groove pattern is etched with the SiO 2 hard mask, an MPS / Aurora ™ etching selection ratio of 1.7 or more can be secured. By controlling the nitrogen gas flow rate in this way, MPS etching can be stopped on Aurora ™ . Thus, it is found that even a SiOCH film continuum can detect a change in the C / Si ratio, and the end point of etching can be detected. Furthermore, when a single carbon atom (C x F y : x = 1) such as CF 4 is used as the fluorocarbon gas, the emission spectrum of SiF or the like becomes clear, and the end point detection by the emission spectrum becomes easy.
3A and 3B are diagrams showing emission spectra of 440 nm when the MPS substrate and the silicon substrate are etched by adding C 4 F 8 gas or CF 4 gas. Referring to FIGS. 3A and 3B, in C 4 F 8 , the molecular emission spectrum from the polymer fluorocarbon exists over a wide band, so that the emission at 440 nm is likely to be buried, but when CF 4 is used, You can see clearly.
Figure 4 performs a groove exposed on the structure of SiO 2 / MPS / Aurora TM, and resist ashing after etching the SiO2 hard mask, observing the time variation of the 440nm emission spectrum in the case of MPS etched in SiO 2 hard mask FIG. Referring to FIG. 4, etching is performed using a parallel plate etching apparatus with a distance between electrodes of 35 mm, a pressure of 6.65 Pa (50 mTorr), an upper electrode power of 1000 W, a lower electrode power of 100 W, Ar / N 2 / CF 4 / The measurement was performed under the condition of O 2 = 300/100/25/6 sccm. When the MPS etching is completed, the emission spectrum of 440 nm indicating SiF increases. This is because Aurora ™ has a smaller C / Si ratio than MPS. A value obtained by differentiating the emission spectrum of 440 nm is also shown, but it is greatly changed. By adjusting the etching time using this emission spectrum or its differential value, variation in etching depth between wafers and lot variation can be suppressed.
5A is a structure of SiO 2 / MPs / SiOCH, and the C / Si ratio of SiOCH is C / Si = 2.22, 1.53, 1.41,1. Each of the samples changed to .20 was exposed to a groove, etched the SiO 2 hard mask, resist ashed, and MPS etched with the SiO 2 hard mask. Show. The C / Si ratio of MPS is 27. The lower the lower SiOCH C / Si ratio, the greater the time variation of the 440 nm spectrum. When the C / Si ratio is 1.4 or less, the time change is particularly large.
From this result, it can be seen that the C / Si ratio of the upper SiOCH (here, MPS) in the SiOCH film continuum is preferably about twice that of the lower layer.
From these facts, when etching MPS with a gas such as Ar / N 2 / CF 4 , a selection ratio with the lower layer Aurora TM film can be secured, and by luminescence spectroscopy, it is a SiOCH film continuum. Since the end point of the etching of the two types of SiOCH low dielectric constant films made of can be detected, there is little in-plane variation and pattern variation, and groove processing with little variation between wafers and lots is possible.
Further, as shown in FIG. 6, Ar / N 2 / CF 4 is superior to Ar / N 2 / C 4 F 8 also from the viewpoint of F occlusion. This is because C 4 FR easily exhibits a dissociation reaction (binding energy is weak) as compared with CF 4 , so that a large amount of CF 2 , CF, and F radicals are generated from C 4 F 8 . When fluorine is taken into the SiOCH film, adhesion is deteriorated or HF is formed by moisture absorption to form voids in the film, so that it is understood that addition of CF 4 is preferable. Furthermore, in the etching efficiency of the film, CF 3 ions are known to be higher than CF 2 and CF ion, CF 4 is added to generate a CF 3 ions.
By the way, in a carbon-rich SiOCH film having a C / Si ratio> 1, when plasma etching is performed with a C x H y / N 2 -based gas, a carbonitride film is formed on the sidewall.
FIG. 7 shows the N1s spectrum observed on the surface after irradiation with etching plasma using XPS. In the MPS film (ie in the case of a SiOCH film with a C / Si ratio> 1) the N1s spectrum is observed after irradiation. This carbonitride film is completely removed in the oxygen ashing process subsequent to the etching process, but has an effect of suppressing carbon extraction from the side wall of the SiOCH film. That is, the amount of oxidation on the side wall after oxygen ashing is suppressed. This effect becomes more prominent as the amount of carbon in the SiOCH film is larger, and it is more remarkable that the film contains unsaturated hydrocarbons. This is presumably because unsaturated hydrocarbons in the film are likely to react with N radicals in the etching plasma, and a carbonitride film is likely to be formed. Further, although the detailed cause is not clear, when the silica skeleton of the SiOCH film having a carbon-rich C / Si ratio> 1 is a ring, and further a six-membered ring (Si 3 O 3 ), oxidation of the side wall after oxygen ashing is performed. There was also a tendency for the amount to be suppressed.
Now, with respect to a structure in which a wiring interlayer low dielectric constant film that is a carbon-rich SiOCH film and a via interlayer low dielectric constant film that is a silicon-rich (C / Si <1) layer are directly laminated. Thus, an opening made of a wiring groove and a via is formed. In the wiring interlayer low dielectric constant film, which is a carbon-rich SiOCH film, the amount of oxidation on the side walls is suppressed and becomes thinner than the amount of oxidation on the via side walls.
8A and 8B are diagrams showing the results of analyzing the composition of the MPS film and the Aurora TM film by TEM-EELS mapping after forming Cu wiring on the pattern exposed to ashing plasma after etching, respectively. It is sectional drawing of the sample for TEM-EELS mapping.
FIG. 9 is an electron micrograph in which Cu wiring is formed on a pattern exposed to ashing plasma after etching, and the oxide layer on the side wall of MPS, Aurora ™ after wiring processing is investigated by hydrofluoric acid dip.
In MPS, the change of C and O is reduced to about 10 nm from the side wall, whereas when Aurora TM is used, C and ○ are changed deeply to about 30 nm, and the thickness of the oxidation-modified layer is large. I understand that. Such a difference in the amount of oxidation can be easily confirmed by dipping the device cross-section into a dilute hydrofluoric acid aqueous solution. The characteristic carbon-rich SiOCH / silicon-rich SiOCH layered structure in this structure is filled with a resist after dual damascene processing, and the result of dipping for 5 seconds in an aqueous solution containing 6% HF and 30% NH 4 F after forming the cross section of the wiring Show. An oxide layer can be confirmed on the Aurora ™ side wall and the bottom of the trench. In MPS, almost no modified layer is confirmed. Since the wiring layer low dielectric constant film can be formed with a small amount of oxidation, it is possible to form a Cu / low-k wiring while suppressing an increase in effective relative dielectric constant.
According to the present invention, in multilayer wiring using a low dielectric constant film as a wiring layer opening film, it is possible to suppress groove depth pattern variation, in-plane variation, wafer-to-lot / lot-to-lot variation, and low effective relative dielectric constant. Wiring can be formed.
以下、本発明の実施例について図面を参照しながら詳細に説明する。
（第１の実施例）
第１の実施例では、ＳｉＯ２ハードマスクについて説明する。
第１０Ａ図から第１０Ｈ図は本発明の第１の実施例にかかわる多層配線構造の製造プロセスを複式的に示す断面図である。第１の実施例は、シリコン酸化膜／ＭＰＳ膜／ＡｕｒｏｒａＴＭ／ＳｉＣＮの絶縁膜構造にビアと配線溝が形成されている、いわゆるデュアルダマシンＣｕ配線の形成にあたり、ビア加工をした後、配線溝用レジストパターン形成し、Ａｒ／Ｎ２／ＣＦ４プラズマにより発光による終点検出を用いながらＭＰＳ膜をエッチングすることにより、面内均―性やパターン依存性、ウエハ間・ロット間ばらつきが少ない溝加工を行うことができるものである。
まず、第１０Ａ図に示すように、下層配線２０１上に銅キャップ膜となるシリコン炭窒化膜２０２、ビア層間低誘電率膜となるＡｕｒｏｒａＴＭ膜２０３、配線層間低誘電率膜となるＭＰＳ膜２０４、ハードマスクであるシリコン酸化膜２０５をこの順に例えばプラズマＣＶＤ法により成膜し、その上に反射防止膜２０６、ビア用レジスト２０７をこの順に塗布し、ビアレジストパターン２０７ａ、２０７ｂを形成する。
次に、第１０Ｂ図に示すように、ビアレジストパターン２０７ａ、２０７ｂをマスクとして、反射防止膜２０６、シリコン酸化膜２０５、ＭＰＳ膜２０４、ＡｕｒｏｒａＴＭ膜２０３をこの順でエッチングする。
その後、第１０Ｃ図に示すように、例えば、酸素プラズマなどでアッシングを行うと、ビア孔パターン２０３ａ、２０３ｂが形成される。
その後、第１０Ｄ図に示すように、シリコン酸化膜２０５の上に有機膜２０８を塗布し、シリコン酸化膜２０９を例えばＣＶＤ法によって成膜する。シリコン酸化膜２０９の上に反射防止膜２１０、配線溝用レジスト２１１をこの順に塗布し、配線溝用レジストパターン２１１ａ、２１１ｂを形成する。
第１０Ｅ図に示すように、配線溝用レジストパターン２１１ａ、２１１ｂをマスクとして、反射防止膜２１０、シリコン酸化膜２０９、有機膜２０８、シリコン酸化膜２０５をエッチングする。有機膜２０８のエッチングの際に配線溝用レジスト２１１と反射防止膜２１０が消失し、シリコン酸化膜２０５のエッチングの際にシリコン酸化膜２０９が消失するため、第１０Ｅ図に示したエッチング加工後は有機膜２０８が最上層になる形となる。
その後、第１０Ｆ図に示すように、有機膜２０８を例えば酸素プラズマによりアクシングすると、配線溝用パターンが転写された配線溝用ハードマスクパターン２０５ａ、２０５ｂが形成できる。
さらに、第１０Ｇ図に示すように、配線溝用ハードマスクパクーン２０５ａ、２０５ｂをマスクとして、ＭＰＳ膜２０４をＡｒ／Ｎ２／ＣＦ４プラズマを用いてエッチングする。このときの条件としては、平行平板電極のプラズマ源で、電極間距離３５ｍｍ、圧力１０．６Ｐａ（８０ｍＴｏｒｒ）、上部電極パワー１０００Ｗ、バイアスパワー１００Ｗ、Ａｒ／Ｎ２／ＣＦ４／Ｏ２＝３００／１００／２５／６ｓｃｃｍの条件などが挙げられる。ここで重要なのは、単炭素原子フルオロカーボンを用いることと、２０％以上５０％未満の窒素を用いることである。単炭素原子フルオロカーボンを用いることで発光分光による終点検出をしやすくし、窒素を含有させることで下層ＡｕｒｏｒａＴＭ膜との選択比を確保することができるためである。これらの条件を用いると、ＳｉＦ＝４４０ｎｍなどの発光変化を容易に観測可能になるため、終点検出ができ、面内ばらつきやパターンばらつき、ウエハ間、ロット間ばらつきの少ない加工が可能になる。また、このエッチング中にＣｕキャップ膜２０２は消失する。
その後、第１０Ｈ図に示すように、デポジション物を除去するため、Ｏ２を含むクリーニングプラズマを若干照射する。このとき、Ｃ／Ｓｉ＝０．７とシリコンリッチのＡｕｒｏｒａＴＭ側壁２０３’に比べて、Ｃ／Ｓｉ＝２．７とカーボンリッチなＭＰＳ側壁２０４′には、薄い酸化層が形成される。配線層間低誘電率膜での酸化改質層が薄いので、比誘電率が低く抑制できる。このような配線部とビア部での酸化量の違いはデバイスの破断面に対して希フッ酸水溶液にディッピングすることで容易に確認できる。例えば、６％ＨＦ、３０％ＮＨ４Ｆを含む水溶液に３から５秒ディッピングすることで確認できる。逆に、このような配線側壁とビア側壁との酸化厚の違いを有することは、本願発明による製造プロセスおよび化学組成の異なるＳｉＯＣＨ膜を直接積層した層間絶縁膜構造を用いた証となる。
この後、第１０Ｉ図に示すように、バリア・Ｃｕシードスパッタ、Ｃｕめっきを行い、ＣＭＰによりＣｕ配線２１２が形成される。さらにＣｕキャップ膜としてシリコン炭窒化膜を例えばＣＶＤ法により成膜する。これを繰り返すことにより、多層配線が形成できる。
本実施例の配線層間低誘電率膜としては、ＭＰＳ膜を示したが、ビア層間低誘電率膜とのカーボン／シリコン比の差が十分確保できるＳｉＯＣＨ膜であれば、特に限定されず、上記と同じ材料が適用できる。望ましくは、ビア層間低誘電率膜のカーボン／シリコン比に対して、配線層間低誘電率膜のカーボン／シリコン比が２倍以上のあることが望ましい。
また、本プラズマ発光をモニタする終点検出方法を適用したデュアルダマシン開口パターン形成の場合、酸素アッシング工程による配線溝側壁の酸化を抑制するため、ＳｉＯＣＨ膜中のＣ／Ｓｉ比が１．５以上であることが望ましい。
一方、本実施例のビア層間低誘電率膜としてＡｕｒｏｒａＴＭ膜を示したが、配線層間低誘電率膜のカーボン／シリコン比に対するビア層間低誘電率膜のカーボン／シリコン比、すなわち｛（Ｃ／Ｓｉ）ビアノ（Ｃ／Ｓｉ）配線｝比が０．５倍以下であることが望ましい。ビア層間低誘電率膜中のＣ／Ｓｉ比が１以下である日本ＡＳＭ社のＡｕｒｏｒａシリーズ、Ｔｒｉｃｏｎ社のＯｒｉｏｎ、Ａｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ社のＢＤ／ＢＤＩＩ、ノベラス社のＣｏｒａｌなどのＣＶＤ−ＳｉＯＣＨ膜、Ｄｏｗ−Ｃｈｅｍｉｃａｌ社のポーラスＳｉＬＫ、触媒化成社のＮＣＳなどの塗布成膜するＳｉＯＣＨ膜などでも構わない。さらには、特許文献１で示されているようなプラズマ重合で形成されるＳｉＯＣＨ膜でもよい。実装耐性を考えると、ビア層間低誘電率膜の方が配線層間低誘電率膜よりも高い密度を持つ材料を選択するのが好ましい。
本実施例では、Ｃｕキャップ膜としてシリコン炭窒化膜を用いた例を示したが、低誘電率膜とのエッチング選択比が確保てき、Ｃｕバリア性のある材料であれば、特に制限はなく、どのような材料も使用することができる。例えば、シリコン炭化膜、シリコン窒化膜などが挙けられるが、プラズマ重合法で形成された有機膜やジビニルシロキサン・ベンゾクロブテン（ＤＶＳ−ＢＣＢ）のようなシロキサン含有有機膜であってもよい。さらには本実施例では、ＭＰＳ膜をハードマスクをマスクとして加工する例について示したが、ＭＰＳのエッチングをレジスト剥離前に行っても良い。
（第２の実施例）
本発明の第２の実施例では、ｌｏｗ−ｋハードマスクについて説明する。
第１１Ａ図乃至第１１Ｈ図は本発明の第２の実施例にかかわる多層配線構造の製造プロセスを複式的に示す断面図である。第２の実施例は、シリコン酸化膜／Ｂｌａｃｋ ＤｉａｍｏｎｄＴＭ／ＭＰＳ膜／ＡｕｒｏｒａＴＭ／ＳｉＣＮの絶縁膜構造にビアと配線溝が形成されている、いわゆるデュアルダマシンＣｕ配線の形成にあたり、ビア加工をした後、配線溝用レジストパターン形成し、Ａｒ／Ｎ２／ＣＦ４プラズマにより発光による終点検出を用いながらＭＰＳ膜をエッチングすることにより、面内均一性やパターン依存性が少ない溝加工を行うとともに、ハードマスクを低誘電率化することにより、さらなる実効誘電率の低下を鑑みたものである。
まず、第１１Ａ図に示すように、第１の実施例と同様に下層配線２０１上に銅キャップ膜となるシリコン炭窒化膜２０２、ビア層間低誘電率膜となるＡｕｒｏｒａＴＭ膜２０３、配線層間低誘電率膜となるＭＰＳ膜２０４をこの順にプラズマＣＶＤなどにより成膜する。さらに、第一のハードマスクであるＢｌａｃｋ ＤｉａｍｏｎｄＴＭ膜３０５、第二のハードマスクであるシリコン酸化膜３０６をこの順に例えばプラズマＣＶＤ法により成膜し、その上に反射防止膜３０７、ビア用レジスト３０８をこの順に塗布し、ビアレジストパターン３０８ａ、３０８ｂを形成する。
次に、第１１Ｂ図に示すように、ビアレジストパターン３０８ａ、３０８ｂをマスクとして、反射防止膜３０７、シリコン酸化膜３０６、Ｂｌａｃｋ ＤｉａｍｏｎｄＴＭ膜３０５、ＭＰＳ膜２０４、ＡｕｒｏｒａＴＭ膜２０３をこの順でエッチングする。
その後、第１１Ｃ図に示すように、例えば、酸素プラズマなどでアッシングを行うと、ビア孔パターン２０３ａ、２０３ｂが形成される。
その後、第１１Ｄ図に示すように、シリコン酸化膜３０６の上に有機膜３０９を塗布し、シリコン酸化膜３１０を、例えばＣＶＤ法によって成膜する。シリコン酸化膜３１０の上に反射防止膜３１１、配線溝用レジスト３１２をこの順に塗布し、配線溝用レジストパターン３１２ａ、３１２ｂを形成する。
第１１Ｅ図に示すように、配線溝用レジストパターン３１２ａ、３１２ｂをマスクとして、反射防止膜３１１、シリコン酸化膜３１０、有機膜３０９、シリコン酸化膜３０６、Ｂｌａｃｋ ＤｌａｍｏｎｄＴＭ膜３０５をエッチングする。有機膜３０９のエッチングの際に配線溝用レジスト３１２と反射防止膜３１１が消失し、シリコン酸化膜３０６のエッチングの際にシリコン酸化膜３１０が消失するため、第１１Ｅ図に示したエッチング加工後は有機膜３０９が最上層になる形となる。
その後、第１１Ｆ図に示すように、有機膜３０９を例えば酸素プラズマによりアッシングすると、配線溝用パターンが転写された配線溝用ハードマスクパターン３０５ａ、３０５ｂが形成できる。
さらに、第１１Ｇ図に示すように、配線溝用ハードマスクパクーン３０５ａ、３０５ｂをマスクとして、ＭＰＳ膜２０４をＡｒ／Ｎ２／ＣＦ４プラズマを用いてエッチングする。このときの条件としては、平行平板電極のプラズマ源で、電極間距離３５ｍｍ、圧力１０．６Ｐａ（８０ｍＴｏｒｒ）、上部電極パワー１０００Ｗ、バイアスパワー１００Ｗ、Ａｒ／Ｎ２／ＣＦ４／Ｏ２＝３００／１００／２５／６ｓｃｃｍの条件などが挙げられる。ここで重要なのは、単炭素原子フルオロカーボンを用いることと、２０％以上５０％未満の窒素を用いることである。単炭素原子フルオロカーボンを用いることで発光分光による終点検出をしやすくし、窒素を含有させることで下層ＡｕｒｏｒａＴＭ膜との選択比を確保することができるためである。これらの条件を用いると、ＳｉＦ＝４４０ｎｍなどの発光変化を容易に観測可能になるため、終点検出ができ、面内ばらつきやパターンばらつき、ウエハ間、ロット間ばらつきの少ない加工が可能になる。
また、第１１Ｈ図に示すように、このエッチング中にＣｕキャップ膜２０２は消失する。その後、デポジション物を除去するため、Ｏ２を含むクリーニングプラズマを若干照射する。このとき、Ｃ／Ｓｉ＝０．７とシリコンリッチのＡｕｒｏｒａＴＭの側壁２０３’に比べて、Ｃ／Ｓｉ＝２．７とカーボンリッチのＭＰＳ側壁２０４’には薄い酸化層が形成される。配線層間低誘電率膜での酸化改質層が薄いので、実効比誘電率の上昇を抑制できる。このような配線部とビア部での酸化量の違いはデバイスの破断面に対して希フッ酸水溶液にディッピングすることで容易に確認できる。例えば、６％ＨＦ，３０％ＮＨ４Ｆを含む水溶液に３から５秒ディッピングすることで確認できる。逆に、このような配線側壁とビア側壁との酸化厚の違いを有することは、本願発明による製造プロセスおよび化学組成の異なるＳｉＯＣＨ膜を直接積層した層間絶縁膜構造を用いた証となる。
この後、第１１Ｉ図に示すように、バリア・Ｃｕシードスパック、Ｃｕめっきを行い、ＣＭＰによりＣｕ配線３１３が形成される。このとき、シリコン酸化膜を削り取ってしまうことにより、実効誘電率の低下が見込める。さらにＣｕキャップ膜としてシリコン炭窒化膜を例えばＣＶＤ法より成膜する。これを繰り返すことにより、多層配線が形成できる。
本実施例の配線層間低誘電率膜としては、ＭＰＳ膜を示したが、ビア層間低誘電率膜とのカーボン／シリコン比の差が十分確保できるＳｉＯＣＨ膜であれば、特に限定されず、上記と同じ材料が適用できる。望ましくは、ビア層間低誘電率膜のカーボン／シリコン比に対して、配線層間低誘電率膜のカーボン／シリコン比が２倍以上のあることが望ましい。また、本プラズマ発光をモニタする終点検出方法を適用したデュアルダマシン開口パターン形成の場合、酸素アッシング工程による配線溝側壁の酸化を抑制するため、ＳｉＯＣＨ膜中のＣ／Ｓｉ比が１．５以上であることが望ましい。
実施例のビア層間低誘電率膜としてＡｕｒｏｒａＴＭ膜を示したが、例えば、配線層間低誘電率膜のカーボン／シリコン比に対するビア層間低誘電率膜のカーボン／シリコン比、すなわち｛（Ｃ／Ｓｉ）ビア／（Ｃ／Ｓｉ）配線｝比が０．５倍以下であることが望ましく、ビア層間低誘電率膜中のＣ／Ｓｉ比が１以下である日本ＡＳＭ社のＡｕｒｏｒａシリーズ、Ｔｒｉｃｏｎ社のＯｒｉｏｎ、Ａｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ社のＢＤ／ＢＤＩＩ、ノベラズ社のＣｏｒａｌなどのＣＶＤ−ＳｉＯＣＨ膜、Ｄｏｗ−Ｃｈｅｍｉｃａｌ社のポーラスＳｉＬＫ、触媒化成社のＮＣＳなどの塗布成膜するＳｉＯＣＨ膜などでも構わない。さらには、特許文献１に示されているようなプラズマ重合で形成されるＳｉＯＣＨ膜でもよい。実装耐性を考えると、ビア層間低誘電率膜の方が配線層間低誘電率膜よりも高い密度を持つ材料を選択するのが好ましい。低誘電率ハードマスクとしても上記の材料のいずれもが使用可能である。ＣＭＰ耐性のある膜であれば、種類を問わない。
本実施例では、Ｃｕキャップ膜としてシリコン炭窯化膜を用いた例を示したが、低誘電率膜とのエッチング選択比が確保でき、Ｃｕバリア性のある材料であれば、特に制限はなく、どのような材料も使用することができる。例えば、シリコン炭化膜、シリコン窒化膜などが挙けられるが、プラズマ重合法で形成された有機膜やジビニルシロキサン・ベンゾクロブテン（ＤＶＳ−ＢＣＢ）のようなシロキサンン含有有機膜であってもよい。
さらには本実施例では、ＭＰＳ膜をハードマスクをマスクとして加工する例について示したが、ＭＰＳのエッチングをレジスト剥離前に行っても良い。
（第３の実施例）
第３の実施例では、多層構造について説明する。
第１２図はシリコン基板４０１に素子分離酸化膜４０２で分離されたＭＯＳＦＥＴ４０３上に炭素含有の低誘電率絶縁膜に銅多層配線を形成した実施例を示す図である。以下に、その構造的特徴を示す。本実施例においても、ＭＰＳのエッチングにはＡｒ／Ｎ２／ＣＦ４の混合ガスプラズマを用いることにより、面内ばらつき、パターン依存性、ウエハ間・ロット間ばらつきの少ない溝加工が可能である。ここては、ビア層間低誘電率膜としてＡｕｒｏｒａＴＭ膜、配線溝用層間膜としてＭＰＳ膜、Ｌｏｗ−ｋハードマスクとしてＢＤＴＭ膜を用いた場合を示したが、日本ＡＳＭ社のＡｕｒｏｒａシリーズ、Ｔｒｉｃｏｎ社のＯｒｉｏｎ、Ａｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ社のＢＤ／ＢＤＩＩ、ノベラズ社のＣｏｒａｌなどのＣＶＤ−ＳｉＯＣＨ膜、Ｄｏｗ−Ｃｈｅｍｉｃａｌ社のポーラスＳｉＬＫ、触媒化成社のＮＣＳなどの塗布成膜するＳｉＯＣＨ膜などでも構わない。さらには、特許文献１で示されているようなプラズマ重合で形成されるＳｉＯＣＨ膜でもよい。ＭＯＳＦＥＴ４０３上には、Ｗコンククトプラグ４０４を持つシリコン酸化膜４０５が形成されており、前記シリコン酸化膜４０５上に第１層目銅配線４０６に対応する配線溝のエッチストップ膜として３０ｎｍ厚のシリコン炭窒素化膜４１３が形成されている。このシリコン炭窒化膜上には１１０ｎｍ厚のＭＰＳ膜４１４とそのハードマスクとして３０ｎｍ厚のＢＤ膜４１５が形成されている。第１層目の銀配線は、かかるＢＤ膜４１５／ＭＰＳ膜４１４／シリコン炭窒化膜４１３からなる積層絶縁膜を貫く配線溝にＴａ（１０ｎｍ）／ＴａＮ（５ｎｍ）のバリア膜４２０で覆われたＣｕ膜４２１が埋め込まれた構造となっている。この第１層目のＣｕ配線４０６は、Ｗコンククトプラグ４０４に接続されている。第１層目のＣｕ配線４０６上には、ビアエッチングストップ層として３０ｎｍ厚のシリコン炭窒化膜４１６が形成されている。さらに、１５０ｎｍ厚のＡｕｒｏｒａＴＭ膜４１７とが形成されている。ＡｕｒｏｒａＴＭ膜４１７はＣＭＰ等によって平坦化されていても良い。さらに、このＡｕｒｏｒａＴＭ膜４１７上には１３０ｎｍ厚のＭＰＳ膜４１８とそのハードマスクとして３０ｎｍ厚のＢＤ膜４１９が形成されている。この積層構造絶縁膜に対して、ＢＤ膜４１９／ＭＰＳ膜４１８を貫く配線溝にＣｕ膜の埋め込まれた第２のＣｕ配線４０８が形成されている。この第２の銅配線４０８の底部より、ＡｕｒｏｒａＴＭ膜４１７とシリコン炭窒化膜４１６を貫く第１のＣｕビアプラグ４０７が形成されており、第１層目のＣｕ配線４０６に接続されている。
酸素プラズマクリーニング工程によりＡｕｒｏｒａＴＭ膜４１７側壁には酸化改質層４２２が存在し、ＭＰＳ膜４１８側壁には、４２２より薄い酸化改質層４２３が存在する。このような配線部とビア部での酸化量の違いはデバイスの破断面に対して希フッ酸水溶液にディッピングすることで容易に確認できる。例えば、６％ＨＦ，３０％ＮＨ４Ｆを含む水溶液に３から５秒ディッピングすることで確認できる。逆に、このような配線側壁とビア側壁との酸化厚の違いを有することは、本願発明による製造プロセスおよび化学組成の異なるＳｉＯＣＨ膜を直接積層した層間絶縁膜構造を用いた証となる。第３層のＣｕ配線層４１０、第３層と第２層を繋ぐＣｕビアプラグ４０９に対しても、第二配線層４０８、ビアプラグ４０７と同じ構造を形成することが可能であり、この構造を重ねることによって多層配線を形成することが可能である。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
In the first embodiment, an SiO 2 hard mask will be described.
FIGS. 10A to 10H are cross-sectional views illustrating a manufacturing process of a multilayer wiring structure according to the first embodiment of the present invention. In the first embodiment, in forming a so-called dual damascene Cu wiring in which a via and a wiring groove are formed in an insulating film structure of silicon oxide film / MPS film / Aurora ™ / SiCN, a wiring groove is formed after via processing. Groove processing with less in-plane uniformity, pattern dependency, and wafer-to-lot / lot-to-lot variations by forming a resist pattern for etching and etching the MPS film using Ar / N 2 / CF 4 plasma to detect the end point by light emission Is something that can be done.
First, as shown in FIG. 10A, a silicon carbonitride film 202 serving as a copper cap film on the lower wiring 201, an Aurora TM film 203 serving as a via interlayer low dielectric constant film, and an MPS film 204 serving as a wiring interlayer low dielectric constant film. Then, a silicon oxide film 205 as a hard mask is formed in this order by, for example, a plasma CVD method, and an antireflection film 206 and a via resist 207 are applied thereon in this order to form via resist patterns 207a and 207b.
Next, as shown in FIG. 10B, the antireflection film 206, the silicon oxide film 205, the MPS film 204, and the Aurora ™ film 203 are etched in this order using the via resist patterns 207a and 207b as masks.
Thereafter, as shown in FIG. 10C, ashing is performed using, for example, oxygen plasma to form via hole patterns 203a and 203b.
Thereafter, as shown in FIG. 10D, an organic film 208 is applied on the silicon oxide film 205, and a silicon oxide film 209 is formed by, for example, a CVD method. On the silicon oxide film 209, an antireflection film 210 and a wiring groove resist 211 are applied in this order to form wiring groove resist patterns 211a and 211b.
As shown in FIG. 10E, the antireflection film 210, the silicon oxide film 209, the organic film 208, and the silicon oxide film 205 are etched using the wiring groove resist patterns 211a and 211b as a mask. Since the wiring groove resist 211 and the antireflection film 210 disappear when the organic film 208 is etched, and the silicon oxide film 209 disappears when the silicon oxide film 205 is etched, after the etching process shown in FIG. 10E, The organic film 208 is the uppermost layer.
Thereafter, as shown in FIG. 10F, when the organic film 208 is axed by, for example, oxygen plasma, wiring groove hard mask patterns 205a and 205b to which the wiring groove pattern is transferred can be formed.
Further, as shown in FIG. 10G, the MPS film 204 is etched using Ar / N 2 / CF 4 plasma using the wiring groove hard mask pacoons 205a and 205b as masks. The conditions at this time were a plasma source of parallel plate electrodes, a distance between electrodes of 35 mm, a pressure of 10.6 Pa (80 mTorr), an upper electrode power of 1000 W, a bias power of 100 W, Ar / N 2 / CF 4 / O 2 = 300 / The condition of 100/25/6 sccm is mentioned. What is important here is to use a single carbon atom fluorocarbon and to use 20% or more and less than 50% nitrogen. This is because the use of a single carbon atom fluorocarbon facilitates end point detection by emission spectroscopy, and the inclusion of nitrogen can ensure the selectivity with the lower Aurora ™ film. When these conditions are used, it is possible to easily observe a change in light emission such as SiF = 440 nm, so that the end point can be detected, and processing with less in-plane variation, pattern variation, wafer-to-lot, and lot-to-lot variation is possible. Further, the Cu cap film 202 disappears during the etching.
Thereafter, as shown in FIG. 10H, a cleaning plasma containing O 2 is slightly irradiated to remove the deposits. At this time, a thinner oxide layer is formed on the C / Si = 2.7 and carbon-rich MPS side wall 204 ′ than on the silicon-rich Aurora ™ side wall 203 ′ with C / Si = 0.7. Since the oxidized modified layer in the wiring interlayer low dielectric constant film is thin, the relative dielectric constant can be suppressed low. Such a difference in the amount of oxidation between the wiring portion and the via portion can be easily confirmed by dipping the fracture surface of the device in a dilute hydrofluoric acid aqueous solution. For example, it can be confirmed by dipping for 3 to 5 seconds in an aqueous solution containing 6% HF and 30% NH 4 F. On the other hand, the difference in oxide thickness between the wiring sidewall and the via sidewall is evidence that the manufacturing process according to the present invention and the interlayer insulating film structure in which SiOCH films having different chemical compositions are directly laminated are used.
Thereafter, as shown in FIG. 10I, barrier / Cu seed sputtering and Cu plating are performed, and a Cu wiring 212 is formed by CMP. Further, a silicon carbonitride film is formed as a Cu cap film by, for example, a CVD method. By repeating this, a multilayer wiring can be formed.
Although the MPS film is shown as the wiring interlayer low dielectric constant film of this embodiment, it is not particularly limited as long as it is a SiOCH film that can sufficiently ensure the difference in carbon / silicon ratio from the via interlayer low dielectric constant film. The same materials can be applied. Desirably, the carbon / silicon ratio of the wiring interlayer low dielectric constant film is preferably twice or more the carbon / silicon ratio of the via interlayer low dielectric constant film.
In addition, in the case of forming a dual damascene opening pattern using the end point detection method for monitoring the plasma emission, the C / Si ratio in the SiOCH film is 1.5 or more in order to suppress the oxidation of the wiring trench side wall by the oxygen ashing process. It is desirable to be.
On the other hand, although the Aurora ™ film is shown as the low dielectric constant film between the via layers of this example, the carbon / silicon ratio of the low dielectric constant film between the via layers with respect to the carbon / silicon ratio of the low dielectric constant film between the wiring layers, that is, {(C / The Si) Viano (C / Si) wiring ratio is preferably 0.5 times or less. CVD-SiOCH film such as Aurora series by ASM Japan, Orion from Tricon, BD / BDII from Applied Materials, Coral from Novellus, etc., C / Si ratio in via interlayer low dielectric constant film is 1 or less A SiOCH film to be formed by coating such as Porous SiLK of Chemical Company or NCS of Catalytic Chemical Company may be used. Furthermore, a SiOCH film formed by plasma polymerization as shown in Patent Document 1 may be used. In view of mounting tolerance, it is preferable to select a material having a higher density in the via interlayer low dielectric constant film than in the wiring interlayer low dielectric constant film.
In this example, an example using a silicon carbonitride film as the Cu cap film was shown, but the etching selectivity with the low dielectric constant film has been secured, and there is no particular limitation as long as the material has a Cu barrier property. Any material can be used. For example, a silicon carbide film, a silicon nitride film, and the like are listed, but an organic film formed by a plasma polymerization method or a siloxane-containing organic film such as divinylsiloxane / benzoclobutene (DVS-BCB) may be used. Furthermore, in the present embodiment, an example in which the MPS film is processed using a hard mask as a mask is shown, but MPS etching may be performed before resist stripping.
(Second embodiment)
In the second embodiment of the present invention, a low-k hard mask will be described.
FIGS. 11A to 11H are cross-sectional views illustrating a manufacturing process of a multilayer wiring structure according to the second embodiment of the present invention. In the second embodiment, after forming a so-called dual damascene Cu wiring in which a via and a wiring groove are formed in an insulating film structure of silicon oxide film / Black Diamond ™ / MPS film / Aurora ™ / SiCN, By forming the resist pattern for the wiring groove and etching the MPS film while using the Ar / N 2 / CF 4 plasma to detect the end point by light emission, the groove processing with less in-plane uniformity and pattern dependency is achieved. This is in view of further reduction in effective dielectric constant by reducing the dielectric constant of the mask.
First, as shown in FIG. 11A, a silicon carbonitride film 202 serving as a copper cap film, an Aurora TM film 203 serving as a via interlayer low dielectric constant film, and a wiring interlayer low layer are formed on the lower layer wiring 201 as in the first embodiment. An MPS film 204 serving as a dielectric constant film is formed in this order by plasma CVD or the like. Further, a black diamond TM film 305 as a first hard mask and a silicon oxide film 306 as a second hard mask are formed in this order by, for example, a plasma CVD method, and an antireflection film 307 and a via resist 308 are formed thereon. Are applied in this order to form via resist patterns 308a and 308b.
Next, as shown in FIG. 11B, using the via resist patterns 308a and 308b as a mask, the antireflection film 307, the silicon oxide film 306, the Black Diamond TM film 305, the MPS film 204, and the Aurora TM film 203 are etched in this order. To do.
Thereafter, as shown in FIG. 11C, for example, when ashing is performed with oxygen plasma, via hole patterns 203a and 203b are formed.
Thereafter, as shown in FIG. 11D, an organic film 309 is applied on the silicon oxide film 306, and a silicon oxide film 310 is formed by, for example, a CVD method. An antireflection film 311 and a wiring groove resist 312 are applied in this order on the silicon oxide film 310 to form wiring groove resist patterns 312a and 312b.
As shown in FIG. 11E, the antireflection film 311, the silicon oxide film 310, the organic film 309, the silicon oxide film 306, and the Black Diamond ™ film 305 are etched using the wiring groove resist patterns 312a and 312b as masks. Since the wiring groove resist 312 and the antireflection film 311 disappear when the organic film 309 is etched, and the silicon oxide film 310 disappears when the silicon oxide film 306 is etched, after the etching process shown in FIG. The organic film 309 is the uppermost layer.
Thereafter, as shown in FIG. 11F, when the organic film 309 is ashed by, for example, oxygen plasma, wiring groove hard mask patterns 305a and 305b to which the wiring groove pattern is transferred can be formed.
Further, as shown in FIG. 11G, the MPS film 204 is etched using Ar / N 2 / CF 4 plasma using the wiring groove hard mask pacoons 305a and 305b as masks. The conditions at this time were a plasma source of parallel plate electrodes, a distance between electrodes of 35 mm, a pressure of 10.6 Pa (80 mTorr), an upper electrode power of 1000 W, a bias power of 100 W, Ar / N 2 / CF 4 / O 2 = 300 / The condition of 100/25/6 sccm is mentioned. What is important here is to use a single carbon atom fluorocarbon and to use 20% or more and less than 50% nitrogen. This is because the use of a single carbon atom fluorocarbon facilitates end point detection by emission spectroscopy, and the inclusion of nitrogen can ensure the selectivity with the lower Aurora ™ film. When these conditions are used, it is possible to easily observe a change in light emission such as SiF = 440 nm, so that the end point can be detected, and processing with less in-plane variation, pattern variation, wafer-to-lot, and lot-to-lot variation is possible.
Further, as shown in FIG. 11H, the Cu cap film 202 disappears during this etching. Thereafter, in order to remove the deposit, a cleaning plasma containing O 2 is slightly irradiated. At this time, a thinner oxide layer is formed on the C / Si = 2.7 and carbon-rich MPS side wall 204 'than on the silicon-rich Aurora ™ side wall 203'. Since the oxidized modified layer in the wiring interlayer low dielectric constant film is thin, an increase in the effective relative dielectric constant can be suppressed. Such a difference in the amount of oxidation between the wiring portion and the via portion can be easily confirmed by dipping in a dilute hydrofluoric acid solution with respect to the fracture surface of the device. For example, it can be confirmed by dipping for 3 to 5 seconds in an aqueous solution containing 6% HF and 30% NH 4 F. On the other hand, the difference in oxide thickness between the wiring sidewall and the via sidewall is evidence that the manufacturing process according to the present invention and the interlayer insulating film structure in which SiOCH films having different chemical compositions are directly laminated are used.
Thereafter, as shown in FIG. 11I, barrier / Cu seed spuck and Cu plating are performed, and a Cu wiring 313 is formed by CMP. At this time, the effective dielectric constant can be reduced by scraping the silicon oxide film. Further, a silicon carbonitride film is formed as a Cu cap film by, for example, a CVD method. By repeating this, a multilayer wiring can be formed.
Although the MPS film is shown as the wiring interlayer low dielectric constant film of this embodiment, it is not particularly limited as long as it is a SiOCH film that can sufficiently ensure the difference in carbon / silicon ratio from the via interlayer low dielectric constant film. The same materials can be applied. Desirably, the carbon / silicon ratio of the wiring interlayer low dielectric constant film is preferably twice or more the carbon / silicon ratio of the via interlayer low dielectric constant film. In addition, in the case of forming a dual damascene opening pattern using the end point detection method for monitoring the plasma emission, the C / Si ratio in the SiOCH film is 1.5 or more in order to suppress the oxidation of the wiring trench side wall by the oxygen ashing process. It is desirable to be.
Although the Aurora ™ film is shown as the via interlayer low dielectric constant film of the embodiment, for example, the carbon / silicon ratio of the via interlayer low dielectric constant film to the carbon / silicon ratio of the wiring interlayer low dielectric constant film, that is, {(C / Si ) Via / (C / Si) wiring} ratio is desirably 0.5 times or less, and the C / Si ratio in the via interlayer low dielectric constant film is 1 or less. Orion, BD / BDII from Applied Materials, CVD-SiOCH film such as Coral from Novellaz, porous SiLK from Dow-Chemical, SiOCH film formed by coating such as NCS from Catalytic Kasei, etc. may be used. Furthermore, a SiOCH film formed by plasma polymerization as disclosed in Patent Document 1 may be used. In view of mounting tolerance, it is preferable to select a material having a higher density in the via interlayer low dielectric constant film than in the wiring interlayer low dielectric constant film. Any of the above materials can be used as the low dielectric constant hard mask. Any film may be used as long as it is a CMP resistant film.
In this example, an example using a silicon charcoal kiln film as a Cu cap film was shown, but the etching selectivity with the low dielectric constant film can be secured, and there is no particular limitation as long as the material has a Cu barrier property, Any material can be used. For example, a silicon carbide film, a silicon nitride film, and the like are listed, but an organic film formed by a plasma polymerization method or a siloxane-containing organic film such as divinylsiloxane / benzoclobutene (DVS-BCB) may be used. .
Furthermore, in the present embodiment, an example in which the MPS film is processed using a hard mask as a mask is shown, but MPS etching may be performed before resist stripping.
(Third embodiment)
In the third embodiment, a multilayer structure will be described.
FIG. 12 is a view showing an embodiment in which a copper multilayer wiring is formed on a carbon-containing low dielectric constant insulating film on a MOSFET 403 separated on a silicon substrate 401 by an element isolation oxide film 402. FIG. The structural features are shown below. Also in this embodiment, by using a mixed gas plasma of Ar / N 2 / CF 4 for MPS etching, groove processing with less in-plane variation, pattern dependency, and wafer-to-lot / lot-to-lot variation is possible. This shows the case where an Aurora ™ film is used as a low dielectric constant film between vias, an MPS film is used as an interlayer film for wiring trenches, and a BDTM film is used as a low-k hard mask. Orion of Applied Materials, BD / BDII of Applied Materials, CVD-SiOCH film such as Coral of Novellaz, porous SiLK of Dow-Chemical, SiOCH film of coating film such as NCS of Catalytic Chemical Co., etc. may be used. Furthermore, a SiOCH film formed by plasma polymerization as shown in Patent Document 1 may be used. A silicon oxide film 405 having a W contact plug 404 is formed on the MOSFET 403, and a 30 nm thick silicon is formed on the silicon oxide film 405 as an etch stop film for a wiring trench corresponding to the first layer copper wiring 406. A carbonitrided film 413 is formed. A 110 nm thick MPS film 414 and a 30 nm thick BD film 415 are formed as a hard mask on the silicon carbonitride film. The silver wiring of the first layer was covered with a barrier film 420 of Ta (10 nm) / TaN (5 nm) in a wiring groove penetrating the laminated insulating film composed of the BD film 415 / MPS film 414 / silicon carbonitride film 413. A Cu film 421 is embedded. This first layer Cu wiring 406 is connected to the W contact plug 404. A 30 nm thick silicon carbonitride film 416 is formed as a via etching stop layer on the first layer Cu wiring 406. Further, an Aurora ™ film 417 having a thickness of 150 nm is formed. The Aurora ™ film 417 may be planarized by CMP or the like. Further, an MPS film 418 having a thickness of 130 nm and a BD film 419 having a thickness of 30 nm are formed as a hard mask on the Aurora ™ film 417. A second Cu wiring 408 in which a Cu film is embedded is formed in a wiring groove that penetrates the BD film 419 / MPS film 418 with respect to the laminated structure insulating film. A first Cu via plug 407 penetrating the Aurora ™ film 417 and the silicon carbonitride film 416 is formed from the bottom of the second copper wiring 408 and connected to the first-layer Cu wiring 406.
By the oxygen plasma cleaning process, the oxidized modified layer 422 exists on the side wall of the Aurora ™ film 417, and the oxidized modified layer 423 thinner than 422 exists on the side wall of the MPS film 418. Such a difference in the amount of oxidation between the wiring portion and the via portion can be easily confirmed by dipping the fracture surface of the device in a dilute hydrofluoric acid aqueous solution. For example, it can be confirmed by dipping for 3 to 5 seconds in an aqueous solution containing 6% HF and 30% NH 4 F. On the other hand, the difference in oxide thickness between the wiring sidewall and the via sidewall is evidence that the manufacturing process according to the present invention and the interlayer insulating film structure in which SiOCH films having different chemical compositions are directly laminated are used. The same structure as the second wiring layer 408 and the via plug 407 can be formed for the Cu wiring layer 410 of the third layer and the Cu via plug 409 connecting the third layer and the second layer, and this structure is overlapped. Thus, a multilayer wiring can be formed.
以上の説明の通り、本発明の多層配線製造方法と多層配線構造と多層配線製造装置は、半導体装置及び電子装置やその製造に適用される。 As described above, the multilayer wiring manufacturing method, multilayer wiring structure, and multilayer wiring manufacturing apparatus according to the present invention are applied to semiconductor devices, electronic devices, and their manufacture.
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| JP2003133411A (en) * | 2001-10-30 | 2003-05-09 | Nec Corp | Semiconductor device and its manufacturing method |
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| JP2004193627A (en) * | 1999-06-24 | 2004-07-08 | Renesas Technology Corp | Method of manufacturing semiconductor integrated circuit device |
| JP2003012776A (en) * | 2001-06-29 | 2003-01-15 | Nec Corp | Method for preparing copolymer film, copolymer film prepared by the same method and semiconductor device utilizing the same polymer film |
| JP2003133411A (en) * | 2001-10-30 | 2003-05-09 | Nec Corp | Semiconductor device and its manufacturing method |
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