WO2007093172A2 - Circuit intégré et procédé pour déterminer la résistance ohmique parasite au moins de la ligne d'alimentation d'au moins une cellule de mémoire d'un circuit intégré - Google Patents

Circuit intégré et procédé pour déterminer la résistance ohmique parasite au moins de la ligne d'alimentation d'au moins une cellule de mémoire d'un circuit intégré Download PDF

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Publication number
WO2007093172A2
WO2007093172A2 PCT/DE2007/000324 DE2007000324W WO2007093172A2 WO 2007093172 A2 WO2007093172 A2 WO 2007093172A2 DE 2007000324 W DE2007000324 W DE 2007000324W WO 2007093172 A2 WO2007093172 A2 WO 2007093172A2
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WO
WIPO (PCT)
Prior art keywords
capacitor
integrated circuit
circuit arrangement
switch
signal propagation
Prior art date
Application number
PCT/DE2007/000324
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German (de)
English (en)
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WO2007093172A3 (fr
Inventor
Marcin Augustyniak
Ralf Brederlow
Alexander Frey
Birgit Holzapfl
Christian Paulus
Jens Sauerbrey
Meinrad Schienle
Roland Thewes
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Infineon Technologies Ag
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Application filed by Infineon Technologies Ag filed Critical Infineon Technologies Ag
Publication of WO2007093172A2 publication Critical patent/WO2007093172A2/fr
Publication of WO2007093172A3 publication Critical patent/WO2007093172A3/fr

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/025—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in signal lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50008—Marginal testing, e.g. race, voltage or current testing of impedance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/14—Measuring resistance by measuring current or voltage obtained from a reference source
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Definitions

  • Integrated circuit arrangement and method for determining the parasitic ohmic resistance of at least the supply line of at least one memory cell of an integrated circuit arrangement are Integrated circuit arrangement and method for determining the parasitic ohmic resistance of at least the supply line of at least one memory cell of an integrated circuit arrangement.
  • the invention relates to an integrated circuit arrangement and a method for determining the parasitic ohmic resistance of at least the supply line of at least one
  • DRAM dynamic random access memory
  • the variations of the device characteristics are completely specified for a given manufacturing process and may be taken into account in the circuit design.
  • parasitic lead resistances are characterized by metallization levels, also referred to as metal levels. If the functional behavior of integrated circuits is critically determined by such parasitic lead resistances, an electrical characterization of the latter for process control is very helpful or even indispensable.
  • the electrical characterization of parasitic lead resistances is generally not trivial because often the leads are not separately electrically accessible and can only be measured together with other elements. Such a situation is given for example with a parasitic ohmic resistance as access to a capacitor. This case occurs, for example, at the gate of a MOS field effect transistor (MOS) or in the DRAM memory cell.
  • MOS MOS field effect transistor
  • Fig.l shows in an arrangement 100, a chip-external
  • Measuring device 101 and an integrated circuit arrangement, integrated circuit (IC) 102 The measuring device 101 is connected by a cable 103 with a bonding connection pad 104 of the integrated circuit arrangement 102nd
  • FIG. 1 For reasons of simpler representation, only one memory cell 105 of a memory cell array having a multiplicity of memory cells arranged in rows and columns is shown in FIG.
  • the dynamic memory cell 105 in other words the memory cell of a dynamic random access memory (DRAM) has a storage capacitor 106 and a parasitic resistor Rparasitic 107 of the supply line to the DRAM.
  • DRAM dynamic random access memory
  • Storage capacitor 106 on.
  • the supply line contains the ohmic resistance of the leading to the storage capacitor 106 supply line and optionally, if in the memory cell 105 for reasons of simplification not shown here selection transistor is provided, for example, the channel resistance of the respective selection transistor.
  • selection transistor is provided, for example, the channel resistance of the respective selection transistor.
  • symbolized in FIG. 1 are the terminal pad capacitance 108, the capacitance of the feeding track 109 and the ohmic resistance 110 of the feeding track.
  • integrated in the integrated circuit arrangement 102 is a component to be tested (in other words the "Device Under Test", DUT), which consists of a capacitor 106 with a parasitic lead resistance 107 which is to be determined Supply lines to the memory cell 105 as well as the interface via the bonding pad 104 cause further capacitances and ohmic resistances.
  • DUT Device Under Test
  • the external measuring device 101 shown symbolically in FIG. 1 serves to determine the parasitic ohmic supply resistance Rparasitic
  • the measurement of such an RC arrangement can generally take place in the time domain or in the frequency domain.
  • the metrological problem scales in this case with the inverse size of the RC constant of the DUT 105.
  • the behavior of the integrated circuit device 102 is dominated by the remaining elements and the influence of the DUT 105 can no longer be resolved, ie, detected.
  • so-called impedance analyzers can be used to determine the parasitic resistive lead resistance of the DUT 105.
  • impedance analyzers can be used to determine the parasitic resistive lead resistance of the DUT 105.
  • impedance analyzers it has not been possible with impedance analyzers to determine the parasitic ohmic lead resistances in a DRAM memory cell.
  • an integrated circuit arrangement which ⁇ at least one electronic component, such as a memory cell has. Furthermore, the integrated
  • Circuit arrangement at least one coupled to the electronic component and with this monolithically integrated resistance-determining circuit for determining the parasitic resistance of at least the supply line to the at least one electronic component.
  • a method for determining the parasitic ohmic resistance of at least the supply line to at least one electronic component of an integrated circuit arrangement electrical quantities which characterize the at least one electronic component are detected on-chip. Using the detected electrical quantities, the parasitic resistance is determined on-chip.
  • an on-chip integrated measuring circuit for measuring and determining the parasitic ohmic resistance of at least the supply line to at least one electronic component, for example one
  • Memory cell in an integrated circuit arrangement. Due to the physical proximity of the circuit, in other words the monolithically integrated resistance detection circuit, to the Device Under Test, in other words the electronic component, for example the memory cell, the additional resistances and capacitances shown in FIG. 1 and described above are avoided ,
  • circuit arrangement may be provided in this monolithically integrated detection circuit for detecting electrical quantities which characterize the at least one electronic component.
  • circuit arrangement may further be provided in this monolithically integrated drive unit for driving the at least one electronic component during the detection of the parasitic ohmic resistance of at least the supply line to the at least one electronic component.
  • the at least one electronic component can be set up as a memory cell.
  • the at least one electronic component may have at least one capacitor.
  • the electronic component may additionally comprise further components, for example a capacitor selection transistor, in the case of the configuration of the electronic component as memory cell, for example as dynamic random access memory cell, a selection transistor for selecting the capacitor with regard to charging or unloading the same with or from electrical charge carriers.
  • the electronic component still contains additional elements, such as a select transistor
  • additional elements such as a select transistor
  • the parasitic resistance of the series connection of the supply line to the capacitor and the elements which in addition to the capacitor in the electronic components is detected, for example, the parasitic resistance of the channel region and the source region or the drain region of the select transistor when it is made in MOS technology, is determined.
  • the at least one electronic component can have at least one capacitor for storing electrical charge carriers and therefore optionally for storing information, for example binary information.
  • the at least one electronic component has a component selection unit for selecting the at least one electronic component, for example one
  • the component selecting unit for selecting the at least one memory cell.
  • the component selecting unit may be formed by at least one component selecting transistor, for example, a memory cell selecting transistor.
  • the at least one memory cell is a dynamic random access memory cell in accordance with an embodiment of the invention.
  • the drive unit is set up to control the charging or discharging of the electronic component with or from electrical charge carriers, for example electrons.
  • the drive unit may further be configured such that the at least one capacitor in a first Actuating phase is substantially fully charged, is partially discharged in a second drive phase and finally discharged in a third drive phase substantially completely.
  • the driving unit may be arranged such that the three driving phases are repeated, e.g. periodically.
  • the drive unit may be configured as a delay locked loop (DLL) circuit, a phase locked loop (PLL) circuit or a ring oscillator circuit, alternatively as any other type of circuit providing the functionality required.
  • DLL delay locked loop
  • PLL phase locked loop
  • ring oscillator circuit alternatively as any other type of circuit providing the functionality required.
  • the detection circuit may be configured to detect at least one of the following electrical quantities:
  • the discharge current of the at least one electronic component for example the discharge current of the at least one capacitor, and / or
  • the voltage applied to the at least one electrical component voltage for example, applied to the at least one capacitor voltage.
  • the resistance detection circuit may be configured to detect the parasitic resistance of at least the lead using the electrical quantities detected by the detection circuit.
  • the resistance-determining circuit may be configured to determine the parasitic ohmic resistance of at least the supply line using formed time averages of the electrical quantities detected during the charging and discharging of the at least one electronic component, for example the capacitor of a memory cell.
  • a time-precise control of charging operations and discharges of electric charge carriers to the electronic component in other words on the "Device Under Test" (DUT) are made possible. From relatively simple to be measured time averages of analog electrical variables, such as the discharge current or the voltage at the electronic component, such as the
  • the parasitic lead resistance can be determined to a capacitance, in other words to the capacitor.
  • the resistance-determining circuit may be arranged such that the parasitic resistance is determined according to the following rule:
  • R is the parasitic resistance of the supply line inside the DUT to the capacitor
  • N is the number of time slots of the charge carried out and discharging of the capacitor
  • Ii is the time average of the charging current during the first activation phase
  • an output amplifier is additionally provided which is coupled on the input side to the at least one electronic component, for example the capacitor, and which provides an amplifier output voltage on the output side.
  • the resistance-determining circuit may be arranged such that the parasitic resistance is determined according to the following rule:
  • N is the number of time slots of charging and discharging the capacitor
  • Ii is the time average of the charging current during the first activation phase
  • array circuit is additionally provided a monolithically integrated in the circuit arrangement unit for compensating for temporal disparities different time slots in the integrated, hereinafter also referred to as ⁇ dynamic element matching unit.
  • the drive unit is set up such that the at least one capacitor in a charging Activation phase is charged and discharged in a discharge An Kunststoffphase.
  • the drive unit may comprise an oscillation measurement circuit, wherein the oscillation measurement circuit is arranged such that
  • the capacitor In the charge-drive phase, the capacitor is charged until a charging threshold is reached,
  • the drive unit Upon the charge threshold being reached, the drive unit is switched to the discharge drive phase, so that the capacitor is discharged; in the discharge drive phase, the capacitor is discharged until a discharge threshold is reached;
  • the drive unit is switched to the charge drive phase so that the capacitor is charged.
  • an integrated circuit is therefore clearly Oszillationsmess' is provided.
  • the parasitic ohmic supply resistance is determined to a capacitor.
  • a monolithically integrated free-running oscillator is provided, the frequency of which is dependent on the parasitic ohmic supply resistance to be determined.
  • the resulting oscillator frequency together with predetermined analog electrical quantities, such as corresponding currents or voltages, enables and forms the basis for the determination of the parasitic resistive supply resistance.
  • the oscillator frequency can be direct, in or on the chip, i. previously divided in the integrated circuit arrangement, determined with an external measuring device. Furthermore, the oscillator frequency can be used to drive an on-chip counter circuit. When specifying a chip-internal or chip-external time base results in the oscillator frequency by simply reading a digital information (bit sequence).
  • the on-chip integrated measuring circuit avoids unwanted parasitic electrical elements.
  • the oscillation measurement circuit comprises a Schmitt trigger whose first threshold is the charge threshold and whose second threshold is the discharge threshold.
  • the drive unit can have:
  • a first current source for providing a charging current for charging the capacitor wherein the first current source can be realized, for example, by means of a current source transistor,
  • a second current source for providing a discharge current for discharging the capacitor wherein the second current source can be realized for example by means of a second current source transistor,
  • At least one switch for selectively coupling the first power source or the second power source to the capacitor
  • the at least one switch is coupled to the output of the Schmitt trigger such that it couples the first current source or the second current source to the capacitor depending on the output signal of the Schmitt trigger.
  • the charging threshold may be a first reference voltage and the discharging threshold may be a second reference voltage.
  • the resistance detecting circuit may be configured such that the parasitic resistance is detected by using the oscillation frequency of the oscillation measuring circuit.
  • the resistance-determining circuit may be arranged such that the parasitic resistance is determined according to the following rule:
  • R is the parasitic resistance of the supply line within the DUT to the capacitor
  • ⁇ u is the difference between the first reference voltage and the second reference voltage
  • At least one reference component for example at least one reference capacitor, may be provided, wherein the
  • Drive unit may be configured such that the at least one electronic component and, for example, the capacitor and the at least one reference component, for example, the at least one reference capacitor, are charged with the same voltage or with two voltages clearly correlated with each other.
  • the expression "two voltages which are clearly correlated with one another" means that the ratio of the two voltages used is known to one another, so that due to the respectively known ratio, the respective different charging processes or discharging processes can be clearly concluded.
  • the integrated circuit arrangement further has, according to an embodiment of the invention, at least one latch capacitor coupled to the capacitor and at least one reference latch capacitor coupled to the reference capacitor.
  • the drive unit further comprises:
  • a first switch connected between a first voltage source and the capacitor, a second switch connected between the first
  • Voltage source and the capacitor is connected or which is connected between a second voltage source and the capacitor
  • a third switch connected between the capacitor and the latch capacitor, • a fourth switch connected between the reference capacitor and the reference buffer capacitor.
  • first switch and the second switch are closed and the third switch and the fourth switch are opened
  • first switch and the second switch are opened and the third switch and the fourth switch are closed
  • the integrated circuit arrangement further comprises a fifth
  • Switch on which is connected between the reference capacitor and a reference potential and a sixth switch, which is connected between the reference intermediate switch capacitor and the reference potential.
  • the fifth switch and the sixth switch thus clearly each form a unit by means of which it is possible, the reference capacitor to a unique potential, the reference potential, for example, the ground potential to discharge or charge before the potential of the
  • Condenser and the reference capacitor are transferred to the latch capacitor or the reference latch capacitor.
  • the drive unit is set up in such a way that the fifth switch and the sixth switch are closed in a first phase (in this phase the latch capacitor and reference latch capacitor are discharged or charged to the reference potential, for example ), and in the second phase the fifth switch and the sixth switch are open (in this phase, for example, the potential which is applied to the capacitor or to the reference capacitor, at least partially transferred to the latch capacitor or to the reference latch capacitor.
  • the resistance-determining circuit is adapted to determine the parasitic resistance of at least the supply line by using the time difference of a charging process of electrical charges of the at least one electronic component, for example the capacitor, and a reloading of electrical charges at least one reference component, for example the at least one reference capacitor.
  • the measurement of the time difference of transhipment processes between a component to be tested, the electronic component (Device Under Test, DUT), for example a DRAM memory cell, and a known reference structure can be measured.
  • the integrated circuit arrangement further comprises a comparator whose first input is coupled to the electronic component and whose second input is coupled to a third voltage source. Furthermore, a reference comparator is provided, whose first input is coupled to the reference component and whose second input is coupled to the third voltage source or to a fourth voltage source.
  • the resistance detection circuit according to this embodiment is arranged to detect the parasitic ohmic resistance of the lead using the temporal
  • a first signal propagation path can be provided in the integrated circuit arrangement, for example downstream of the comparator, with at least one first signal propagation delay element.
  • a second signal propagation path for example downstream of the reference comparator, may be provided with at least one second signal propagation delay element.
  • the at least one second signal propagation delay element can be set up such that its signal propagation delay is greater than that of the at least one first signal propagation delay element.
  • the first signal propagation path has a plurality of series-connected first signal propagation delay elements, wherein one or more first signal propagation delay elements are grouped into a first signal propagation delay stage.
  • Signal propagation path may include a plurality of serially connected second signal propagation delay elements, wherein one or more second signal propagation delay elements are grouped into second signal propagation delay stages.
  • a bistable flip-flop such as a flip-flop
  • a bistable multivibrator can be connected between the output of at least a part of the first signal propagation delay stages and a corresponding second signal propagation delay stage.
  • the at least one first signal propagation delay element may be formed by at least one first inverter, and the at least one second signal propagation delay element may be formed by at least one second inverter.
  • the resistance-determining circuit may be arranged to determine the parasitic resistance of the lead using the outputs of the bistable flip-flops.
  • the integrated circuit arrangement may comprise a first reference structure having signal propagation delays whose signal propagation delay is equal to that of the first signal propagation delay elements. Furthermore, a second reference structure may be provided which has signal propagation delay elements whose signal propagation delay is equal to that of the second signal propagation delay elements.
  • the first reference structure has a first ring oscillator with the signal propagation delay elements and the second
  • Reference structure comprises a second ring oscillator with the second signal propagation delay elements.
  • the resistance-determining circuit may be arranged such that the parasitic resistance is determined according to the following rule:
  • N the number of the signal propagation delay stage at which the state of the associated bistable multivibrator changes compared to the bistable multivibrator immediately preceding it
  • k the number of signal propagation delays in the first reference structure, the number of signal propagation delay elements in the first reference structure and the number of signal propagation delay elements in the second reference structure is the same
  • Figure 1 is a plan view of a circuit arrangement
  • Figure 2 is a plan view of a monolithic integrated circuit
  • Figure 3 is a detailed illustration of a monolithic integrated circuit arrangement according to an embodiment of the invention.
  • Figures 4A and 4B is an illustration of a charge and discharge cycle for the device under test of the circuit arrangement of Figure 3 ( Figure 4A) and the corresponding drive signals for the switches provided in the circuit arrangement of Figure 3 ( Figure 4B );
  • Figure 5 is a detailed illustration of a monolithic integrated circuit arrangement according to another embodiment of the invention;
  • Figure 6 is a detailed illustration of a monolithic integrated circuit arrangement according to another embodiment of the invention.
  • FIG. 7 is a detailed illustration of the voltage source circuit of the circuit arrangement of Figure 6;
  • FIG 8 is a diagram in which the time course of
  • FIG 9 is a diagram in which the time course of
  • Figure 10 is a diagram in which the accuracy of
  • Figure 11 is a diagram in which the accuracy of
  • Figure 12 is a detailed illustration of a monolithic integrated circuit arrangement according to another embodiment of the invention.
  • 2 shows a plan view of a monolithic integrated circuit arrangement 200 according to the exemplary embodiments of the invention.
  • the basic structure of the monolithic integrated circuit arrangement 200 according to the exemplary embodiments of the invention described below is continuous, as shown in FIG.
  • the circuit arrangement 200 has one or a plurality of chip-external connection pads 201, wherein the connection pad 201 is connected by means of one or more electrically conductive tracks 202 to an electronic component 203 to be tested.
  • the electrical component may be any electrical component on or in a wafer, generally in an integrated circuit.
  • the electronic component 203 to be tested has a capacitor 204, such as a capacitor of a memory cell, such as a dynamic random access memory (DRAM) memory cell, without limitation of algo- rality.
  • a capacitor 204 such as a capacitor of a memory cell, such as a dynamic random access memory (DRAM) memory cell, without limitation of algo- rality.
  • DRAM dynamic random access memory
  • the electronic component 203 is a transistor, wherein, for example, the gate terminal of the transistor is connected by means of a feed line 205 with the electrically conductive conductor 202, for example made of aluminum or copper.
  • the electronic component 204 is coupled by means of a feed line 205, for example additionally by means of a switched in the supply selection transistor (select transistor), with the electrically conductive conductor 202, wherein the supply line is made of polysilicon, for example.
  • the supply line 205 has a parasitic ohmic resistance R, which is to be determined by means of the monolithic integrated circuits described below.
  • any number of electronic components whose parasitic ohmic lead resistances, for example, the respective supply to the metallic electrically conductive tracks 202 are to be determined, may be provided in the integrated circuit arrangement 200 can, for example, a plurality of thousands or millions, for example, in a memory array, provided memory cells, each of which is formed by a respective capacitor and a capacitor upstream of the respective selection transistor, in each case, the parasitic ohmic supply resistance of the supply line between the capacitor 204 and the electrically conductive trace 202 of aluminum or copper to determine.
  • a detection circuit 206 which is coupled to the conductor track 202 and which detects electrical quantities which characterize, for example, the electronic component 204 and / or the parasitic ohmic lead resistance 205.
  • a likewise monolithically integrated in the circuit arrangement 200 drive unit 207 is used to drive the electronic component 204 and optionally additionally provided in the circuit arrangement provided power sources or voltage sources (not shown in Figure 2 for the sake of a simplified and comprehensible representation).
  • 3 shows a detailed illustration of a monolithic integrated circuit arrangement 300 according to an embodiment of the invention.
  • the parasitic ohmic feed line resistance is the parasitic ohmic trench resistor (trench resistor) of a DRAM memory cell as electronic component 301.
  • the integrated circuit assembly 300 has the following components monolithically integrated therein:
  • An electronic component 301 which is a capacitor
  • the capacitor 302 is coupled by means of the lead to a node 304, which is coupled to a first input 305 of a first switch SWi 306, the second terminal 307 is coupled to a first current detection circuit 308 for detecting a first current I ⁇ , which in The following will be explained in more detail.
  • a voltage source 309 which provides an electrical voltage Vi.
  • the node 304 is coupled to a first terminal 310 of a second switch SW2 311, whose second terminal 312 is coupled to the ground potential.
  • the node 304 is coupled to a first terminal 313 of a third switch SW3 314 whose second terminal 315 is coupled to a second current detection circuit 316 for measuring a third current I3.
  • the second Current sense circuit 316 is further coupled to the ground potential.
  • three RS flip-flops 317, 318, 319 are provided in the circuit arrangement 300, wherein the output 320 of a first RS flip-flop 317 is coupled to the control input 321 of the first switch SW] _ 306 and this controls.
  • the second RS flip-flop 318 is coupled at its output 322 to the control input 323 of the second switch SW2 311 and controls this by means of the output signal of the second RS flip-flop 318th
  • the output 324 of the third RS flip-flop 319 is coupled to the control input 325 of the third switch SW3 314 and controls this, in other words opens this or
  • the inputs of the RS flip-flops 317, 318, 319 are optionally coupled to an intermediate Dynamic Element Matching unit 326 with outputs of a Delay Locked Loop circuit 327, such that the reset input 329 of the first RS flip-flop 327 Flops 317 is timed after the set input 328 of the first RS flip-flop 217 from the delay locked loop circuit 327 with a high level (DLL) signal.
  • DLL high level
  • the reset input 331 of the second RS flip-flop 318 timed after the set input 330 of the second RS flip-flop 318.
  • the set input 332 of the third RS flip-flop 319 is timed to the reset input 331 of the second RS flip-flop 318 with a high-level signal, and finally, in a respective cycle, the reset input 333 of the third RS flip-flop 319 timed after the set input 332 of the third RS flip-flop 319 with a high-level signal.
  • a phase-locked loop circuit PLL circuit
  • a ring oscillator circuit for example with a plurality of series-connected inverters, may be provided for providing the corresponding drive signals.
  • a DRAM memory cell 301 is connected to the voltage source 309 by means of the first switch SWi 306 when it is closed, and thus charged.
  • the DUT 301 is discharged in two non-overlapping partial discharge processes, such that first (in a first partial discharge phase) via the then closed second switch SW2 311, the charge carriers stored on the capacitor 302 partially drain as a second current flow I2 and in a second partial discharge phase, when the second switch SW2 311 is opened and the third switch SW3 314 is closed, by means of the third switch SW3 314 is substantially completely discharged, wherein a third current I3 flows and is detected by the second current measuring circuit 316.
  • a first partial discharging process 402 and a second partial discharging process 403 are shown in a time diagram 400 in FIG. 4A.
  • the pulse duration for the respective switches 306, 311, 314 is derived. If a ring oscillator circuit is used instead of the DLL circuit 327, for example when using a 70 nm process technology, a time delay of 1 ns can be achieved with a series connection of six inverters.
  • the first switch SWi 306 is active, in other words, closed (cf.
  • Switch aging diagram 450 in FIG. 4B corresponding to the first switch control signal 451 for the first switch SWi 306, which corresponds to the output signal of the first RS flip-flop 317.
  • the first switch driving signal 451 is at the low level until the beginning of the charging operation 401 (thus, the first switch SWi 306 is opened), changing at the beginning of the
  • T charging process 401 (time) to high level (which the first switch SWi 306 is closed) and returns to the low level (time "0") upon completion of the charging process, with the first switch SWi 306 is opened again.
  • a first flows
  • the second switch SW2 311 opened during the charging process 401 is closed (time "0") (see second switch driving signal 452 in Fig. 4B) ) and remains closed for the duration of a time slot whose duration is defined according to T / N, where N is the number of time slots during the period T, whereby during the first partial discharge phase 402 via the second switch SW2 311 a first Part discharge current I2 (in Fig.4A shown as a time course I (t), measured as the average I2) flows.
  • the first switch SWi 306 and the third switch SW3 314 are opened.
  • FIG. 4A shows the partial discharge during the first partial discharge process 402 in a first partial discharge curve 405.
  • the third switch SW3 314 is closed by means of the third switch drive signal 453, in that the third switch drive signal 453, which previously had a low level during the charging process 401 and the first partial discharge process 402, rises to high level and thus the third switch SW3 314 closes (time T / N).
  • the residual charge still remaining on the capacitor 302 discharges through the third switch SW3 314 and the second measuring circuit 316 to the ground potential, whereby a third current I3 (shown in FIG. 4A as time characteristic I (t ), measured as r ⁇
  • Mean value I3) flows (until a time - at which the
  • the first switch SWi 306 is active and the DUT 301 is charged, with an exponentially decaying first current Ii flowing.
  • the DUT 301 is discharged.
  • An exponential discharge current with the opposite sign, but for example the same amount, flows.
  • the discharge current first flows in the first partial discharge phase 402 via the second switch SW2 411 and then, in the second partial discharge phase 403, via the third switch SW3 314.
  • R is the parasitic resistive line resistance to be determined
  • the specification of the voltage Vi and the measurement of the current values Ii and I3 is thus required.
  • a parameter analyzer for example the company Agilent, can be used, for example, to determine the above-mentioned current values. The accuracy of the method is then determined by the precision of the time base generated by DLL circuit 327.
  • the accuracy of the time base and thus the determination of the parasitic ohmic supply resistance can, as is schematically indicated in FIG. 3, be improved with an optional "Dynamic Element Matching", wherein by means of the Dynamic Element Matching unit 326 any existing inequalities of the time slots, which under the Charging process and the unloading process are to be timed out.
  • FIG 5 shows an integrated circuit arrangement 500 according to another embodiment of the invention.
  • the circuit arrangement 500 according to FIG. 5 has a fourth switch SW4 501, a fifth switch SW5 502 and a sixth switch SWg 503. Furthermore, a selection logic, in other words a selection circuit 504 is provided, which is coupled to
  • the select logic 504 thus controls the switching behavior of the following switches:
  • the fifth switch SW5 502 and
  • a first terminal 508 of the fourth switch SW4 501 is coupled to 'the second terminal 313 of the third switch SW3 314th
  • the second terminal 509 of the fourth switch SW4 505 is coupled to the node 304.
  • the fourth switch SW4 501 is thus connected between the third switch SW3 314 and the node 304.
  • the first terminal 510 of the fifth switch SW5 502 is coupled to the node 304
  • the second terminal 511 of the fifth switch SW5 502 is coupled to an input 512 of a buffer amplifier 513 to the output 514 of which an output voltage ⁇ VOUT is provided.
  • the second terminal 515 of the sixth switch SWg 503 is coupled, the first terminal 516 of which is connected to the ground potential.
  • a buffer capacitor 517 which is additionally coupled to the ground potential, is coupled to the second terminal 511 of the fifth switch SW5 502 and to the input 512 of the buffer amplifier 513.
  • the charging operations and the (partial) discharging operations controlled by the switches SWi 306, SW2 311 and SW3 314 are the same as those explained above in connection with the circuit arrangement 300 of Fig. 3 and Figs. 4A and 4B were.
  • Buffer amplifiers 513 enable the measurement of a voltage value, the output voltage ⁇ VQUT TO a
  • the embodiment according to FIG. 5 thus requires the presetting of the voltage Vi and the measurements of the current value Ii and the voltage ⁇ VQUT.
  • the measurement principle of the circuit arrangements 300, 500 is based on the precise timing of charging and discharging operations of the DUT 301 by means of the drive circuit 327.
  • the measurement of time averages of analog electrical variables, such as the discharge current or the voltage allows the determination of the resistive portion in the DUT 301.
  • the method is only due to the precision of the DLL circuit 327, generally the
  • Timer circuit 327 limited and is therefore suitable, for example, just for small values of the RC constant.
  • the measuring effort is low and can be measured, for example, with standard measuring instruments, such as a Parameter analyzer from Agilent. • For the determination of the parasitic ohmic
  • Fig. 6 shows an integrated circuit assembly 600 according to another embodiment of the invention.
  • the DUT 501 is also a dynamic random access memory cell having a trench capacitor 602 of capacitance CT and a select transistor 603 for selecting the respective memory cell 601 according to a select signal supplied via a word line 604 to the gate terminal of the select - Transistor 603 is performed.
  • the selection transistor 603 is shown in order to make it clear that, if necessary, an additional ohmic resistance is taken into account or additionally determined in the determination of the parasitic ohmic supply resistance RT 605 of the DUT 601, in this case the resistance .des Select transistor 603 formed by the distance of the source region, the channel region and the drain region of the select transistor 603.
  • the first source / drain region 606 of the select transistor 603 is coupled to the trench capacitor 602 by way of the feed line to the line resistor 605.
  • the second source / drain region 607 of the select transistor 603 is coupled to a bit line 608 and above to the input
  • Schmitt trigger circuit 610 of a Schmitt trigger circuit 610 coupled.
  • the reference voltages U re fi and U re f2 are used to adjust the two Sehaltschwellen the Schmitt trigger circuit 610.
  • the output 612 of the Schmitt trigger circuit 610 is fed back to two switches, namely the control input 613 of a first switch 614 and the control input 615 of a second switch 616.
  • a first terminal 617 of the first switch 614 is coupled to a first current source 618, which provides a current +1 and which is realized, for example, by means of a current source transistor.
  • the second terminal 619 of the first switch 614 is coupled in a first switch position to a second reference voltage U re f2 620 and in a second switch position to a node 621 which is coupled to the bit line 608.
  • a first terminal 622 of the second switch 615 is coupled to a second current source 623, which has one to the
  • the two switches 614 and 616 are switched in such a way that in each case only one of the two switches is coupled to the node 621 and thus either the current +1 or the current -I flows to the bit line 608.
  • the other of the two switches 614, 616 is in each case at one of the two reference voltages and is thereby pre-charged to the voltage value (pre-charged), in which the node 621 is located when the device is switched on again. This reduces the Influence of parasitic capacitances and stabilizes the operating point of the current sources 618, 623, which are realized for example by means of current source transistors.
  • the two switches 614, 616 are thus activated depending on the binary output state and thus the binary output signal of the Schmitt trigger circuit 610.
  • Fig. 7 shows the Schmitt trigger circuit 610 in detail.
  • the Schmitt trigger circuit 610 has a third switch 701 whose control input 702 is coupled to the output 612 of the operational amplifier 611 and whose first input 703 is coupled to a reference voltage input 626 of the operational amplifier 611 and whose second input 704 each is coupled to switch position either to a first voltage source 705 (first switch position of switch 701) which provides the voltage (U + ⁇ U) and coupled in a second switch position to a second voltage source 706 which provides the voltage (U - ⁇ U).
  • the measuring circuit in the circuit arrangement 600 corresponds to a free-running oscillator for determining the trench resistor RT.
  • a current +1 is impressed in a first phase, which from the first current source 618 via the first switch 614, which is in the Wegerpositiori such that the current +1 from the first current source 618 to the node 621 and thus to the bit line BL 608 and above into the trench capacitor 602.
  • the current +1 causes a time independent voltage drop I * RT on bit line 608, as in the voltage diagram
  • the voltage on the bit line BL 608 increases linearly with time (depending on the current +1 and the trench capacitance CT, in other words the capacitance of the trench capacitor 602).
  • the voltage on the bit line BL 608 is measured by a comparator circuit with the Schmitt trigger circuit 610.
  • the bit line BL 608 Upon reaching an upper voltage reference value U re fi, which is provided by the first voltage source 705, the bit line BL 608 is switched to a current source of equal amplitude but inverse sign, namely the second current source 623, which provides the current -I. This is done by bringing the first switch 614 to the second switch position at this time and coupling it to the second reference voltage U re f2 and bringing the second switch 616 into its second switch position and thus the second current source 623 to the node 621 and is coupled thereto via the bit line BL 608.
  • the voltage drop I * RT thus changes its direction and the voltage decreases linearly with time, as also shown in Fig.8.
  • the second reference voltage U re f2 / which is provided by the second voltage source 706, the first current source is reconnected and the process repeats. This is done by bringing the second switch 616 from its second switch position to its first switch position and thereby coupling it to the first reference voltage U re fi 625.
  • the first switch 614 is again brought into its first switch position, which in turn the first current source 618 with the Node 621 and above is coupled to bit line BL 608.
  • the accuracy of the resistance determination of the parasitic ohmic resistance of the supply line RT is to be determined as a function of inaccuracies of the variables I, ⁇ U and CT.
  • the quantities ⁇ j and ⁇ ⁇ u are inaccuracies of the current generation and the reference voltage generation or
  • I, ⁇ U, C ⁇ and f are nominal values.
  • the output voltage UouT ' which is provided at the output 612 of the Schmitt trigger circuit 610, is shown in its time history in the voltage diagram 900 in FIG.
  • FIGS. 10 and 11 show the evaluation of equation (15) as a function of the oscillation frequency f (see graph 1000 in FIG. 10) or of the current corresponding thereto (compare graph 1100 in FIG. 11).
  • the determination of the value for the capacitance CT of the trench capacitor 602 is given.
  • a measuring process is provided in which the value of the trench capacitance 0 ⁇ of the trench capacitor 602 in a first step at low frequencies (currents) , for example, using the same circuit arrangement 600, as shown in Figure 6, is determined exactly.
  • the parasitic ohmic supply resistance RT to be determined is subsequently measured at moderate frequencies.
  • Resistance accuracy is achieved with a measurement frequency below 100 MHz, when the uncertainty of the capacitance CT of the trench capacitor 602 is limited to 1% (see first curve 1001 in Fig. 10).
  • Fig. 12 shows an integrated circuit arrangement 1200 according to another embodiment of the invention.
  • DUT 1201 which is a trench capacitor
  • a dynamic random access memory memory cell contains in an array a plurality, for example, thousands or millions of trench capacitors as DRAM memory cells in a corresponding memory cell array.
  • a buffer capacitor 1204 as well as a reference capacitor 1205 and a reference buffer capacitor 1206 are provided in FIG.
  • the circuit arrangement 1200 has a first switch S1 1207, a second switch S2 1208, a third switch S3 1209, a fourth switch S4 1210, a fifth switch S5 1211 and a sixth switch S6 1212.
  • the first switch Sl 1207 is connected between the DUT 1201 and a reference voltage Vi n 1213.
  • the fourth switch S4 1210 is coupled between the reference voltage 1213 and the reference capacitor 1205.
  • the second switch S2 1208 is connected between the DUT 1201 and the latch capacitor 1204.
  • the third switch S3 1209 is coupled between the ground potential and thus a first terminal of the latch capacitor 1204 and the second terminal of the latch capacitor 1204 and thus short-circuits the latch capacitor 1204 when the third switch S3 1209 is closed.
  • the fifth switch S5 1211 is coupled on the one hand to the reference capacitor 1205 and on the other hand to the reference latch capacitor 1206.
  • the sixth switch S6 1212 is between a first one
  • Terminal of the reference latch capacitor 1206 and the second terminal of the reference latch capacitor 1206 and closes this to the ground potential for a short time when the sixth switch S6 1212 is closed. Furthermore, a first comparator 1214 and a second comparator 1215 are provided.
  • the first input 1216 of the first comparator 1214 is coupled to one terminal of the latch capacitor 1204, the second switch S2 1208, and the third switch S3 1209.
  • the second input 1217 of the first comparator 1214 is coupled to a second reference potential Vi n / 3 1218.
  • the first input 1219 of the second comparator 1215 is coupled to the reference latch capacitor 1206 and to the fifth switch S5 1211 and the sixth switch S6 1212.
  • the second input 1220 of the second comparator 1215 is coupled to one terminal of the reference latch capacitor 1206, the sixth switch S6 1212 and the fifth switch S5 1211 coupled.
  • the output 1221 of the first comparator 1214 is coupled to a first input 1222 of a first flip-flop circuit 1223 and further to a first inverter 1224 of a first delay stage 1225 having an additional series-connected second inverter 1226.
  • the circuit arrangement 1200 in addition to the first delay stage 1225, there are also five further delay stages 1227, 1228, 1229, 1230, 1231 connected in series, each with two series-connected inverters.
  • Each delay stage 1227, 1228, 1229, 1230, 1231 has a delay for the signal propagation of the output signal of the first comparator 1214 of 450 ps according to this embodiment of the invention.
  • the output 1232 of the second comparator 1215 is coupled to a second input 1233 of the first flip-flop circuit 1223. Further, the output 1232 of the second comparator 1215 is coupled to the input of a first reference inverter 1234 of a first reference delay stage 1235 which additionally includes a second reference inverter connected in series with the first reference inverter 1234 1236 has.
  • the first delay stage according to this embodiment of the invention, five further delay stages 1237, 1238, 1239, 1240, 1241 followed.
  • any number of delay stages in series may be connected in series to the output 1232 of the second comparator 1215 and any number of delay stages in series to the output 1221 of the first comparator 1214 for the respective time delay of the signal propagation of the first comparator 1214 Output signal of the second comparator 1215 and the first comparator 1214, respectively.
  • Each reference delay stage 1234, 1236, 1237, 1238, 1239, 1240, 1241 produces a time signal propagation delay of a signal applied to its input with respect to its output signal of 500 ps.
  • the reference inverters are according to this
  • Embodiment of the invention a greater time delay than the inverters connected to the first comparator 1214 delay stages.
  • Delay stages or reference delay stages corresponding flip-flop circuits 1242, 1243, 1244, 1245, 1246 provided (in the present example, six flip-flop circuits are thus provided in the circuit arrangement 1200), wherein a respective first input of the respective flip Floating circuit 1247, 1248, 1249, 1250, 1251 between a respective output of a Delay stage and the input of a downstream delay stage is connected.
  • a respective second input 1252, 1253, 1254, 1255, 1256 of a respective flip-flop circuit 1242, 1243, 1244, 1245, 1246 is connected between a respective output of a reference delay stage 1234, 1236, 1237, 1238, 1239, 1240, 1241 and the respective input of a respective downstream reference delay stage switched.
  • the respective outputs 1257, 1258, 1259, 1260, 1261, 1262 of the flip-flop circuits 1223, 1242, 1243, 1244, 1245, 1246 are coupled to an output register 1263 into which the respective output values of the flip-flop circuits Circuits 1223, 1242, 1243, 1244, 1245, 1246 are written.
  • any other delay elements can be provided which provide a time delay for the signal propagation of the respective output signal of the comparators 1214, 1215.
  • Ring oscillator circuit 1264 having inverters 1265, 1266, 1267, 1268, 1269 coupled in series with one another and a binary counter 1270 coupled to the output of inverter 1269, which provides a signal having a first frequency f 1, the Inverter of the first ring oscillator circuit 1264 has the same timing and thus the same temporal
  • a signal having a second frequency .2 .2 providing second ring oscillator circuit 1271 is provided, which has five reference inverters 1272, 1273, 1274, 1275, 1276, wherein the inverters of the second Ring oscillator circuit 1271 have the same timing and thus the same time signal propagation delay as the reference inverters of the reference delay stages 1235, 1237, 1238, 1239, 1240 and 1241.
  • the second ring oscillator circuit 1271 has a second binary counter 1277 which is coupled to the output of inverter 1276.
  • circuit arrangement 1200 can be clearly seen in the measurement of the time difference of recharging events between the DUT 1201 (for example, a DRAM memory cell) and a known reference structure (the reference capacitor, the reference latch capacitor , the second comparator 1215 and the reference delay stages).
  • the DUT 1201 for example, a DRAM memory cell
  • a known reference structure the reference capacitor, the reference latch capacitor , the second comparator 1215 and the reference delay stages.
  • the nodes Vl and V4 are charged to an initial potential V ⁇ n by closing the first switch Sl 1207 and the fourth switch S4 1210.
  • the nodes V2 and V5 are reset to zero potential according to this embodiment by also closing the third switch S3 1209 and the sixth switch S6 1212 in this phase, so that the nodes V2 and V5 are discharged to the ground potential.
  • the first switch Sl 1207, the third switch S3 1209, the fourth switch S4 1210 and the sixth switch S6 1212 are opened and the second switch S2 1208 and the fifth switch S5 1211 are closed. In this way, the potentials are equalized at the nodes V1 and V2 or at the nodes V4 and V5.
  • the compensation between the voltages at the nodes V1 and V2 is slower than the compensation of the voltages at the nodes V1 and V2
  • the output of the second comparator 1215 is switched earlier and thus faster than the first comparator 1214 (in other words, this means that the potential at the node V6 assumes a high level faster than the node V3, i.e., the output of the first comparator 1214.
  • the output signals of the comparators 1214, 1215 which are in digital form, propagate through the inverter chains (also referred to as the Verier line).
  • the state of the flip-flop circuits changes at the point where the time delay of the signals between the outputs of the two comparators 1214, 1215 is equal to the skew of the inverter chains, i. the respective delay stages or reference delay stages.
  • the two ring oscillator circuits 1264, 1271 are additionally provided, which provide a frequency reference.
  • the sought parasitic resistive impedance R is calculated according to the following rule:
  • N is the stage number of the delay stage or the reference delay stage, at which the state of the respective flip-flop circuit changes
  • K is the number of delay stages provided in the respective ring oscillator circuit 1264, 1271,
  • F2 is the frequency of the second ring oscillator circuit 1271
  • the capacity of the trench capacitor 1202 is assumed to be known or determined by means of measuring methods known per se, for example in the manner described above in connection with the exemplary embodiments according to FIG.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un circuit intégré comprenant au moins un composant électronique, ainsi qu'au moins un circuit de détermination de résistance connecté à ce composant électronique et intégré monolithiquement avec celui-ci, ce circuit de détermination de résistance servant à déterminer la résistance ohmique parasite au moins de la ligne d'alimentation reliée à ce composant électronique.
PCT/DE2007/000324 2006-02-16 2007-02-16 Circuit intégré et procédé pour déterminer la résistance ohmique parasite au moins de la ligne d'alimentation d'au moins une cellule de mémoire d'un circuit intégré WO2007093172A2 (fr)

Applications Claiming Priority (2)

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DE200610007321 DE102006007321A1 (de) 2006-02-16 2006-02-16 Integrierte Schaltkreis-Anordnung und Verfahren zum Ermitteln des parasitären ohmschen Widerstands zumindest der Zuleitung zumindest einer Speicherzelle einer integrierten Schaltkreis-Anordnung
DE102006007321.5 2006-02-16

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WO2009076237A1 (fr) * 2007-12-06 2009-06-18 Qualcomm Incorporated Procédé et appareil permettant d'estimer la résistance et la capacité d'interconnexions métalliques
WO2015183680A1 (fr) * 2014-05-30 2015-12-03 Allegro Microsystems, Llc Circuit intégré et procédé associé pour la mesure d'une impédance externe

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Cited By (7)

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Publication number Priority date Publication date Assignee Title
WO2009076237A1 (fr) * 2007-12-06 2009-06-18 Qualcomm Incorporated Procédé et appareil permettant d'estimer la résistance et la capacité d'interconnexions métalliques
US7973541B2 (en) 2007-12-06 2011-07-05 Qualcomm Incorporated Method and apparatus for estimating resistance and capacitance of metal interconnects
KR101119453B1 (ko) 2007-12-06 2012-03-16 퀄컴 인코포레이티드 금속 인터커넥트의 저항 및 커패시턴스 추정을 위한 방법 및 장치
WO2015183680A1 (fr) * 2014-05-30 2015-12-03 Allegro Microsystems, Llc Circuit intégré et procédé associé pour la mesure d'une impédance externe
KR20170015335A (ko) * 2014-05-30 2017-02-08 알레그로 마이크로시스템스, 엘엘씨 외부 임피던스의 측정을 위한 집적 회로 및 관련 방법
US9575103B2 (en) 2014-05-30 2017-02-21 Allegro Microsystems, Llc Integrated circuit and associated methods for measurement of an external impedance
KR102025590B1 (ko) 2014-05-30 2019-11-04 알레그로 마이크로시스템스, 엘엘씨 외부 임피던스의 측정을 위한 집적 회로 및 관련 방법

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