Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L3/00—Starting of generators
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
  • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
  • H03B5/02—Details
  • H03B5/06—Modifications of generator to ensure starting of oscillations
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
  • H03L5/00—Automatic control of voltage, current, or power

Definitions

• the present embodiments relate to an oscillator. More specifically, the present embodiments relate to an oscillator having a decreased start-up time and low noise in steady state operation.
• the crystal resistance is not constant, typically being higher at start-up than when oscillating in steady state.
• the crystal resistance is related to the Q factor of the oscillator, which determines the amount of power applied to the crystal to keep it oscillating at the same amplitude. As the resistance decreases, the amount of power consumed decreases.
• the variation in the crystal resistance causes more power to be used at start-up than is desired to achieve the best noise performance in steady state operation.
• decreasing the power such that optimal noise performance is achieved in steady state increases the amount of time for the crystal oscillator to reach steady state from start-up.
• crystals in a batch of crystals may have different steady state oscillation frequencies over a particular amplitude range.
• variations in the ambient temperature of the oscillator circuit may cause the steady state oscillation amplitude of a particular crystal to fluctuate due to changes in the gain of the circuit. It is thus additionally desirable to provide an arrangement that provides compensation for both crystal- to-crystal variation and temperature variation for a single crystal.
• Figure 1 illustrates an AGC loop according to one embodiment.
• Figure 2 illustrates the AGC loop of Fig. 1 when in analog mode.
• Figure 3 illustrates the AGC loop of Fig. 1 when in digital mode.
• Figure 4 show graphs of the oscillator, reference, and start signals with respect to time for one embodiment of the AGC loop.
• Figure 5 is a graph showing the phase noise vs. oscillator output for the AGC loop shown in Fig. 1 when in digital mode.
• a hybrid automatic gain control (AGC) loop for a frequency source is presented.
• the hybrid AGC loop contains both an analog AGC loop and a digital AGC loop.
• the AGC monitors the amplitude of a crystal oscillator of the frequency source.
• the analog AGC loop controls excitation of the crystal oscillator at start-up time, and the digital AGC loop controls excitation of the crystal oscillator after steady state operation has been achieved.
• the AGC feedback loop adjusts the gain of the oscillator to keep the amplitude substantially constant. This permits the AGC loop, which introduces noise that can modulate the oscillator, to initially have a faster starting analog mode and then switch into a digital mode.
• the oscillator output changes occur relatively slowly compared with the analog mode as the digital controller is updated at a slower rate.
• the digital mode produces lower noise than the analog mode.
• the hybrid AGC loop can be used in any product in which a low noise oscillator is desired, such as a tuner integrated circuit for communication equipment.
• FIG. 1 shows one embodiment of a hybrid AGC.
• the hybrid AGC 100 includes an amplitude-controllable oscillator 102, a peak detector 104, an error integrator 106, a multiplexer (MUX) 108, a first comparator 110, a counter (timer) and digital control logic block 112, a digital-to-analog converter (DAC) 114, a low pass filter 116, and a second comparator 118.
• MUX multiplexer
• DAC digital-to-analog converter
• the oscillator 102 is a crystal oscillator, which contains a quartz crystal. The crystal is excited by a power supply to produce sine wave oscillations of an amplitude that depends on the excitation power.
• An output of the oscillator 102 is connected to an input of the peak detector 104.
• the peak detector 104 is an analog circuit that detects the peak amplitude of the oscillator 102.
• An output of the peak detector 104 is supplied to an input of the error integrator 106 and an input of the first comparator 110.
• a view of the AGC loop 100 when in analog mode is shown in Fig. 2. Figure 2 illustrates that during start-up, the feedback path to control the amplitude of the oscillator 102 includes the peak detector 104, the error integrator 106, and the MUX 108.
• the error integrator 106 is also supplied with a reference voltage.
• the reference voltage may be provided by, in one embodiment, a voltage divider connected between the power supply and ground.
• the power supply in turn may be a regulated supply voltage (e.g. a battery).
• the voltage divider may contain fixed or adjustable resistors. Accordingly, the reference voltage supplied to the error integrator 106 can be set to any desired value.
• the error integrator 106 compares the peak value detected by the peak detector 104 with the reference voltage and integrates a difference between the output of the peak detector 104 and the reference voltage.
• the error integrator 106 can be implemented by an analog circuit.
• the error integrator 106 includes an operational amplifier (op-amp) having an inverting input to which the signal from the peak detector 102 is supplied through a resistor, a non-inverting input to which the reference voltage is supplied, and a capacitor connected between an output of the op-amp and the inverting input.
• An output of the error integrator 106 is supplied to one input of the MUX 108.
• the selector of the MUX 108 is connected to the counter and logic circuitry 110, which supplies a selection signal to the MUX 108.
• the MUX 108 selects the output of the error integrator 106 when the hybrid AGC 100 is in analog mode, such as during start-up.
• An output of the MUX 108 is supplied to the oscillator 102 to drive the crystal in the oscillator.
• Fig. 3 shows a view of the AGC loop 100 when in digital mode.
• Figure 3 illustrates that during steady state operation the feedback path to control the amplitude of the oscillator 102 includes the peak detector 104, the first comparator 110, the counter and digital logic block 112, the digital-to- analog converter (DAC) 114, the low pass filter 116, and the MUX 108.
• An output of the peak detector 104 is supplied to an input of the first comparator 110.
• the first comparator 110 is also supplied with at least two reference voltages. These reference voltages are different and may be supplied by a voltage divider or other circuitry in a manner similar to that of the reference voltage supplied to the error integrator 106.
• the reference voltages supplied to the first comparator 110 represent the range of acceptable amplitude voltages supplied by the oscillator 102 before the power to the oscillator 102 is to be adjusted.
• an output of the first comparator 110 is supplied to the DAC 114 through counter and logic circuitry block 112.
• the reference voltages supplied to the first comparator 110 are the low and high voltages of the amplitude of the oscillator 102 before the output of the DAC 114 is adjusted. For example, if the oscillator 102 has a nominal IV peak to peak, the low and high reference voltages may be 0.95V and 1.05V, respectively.
• Counter and logic circuitry block 112 contains a first counter (up/down counter) and a second counter (ripple counter).
• First comparator 110 and the up/down counter of counter and logic block 112 comprise a digital error integrator.
• the output of first comparator 110 is a tri-state signal indicating whether the up/down counter should count up, count down or retain its current value.
• the output of first comparator 110 will allow the up/down counter to count either up or down; when the output of peak detector 104 is within the reference voltage window, the up/down counter will hold its value.
• the output of the up/down counter is a digital word (e.g. a binary number).
• this word is the digital equivalent of the analog output of error integrator 106 in the analog loop.
• the digital word is supplied to DAC 114 where it is converted to an analog voltage comparable to the output of analog error integrator 106.
• the second binary counter acts as a timer and is used to determine when the output of MUX 108 is to be switched from the analog to the digital output.
• This ripple counter also performs the operation of determining when to update the up/down counter output to DAC 114.
• the up/down counter output is updated at predetermined intervals. Controlling the update rate and low pass filtering the output of DAC 114 using LPF 116 reduces noise associated with digital loop operation.
• the output of the DAC 114 is supplied to the oscillator 102 through the LPF 116.
• the LPF 116 decreases the higher frequency noise generated by the DAC 114 during switching of the DAC 114 when the DAC 114 steps up or down to adjust the gain of the oscillator 102.
• the LPF 116 may be implemented by any number of circuits.
• the LPF 116 passes frequencies ranging from DC to a set value. In one embodiment, the corner frequency of a single-pole RC filter is about 100 kHz.
• the AGC loop 100 operates as shown by the example of Fig. 4.
• the signal from the oscillator 102 shown in the top graph as Xtall, and the regulated voltage to the oscillator 102, shown as the middle graph, are low.
• the power down signal shown in the bottom graph of Fig. 4 transitions to low (e.g. about 0.9ms).
• the peak detector 104 detects a low voltage provided from the oscillator 102 and the error integrator 106 provides a maximum voltage, which the MUX 108 passes to the oscillator 102.
• the voltage supplied to the oscillator 102 thus quickly increases to a maximum, taking about 0. lms as shown in one example.
• the oscillator 102 begins to oscillate, as shown at around 1.5ms. Once the amplitude of the oscillating signal from the oscillator 102 reaches a predetermined amount, the signals are used as clock signals for the digital circuitry in the AGC loop 100. This starts the ripple counter in the counter and digital logic block 112. The ripple counter, in turn, triggers the up/down counter to update the DAC 114.
• the DAC 114 provides an output that is compared to the output from the error integrator 106 by the second comparator 118.
• the result from the second comparator 118 is fed back to the digital logic in counter and logic block 112, whose result is supplied to the DAC 114.
• the DAC 114 input counts up or down and adjusts its output so that it eventually approaches or essentially equals that of the error integrator 106.
• the output of the DAC 114 thus settles and reaches that of the error integrator 106, so that when the AGC loop 100 switches from the analog AGC loop to the digital AGC loop, the oscillator 102 does not experience a large change in the driving signal.
• the oscillator 102 After a specified number of cycles of oscillation, the oscillator 102 has reached steady state.
• the ripple counter determines when the predetermined number of cycles have occurred, and then disconnects the output of the error integrator 106 from the oscillator 104 and connects the low pass filtered DAC 114 output using the MUX 108. This occurs in Fig. 4 between 1.7 ms and 1.8 ms.
• the first comparator 110 then compares the output of the peak detector 104 to the high and low reference voltages. If the output of the peak detector 114 drifts outside the reference voltage window, the first comparator 110 enables the up/down counter in counter and logic block 112 to count in the appropriate direction.
• the output of the up/down counter is converted to an analog control voltage by the DAC 114, and the analog voltage is low pass filtered by the LPF 116 to minimize noise.
• the filtered control voltage is then fed back to the oscillator 102 to control its amplitude.
• the AGC loop 100 is switched from an analog loop to a digital loop (i.e. steady state operation is deemed to have occurred) after a predetermined amount of time.
• the ripple counter in counter and logic block 112 is connected to the output from the oscillator 102 and is used as a timer. In this case, one output of the ripple counter is used to trigger the switch from analog to digital while another downstream output is used to trigger logic in counter and logic block 112 to check the amplitude of oscillation in steady state.
• a second oscillator that is already in steady state may be used to determine the time.
• This time may be set empirically, after measuring the response using a large number of oscillators and taking the worst case scenario.
• the empirical result may be stored in the logic or elsewhere for comparison purposes.
• the time also depends on the frequency of the crystal. For example, it may take lms for a crystal that operates at 20MHz, as shown in Fig. 4, or 5ms for a crystal that operates at 4MHz.
• the ripple counter may cause the logic block 112 to check the oscillation amplitude every 10 ms in steady state.
• the oscillation amplitude of the oscillator 102 may be monitored and used to switch between the analog and digital loops. As the oscillator 102 is starting up and before it reaches steady state (e.g. before switching to the digital loop) some overshoot and ringing may occur. The overshoot and ringing depends on the loop stability. The loop thus may be switched when the amplitude of oscillator 102 has stabilized and falls within a specific window for a specified period of time.
• FIG. 5 is a graph of the phase noise vs. oscillator output for the AGC loop shown in Fig. 1 when in digital mode. The graph shows the performance of digital loop, which is substantially better than the noise performance of the corresponding analog loop. As can be seen, at IkHz, 1OkHz, and 10OkHz offsets from the carrier frequency, the noise is -125dB, -15OdB, and -17IdB, respectively, below the carrier amplitude.
• a low noise reference oscillator with a minimized start-up time is provided.
• the start-up time is minimized by first initializing the amplitude of the oscillator with an analog AGC loop. After the amplitude of the oscillator has stabilized for a predetermined amount of time, the AGC loop is switched from analog control during the start up mode to digital control in the steady state mode to provide a lower noise control.
• a frequency source that has both a fast start-up time and low noise at steady state operation is provided. This frequency source additionally is able to compensate for both crystal-to-crystal variation and temperature variation for a single crystal.
• the structure or embodiments may also be used to provide a slower start time or higher noise in steady state operation.
• the hybrid AGC loop 100 can switch between the analog and digital AGC loops as desired.
• the analog AGC loop may be used in the steady state mode.
• any criteria desired may be used to switch between the analog and digital AGC loops.

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• Oscillators With Electromechanical Resonators (AREA)
• Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

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• 2005
  • 2005-10-28 US US11/261,978 patent/US7332979B2/en not_active Expired - Lifetime
• 2006
  • 2006-10-18 EP EP06826267A patent/EP1943736A1/en not_active Withdrawn
  • 2006-10-18 JP JP2008537794A patent/JP4851532B2/ja not_active Expired - Fee Related
  • 2006-10-18 WO PCT/US2006/040872 patent/WO2007070166A1/en not_active Ceased
  • 2006-10-18 CN CN200680040100.0A patent/CN101366180B/zh not_active Expired - Fee Related

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