WO2007043645A1 - 素子の製造方法 - Google Patents

素子の製造方法 Download PDF

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Publication number
WO2007043645A1
WO2007043645A1 PCT/JP2006/320450 JP2006320450W WO2007043645A1 WO 2007043645 A1 WO2007043645 A1 WO 2007043645A1 JP 2006320450 W JP2006320450 W JP 2006320450W WO 2007043645 A1 WO2007043645 A1 WO 2007043645A1
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WO
WIPO (PCT)
Prior art keywords
aluminum alloy
alloy film
film
etching
acid
Prior art date
Application number
PCT/JP2006/320450
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English (en)
French (fr)
Japanese (ja)
Inventor
Takashi Kubota
Yoshinori Matsuura
Original Assignee
Mitsui Mining & Smelting Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui Mining & Smelting Co., Ltd. filed Critical Mitsui Mining & Smelting Co., Ltd.
Publication of WO2007043645A1 publication Critical patent/WO2007043645A1/ja

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Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/13439Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to a method for manufacturing an element in a display device such as a liquid crystal display, and more particularly to a technique for manufacturing an element using an aluminum alloy film as a wiring circuit material.
  • liquid crystal displays have been used for display of various electronic devices, and the development of display devices constituting the liquid crystal display is proceeding remarkably.
  • a display device for this liquid crystal display for example, a thin film transistor (hereinafter abbreviated as “TFT”) is known.
  • TFT thin film transistor
  • A1 alloy aluminum (A1) alloy is used. Is used! /
  • the electrode constituting the wiring or electrode is a force formed by an aluminum alloy film.
  • An electrode made of this aluminum alloy film (hereinafter referred to as an aluminum alloy layer)
  • a so-called contact barrier layer (also called a cap layer) made of Mo, Cr or the like is formed at the bonding interface between a transparent electrode layer such as ITO or IZO and an aluminum alloy layer.
  • Non-Patent Document 1 edited by Tatsuo Uchida, “Next Generation Liquid Crystal Display Technology”, first edition, Industrial Research Co., Ltd., November 1, 1994, p. 36- 38
  • Patent Document 1 Japanese Patent Application Laid-Open No. 2004-214606
  • Patent Document 2 Japanese Unexamined Patent Publication No. 2003-89864
  • the aluminum alloy materials disclosed in these prior arts are basically composed mainly of aluminum, chemicals used in the manufacturing process of display devices, such as developers, resists, etc. Direct contact with the stripping solution, etc. tends to cause pinhole erosion and contamination. If defects such as pinholes occur in the aluminum alloy layer, there is a concern that the electrical characteristics of the element may be affected, for example, the bonding characteristics may be reduced when the aluminum alloy layer and the transparent electrode layer are directly bonded. . In other words, with regard to the method of manufacturing the element of the display device using the aluminum alloy film, the detailed examination has been made on more effective measures.
  • the present invention has been made in the background as described above, and relates to a method for manufacturing an element including a step of etching an aluminum alloy film to form a wiring circuit, and damages the aluminum alloy film.
  • the objective is to propose a manufacturing technology that can suppress this as much as possible and realize a highly reliable device.
  • an element manufacturing method comprising: forming an aluminum alloy film on a substrate; and etching the aluminum alloy film to form a wiring circuit. After forming the film, the surface of the aluminum alloy film was oxidized.
  • the aluminum alloy film formed on the substrate is generally processed into a wiring circuit by photolithography after the film is formed. Resist application, resist image liquid, There is an opportunity for the chemical solution such as a resist stripping solution to come into contact with the aluminum alloy film. Therefore, the surface of the aluminum alloy film is highly likely to cause erosion and surface contamination such as pinholes due to contact with various chemicals. Therefore, in the present invention, after the aluminum alloy film is formed, the surface of the aluminum alloy film is positively treated with an acid so as to form a surface acid film as a protective film. Surface acid of this aluminum alloy film
  • the conversion coating is mainly an aluminum oxide coating. Since this aluminum oxide coating has excellent corrosion resistance, erosion and contamination of the aluminum alloy film can be suppressed even when in contact with various chemical solutions.
  • an oxidation treatment is performed after an aluminum alloy film is formed on a substrate.
  • other film formation treatments, semiconductor layers, insulating layers are formed on the substrate.
  • a layer or the like may be formed.
  • an acid treatment is performed to form a surface acid film on the aluminum alloy film.
  • a known method such as so-called annealing treatment or oxygen gas ashing treatment can be employed.
  • the oxidation treatment on the surface of the aluminum alloy film is calculated when the entire thickness of the aluminum alloy film having a natural oxide film with a predetermined thickness is etched with an etching solution for aluminum alloy. It is desirable to form an acid film so that an etching rate of 80% or more can be secured with respect to the etching rate in the thickness direction.
  • the upper limit of the etching rate in the aluminum alloy film that has been subjected to the prescribed acid / oxidation treatment is less than 100% of the etching rate of the natural acid / oil film, but it is substantially natural oxidation.
  • Oxidation on the surface is more advanced than the coating, and it is necessary to carry out an acidification treatment so that the surface of the aluminum alloy film is not eroded or contaminated by contact with the chemical solution.
  • the oxidation treatment is 95% or less of the etching rate of the natural oxide film, there is a tendency that the surface of the aluminum alloy film is not eroded or contaminated by the chemical solution. I have confirmed that.
  • the aluminum oxide film formed as the surface acid film has excellent corrosion resistance, but at the same time has electrical insulation. Therefore, for example, when direct bonding is performed with a transparent electrode layer such as ITO, if an aluminum oxide film is present at the bonding interface, contact resistance is increased, and a practical device cannot be manufactured. Therefore, the present inventors examined the structure of the surface acid film formed on the surface of the aluminum alloy film. As a result, it has been found that an aluminum alloy film having a surface oxide film formed by oxidation treatment can protect the aluminum-alloy film without greatly affecting the electrical characteristics of the device if the etching rate is predetermined. It was.
  • a naturally formed aluminum oxide film is generally formed by forced acid treatment such as force annealing, which is generally known to have a thickness of about 5 to: LOnm. Further, it is known that the thickness of the surface oxide film does not change greatly even when compared with the thickness of the natural oxide film, and the structure of the aluminum oxide film itself becomes dense. In other words, it is not easy to specify the structure itself, such as the density of the surface oxide film! Therefore, the inventors focused on the etching rate in the thickness direction of the aluminum alloy film. When an aluminum alloy film is etched with an aluminum alloy etching solution, the rate-limiting process when the etching proceeds is when the surface oxide film of the aluminum alloy film is etched.
  • the change in the etching rate in the thickness direction of the aluminum alloy film having the same composition corresponds to the difference in the structure of the surface oxide film itself including the difference in thickness. From this, the oxidation treatment of the aluminum alloy film in the present invention was specified based on the etching rate in the thickness direction when an aluminum alloy film having a natural oxide film and having a predetermined thickness was etched.
  • an aluminum alloy film having a thickness of 1000 A or more is formed on the substrate and left in the air without any treatment to form a natural acid film on the surface of the aluminum alloy film.
  • the etching rate in the direction (here, referred to as the reference etching rate) is calculated.
  • an aluminum alloy film having the same thickness is formed, a surface oxide film is formed by oxidation treatment under a predetermined condition, and the entire thickness of the aluminum alloy film is etched with the same etching solution to obtain an etching rate in the thickness direction.
  • the etching rate force when the acid treatment under the predetermined conditions is performed. If the etching rate is 80% or more of the reference etching rate obtained in advance, the aluminum alloy can be used without greatly affecting the electrical characteristics of the device.
  • a surface acid film capable of protecting the film can be formed.
  • the element manufacturing method according to the present invention described above includes an aluminum alloy containing at least one element selected from nickel, cobalt, iron, carbon, and boron, with the balance being aluminum.
  • a membrane is desirable. This is particularly effective when the aluminum alloy film is an Al—Ni alloy.
  • Al-Ni alloy containing nickel in aluminum has excellent bonding characteristics in direct bonding with the transparent electrode layer.
  • direct bonding with low contact resistance is possible. It is possible to manufacture an element having a good bonding state. If an Al—Ni—B alloy is used among these A1—Ni-based alloys, it is possible to manufacture an element having excellent bonding characteristics even in direct bonding with a semiconductor layer.
  • the oxidation treatment of the present invention described above is preferably performed by so-called annealing treatment or ashing treatment with oxygen gas.
  • annealing it is desirable that the annealing atmosphere be 20% to 100% in terms of oxygen partial pressure.
  • the annealing temperature is a treatment time of 30 minutes to less than 24 hours at an annealing temperature of 150 ° C to less than 500 ° C, with a force S that varies with the acidity of the annealing atmosphere.
  • the oxygen concentration in the ashing atmosphere is 80 to 100%, the processing time is less than 10 seconds to 2 minutes, and the input power during ashing is 50 to 300W. If these oxidation treatment condition ranges are not met, an appropriate oxide film will not be formed, or the oxidation process will proceed excessively and the contact resistance value at the direct junction will tend to increase.
  • FIG. 1 is a schematic diagram of a resistance value measuring element by a four-terminal method.
  • FIG.2 SEM observation photograph of 200 ° C annealing treated aluminum alloy film surface.
  • FIG. 3 SEM observation photograph of the surface of an aluminum alloy film treated with oxygen gas ashing for 1 minute.
  • FIG. 4 SEM observation photograph of untreated aluminum alloy film surface.
  • FIG. 5 Enlarged SEM observation photograph of Fig. 4.
  • the aluminum alloy film is formed on a glass substrate using an A1 alloy target having the above composition, sputtering conditions, input power 3. OWatt / cm 2 , argon gas flow rate 100 ccm, An aluminum alloy film having a thickness of 2000 A was formed using a magnetron sputtering apparatus (manufactured by Tokine Earth Co., Ltd .: multi-chamber type sputtering apparatus MSL464) at a Lugon pressure of 0.5 Pa.
  • the aluminum alloy film was then subjected to an oxidation treatment under various conditions.
  • oxidation conditions annealing at 100 ° C to 300 ° C in air (30 minutes) and oxygen gas ashing (oxygen gas flow rate 50ccm, pressure 10Pa, input power 100Watt, room temperature: treatment time 1 to 3 minutes) was formed.
  • Each oxidized sample was covered with a resist (OFPR800: Tokyo Ohka Kogyo Co., Ltd.), and a pattern film for forming a 20 m wide circuit was placed and exposed to light. Liquid temperature 23.
  • the film was developed with an alkali developer containing C tetramethylammonium and id-oxide (hereinafter abbreviated as TMAH developer). After development, phosphoric acid mixed acid etching solution (manufactured by Kanto Chemical Co., Ltd.
  • DMSO DMSO
  • DMSO DMSO
  • the etching rate was measured by etching the entire circuit with the phosphoric acid mixed acid etching solution.
  • Table 1 shows the results of the phosphoric acid mixed acid etching solution. After forming the aluminum alloy film, the same etching process was performed on the sample with the natural oxide film (untreated) that was left in the atmosphere for about 60 minutes at room temperature, and the etching rate was measured. did.
  • an aluminum alloy film having a thickness of 2000A was formed on a glass substrate under the same sputtering conditions as described above using an A1 alloy target having the above composition. Then, after each of the oxidation treatments described above, a 20 m wide circuit made of an aluminum alloy film was formed under the above-described circuit formation conditions.
  • the substrate on which the 20 ⁇ m width circuit was formed was subjected to pure water cleaning and drying treatment, and an SiNx insulating layer (thickness 4200 A) was formed on the surface thereof.
  • This insulating layer was formed using a sputtering apparatus under sputtering conditions of input power RF3. OWatt / cm 2 , argon gas flow rate 90 ccm, nitrogen gas flow rate 10 ccm, pressure 0.5 Pa, substrate temperature 300 ° C.
  • a positive resist (Tokyo Oka Kogyo Co., Ltd .: TFR-970) was covered on the surface of the insulating layer, and a 10 m x 10 m square contact hole opening pattern film was placed for exposure treatment. And developed with TMAH developer. CF dry etching gas
  • Contact hole formation condition is CF gas field
  • the resist was stripped with the following resist stripping solution DMSO.
  • Each evaluation sample subjected to the resist stripping treatment was subjected to a drying treatment after washing the remaining stripping solution with pure water.
  • an ITO target (composition of InO-10wt% SnO) was used to transparent ITO in and around the contact hole.
  • the transparent electrode layer is formed by sputtering (substrate temperature 70 ° C, input power 1.8 WattZcm 2 , argon gas flow rate 80ccm, oxygen gas flow rate 0.7ccm, pressure 0.37Pa), and the thickness of the transparent electrode layer 1000 A An ITO film was formed.
  • a resist (OFPR800: manufactured by Tokyo Ohka Kogyo Co., Ltd.) is coated on the surface of the ITO film. Then, pattern film is placed and exposed to light, developed with TMAH image solution with a density of 2.38% and a liquid temperature of 23 ° C, and oxalic acid mixed acid etchant (manufactured by Kanto Chemical Co., Ltd.) A 20 m wide circuit was formed by ITO05N). After forming the ITO film circuit, the resist was removed with a stripping solution (DMSO 100 wt%).
  • the contact resistance value is measured for an evaluation sample in which a contact hole is formed by the procedure as described above and a circuit made of an aluminum-alloy film and the transparent electrode layer are directly bonded via the contact hole. did.
  • Table 2 shows the measurement results.
  • This contact resistance measurement method is based on the four-terminal method as shown in Fig. 1.After the element, which is an evaluation sample, is annealed in air at 250 ° C for 30 minutes, the resistance value of each evaluation sample is measured. It was.
  • the four-terminal method shown in FIG. 1 measures the resistance by applying a continuous current (3 mA) from the terminal portion of the evaluation sample after heat treatment.
  • FIGS. 2 to 5 show SEM observation photographs of the aluminum alloy film surface.
  • Fig. 2 shows 200 ° C annealing
  • Fig. 3 Force S 1 minute oxygen gas ashing
  • Fig. 4 shows no treatment (natural oxidation)!
  • FIG. 5 shows an enlarged SEM observation photograph (magnification 200,000 times) of FIG. It was confirmed that many small pinholes were formed on the surface of the aluminum alloy film. On the other hand, in the case of the oxidation treatment shown in FIGS. 2 and 3, erosion such as pinholes was not observed on the surface of the aluminum-alloy film. From the above, in the case of untreated (natural oxidation), although the contact resistance is low, the existence of pinholes is considered to be not reliable, and in contrast to the oxidation of the present invention, In the case of processing, it has been found that a practical junction resistance value can be satisfied, and a highly reliable direct bonding structure can be realized.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Liquid Crystal (AREA)
  • Manufacturing & Machinery (AREA)
  • Weting (AREA)
PCT/JP2006/320450 2005-10-14 2006-10-13 素子の製造方法 WO2007043645A1 (ja)

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Application Number Priority Date Filing Date Title
JP2005299666A JP2007109916A (ja) 2005-10-14 2005-10-14 素子の製造方法
JP2005-299666 2005-10-14

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JP (1) JP2007109916A (ko)
KR (1) KR20080063339A (ko)
CN (1) CN101283443A (ko)
TW (1) TWI371082B (ko)
WO (1) WO2007043645A1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011091352A (ja) * 2009-09-28 2011-05-06 Kobe Steel Ltd 薄膜トランジスタ基板およびその製造方法並びに表示装置
CN102034832A (zh) * 2009-09-28 2011-04-27 株式会社神户制钢所 薄膜晶体管基板及其制造方法以及显示装置
CN110993694B (zh) * 2019-10-22 2023-08-25 清华大学 自氧化方式制备亚10nm沟道的二维薄膜场效应晶体管

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102151A (ja) * 1991-10-07 1993-04-23 Fujitsu Ltd 半導体装置の製造方法
JPH0618912A (ja) * 1992-07-03 1994-01-28 Fujitsu Ltd 液晶表示装置及びその製造方法
JPH06148658A (ja) * 1992-11-02 1994-05-27 Sharp Corp 配線構造
JPH07169966A (ja) * 1993-12-16 1995-07-04 Sharp Corp 電子部品及びその製造方法
JPH11284195A (ja) * 1998-03-31 1999-10-15 Mitsubishi Electric Corp 薄膜トランジスタおよび該薄膜トランジスタを用いた液晶表示装置
JP2001023990A (ja) * 1999-07-07 2001-01-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003273109A (ja) * 2002-03-14 2003-09-26 Advanced Display Inc Al配線用薄膜及びその製造方法並びにこれを用いた液晶表示装置
JP2004214606A (ja) * 2002-12-19 2004-07-29 Kobe Steel Ltd 表示デバイスおよびその製法、ならびにスパッタリングターゲット
JP2005062802A (ja) * 2003-07-28 2005-03-10 Advanced Display Inc 薄膜トランジスタアレイ基板の製法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05102151A (ja) * 1991-10-07 1993-04-23 Fujitsu Ltd 半導体装置の製造方法
JPH0618912A (ja) * 1992-07-03 1994-01-28 Fujitsu Ltd 液晶表示装置及びその製造方法
JPH06148658A (ja) * 1992-11-02 1994-05-27 Sharp Corp 配線構造
JPH07169966A (ja) * 1993-12-16 1995-07-04 Sharp Corp 電子部品及びその製造方法
JPH11284195A (ja) * 1998-03-31 1999-10-15 Mitsubishi Electric Corp 薄膜トランジスタおよび該薄膜トランジスタを用いた液晶表示装置
JP2001023990A (ja) * 1999-07-07 2001-01-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2003273109A (ja) * 2002-03-14 2003-09-26 Advanced Display Inc Al配線用薄膜及びその製造方法並びにこれを用いた液晶表示装置
JP2004214606A (ja) * 2002-12-19 2004-07-29 Kobe Steel Ltd 表示デバイスおよびその製法、ならびにスパッタリングターゲット
JP2005062802A (ja) * 2003-07-28 2005-03-10 Advanced Display Inc 薄膜トランジスタアレイ基板の製法

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JP2007109916A (ja) 2007-04-26
CN101283443A (zh) 2008-10-08
TWI371082B (en) 2012-08-21
TW200725805A (en) 2007-07-01
KR20080063339A (ko) 2008-07-03

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