TWI326309B - A1-ni-b alloy wiring material and device structure using the same - Google Patents

Abstract

The present invention provides an Al alloy wiring material, which is capable of being directly bonded to transparent electrode layers such as ITO, IZO and the like, further to semiconductor layers such as n+-Si, in a display device provided with a thin-film transistor or a transparent electrode layer. In an Al-Ni-B alloy wiring material according to the present invention, when a nickel content is assumed X at% as an atomic percent of nickel and a boron content is assumed Y at% as an atomic percent of boron, formulae 0.5 ≤ X ≤ 10.0, 0.05 ≤ Y ≤ 11.0, Y+0.25X ≥ 1.0, and Y+1.15X ≤ 11.5 are all satisfied in terms of scope, and the balance being aluminum.

Description

1326309 IX. Description of the Invention: The present invention relates to an A1 alloy wiring material used for components of a display device such as a liquid crystal display, and more particularly to a display device suitable for a thin film transistor and a transparent electrode. A1 — Ni—B alloy wiring material and component structure using the Al—Ni—B alloy wiring material. [Prior Art] In recent years, in a display device such as a thin-type television such as a liquid crystal display, aluminum (hereinafter sometimes referred to as A1)-based alloy wiring material has been widely used as a constituent material. The reason for this is that the A1 alloy wiring material has a low specific resistance value and has a characteristic that wiring processing is easy. - For example, in the case of an active matrix type liquid crystal display, it is used as a switching element; thin film transistor (hereinafter referred to as TFT), .ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide: oxidation) A transparent electrode such as indium zinc (hereinafter sometimes referred to as a transparent electrode layer) and a wiring circuit formed of an Al-based alloy wiring material (hereinafter referred to as a wiring circuit layer when *) constitute an element. In such an element structure, a portion where a wiring circuit formed of an Al-based alloy wiring material is bonded to a transparent electrode and a portion where n+-Si (phosphorus-doped semiconductor layer) is bonded to the TFT is present. In the Al-based alloy wiring material used in the prior art, in order to constitute the above-mentioned element, the influence of the aluminum oxide formed on the Al-based alloy wiring material is considered, and molybdenum is formed between the wiring circuit and the transparent electrode. A high melting point metal material such as Mo) or titanium (Ti) is used as a so-called cap layer. 5 318169 1326309 : In the junction of the semiconductor layer such as n-Si and the wiring circuit, in order to prevent the mutual diffusion of A1 and Si due to the thermal process in the process, between the semiconductor layer and the wiring circuit' A high melting point metal material such as molybdenum (Mo) or titanium (Ti) is provided in the same manner as the above coating layer. The above-described element structure will be specifically described below with reference to Fig. 1 . Fig. 1 is a schematic cross-sectional view showing an a-Si (amorphous germanium) type TFT of a liquid crystal display. In the TFT structure, 'on the glass substrate 1' is formed with an electrode wiring electric circuit layer 2 composed of an A1 alloy wiring material constituting the gate electrode portion G, and a composition composed of Mo or Mo-W or the like. In addition, the gate electrode portion G is provided with a gate insulating film 4 of siNx as the protective film. Further, on the gate insulating film 4, an a-Si semi-conductor layer 5, a channel protective film layer 6, an n+-Si semiconductor layer 7, a cap layer 3, an electrode wiring circuit layer 2, and a cap layer 3 are sequentially deposited. By forming an appropriate pattern, the drain electrode portion D and the source electrode portion s are provided. On the electrodeless electrode portion d and the source electrode portion S, a resin or a SiNx insulating film 4' for planarizing the surface of the device is coated. Further, on the side of the source electrode portion s, a contact hole CH is formed in the insulating film 4?, and a transparent electrode layer 7 of ITO or IZO is formed in this portion. When the iridium-based alloy wiring material is used for the electrode wiring circuit layer 2, it is formed between the η+-Si semiconductor layer 7 and the electrode wiring layer 2, and the transparent electrode layer 7 in the contact hole CH, and the electrode. The wiring circuit layer 2 is sandwiched between the layers 3 having a structure. In the element structure shown in Fig. 1, since a cover layer such as M〇 is formed, the cost of the material, the manufacturing equipment, and the like cannot be avoided, and the process is complicated. Therefore, the applicant's compound has been proposed to omit the above-mentioned 318169 6 1326309. A technique of covering a cover layer in a structure (refer to Patent Document 1;). In Patent Document 1, a wiring material of an A1-c_Ni alloy and an A1-C-Ni-Si alloy which can be directly bonded to IT〇 is disclosed. In the A1 series alloy wiring material of the above-mentioned Patent Document 1, it is possible to use ITO or IZ 〇 专利 专利 _ _ _ ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ITO ; ITO ITO ITO ITO ITO ITO ITO ITO ITO When the transparent electrode layer is directly bonded, when it is directly bonded to a semiconductor layer such as n+_si, it does not have a characteristic that can be sufficiently satisfied. In the case where the wiring circuit layer composed of the A1 alloy wiring material is directly bonded to the semiconductor layer, a diffusion phenomenon such as & More specifically, when the coating layer of the element structure shown in Fig. 1 is omitted, a metal wiring material which satisfies the following characteristics is required. The electrode wiring layer 2 of the gate electrode portion G of the device structure of the first embodiment is not shown, but it is necessary to directly bond the transparent wiring layer such as IT0 to the drawing wiring portion. Busy heat resistance. The reason for this is that when the gate insulating film formed over the gate electrode portion G is formed, since a thermal history of high temperature is applied, it is necessary to have an electrode wiring circuit layer even in a temperature higher than the temperature of Cong. It does not have the heat resistance of defects such as i (hlll〇ck). Further, in the electrode wiring layer 2 of the element structure D and the source electrode portion s of Fig. 1, a transparent electrode layer such as ITO is directly bonded and directly bonded to the n + - body layer. Here, in the direct bonding with a semiconductor layer such as n+-si, 318169 7 1326309, even if the above thermal history is applied, it is necessary to prevent the diffusion phenomenon of A1 and Si. Further, in the electrode wiring circuit layer 2 of the electrodeless electrode portion D and the source electrode portion s -, it is required to have heat resistance which does not cause defects such as protrusions even if a heat history of 2 thieves is applied. Further, in the interpole electrode portion G, the electrodeless electrode portion D, the source electrode portion s, and the A1 alloy wiring material in which other wiring portions are formed, of course, the specific resistance is also required to be low, that is, full; 1 is more preferably a characteristic of the ratio - resistance value of (10) (10) or less. That is to say, at present, it is deeply desired that the alloy wiring material of the ten-sex is desired. In addition, in the conventional A-based alloy wiring material, it is presumed that a precipitate such as an intermetallic compound exists in the wiring circuit, and the transparent electrode layer (pixel electrode) can be formed by the presence of the precipitate. Direct bonding (see, for example, Patent Document 2). However, in the dispersion state of the precipitates formed in the wiring circuit formed of the A1 alloy wiring material, the direct bond is affected, and the inventors of the present application do not explicitly study the range known to the inventors of the present application. . _ : In order to achieve a more desirable direct bonding, the precipitation of the A1 alloy wiring material is required to further study this phenomenon. In the conventional A1 alloy wiring material, the surface of the A1 alloy film formed by the machine bond is formed in the conventional A1 alloy wiring material. It is known to be in a very rough human form. When the transparent electrode layer, the semiconductor layer, or the like is directly laminated on the μ gold film in such a rough surface state, there is a fear that the laminate material cannot be sufficiently covered well, that is, The concave portion of the surface unevenness is completely covered from the laminated material. Therefore, regarding 318169 1326309 - the technique of forming the surface state of the A1 alloy film for forming a wiring circuit to be smooth is required to be further explored. The present invention has been developed in view of the above circumstances, and aims to be used for a display device having a thin film transistor and a transparent electrode layer, and can be directly bonded to an ITO or a transparent electrode layer such as Z0. n+—A1 alloy wiring material directly bonded to a semiconductor layer such as Si. Further, the wiring circuit layer formed of the A1-based alloy wiring material is an element having a display device ♦ having a structure that can be directly bonded to the transparent electrode layer or the semiconductor layer, and proposes that it does not occur in direct bonding. The increase in contact resistance value and the component configuration of the display device with poor bonding. (Means for Solving the Problem) • After inventing the A1_Ni alloy, the inventors of the 纟 application found that the above problem could be solved by the inclusion of a predetermined amount of exclusive (8) in the A1-Ni alloy. Thus, the present invention has been completed. The invention relates to a kind of Al-Ni-B alloy wiring material, which is characterized in that: nickel and boron are contained in Shaozhong, and the characteristic is: the nickel content is set to the atomic percentage of nickel X, and the content is set to boron. When the atomic percentage is increased by %, it is located at full 〇*5^X^i〇q......(1) 〇.〇5^Υ^ιι.〇...(2) Y+0.25X ^1.00 ......(3) Υ+1·15Χ^11.5......(4) Within the range of the domain, and the remainder is the same. Wherein, the 配线 1 alloy wiring material of the present invention is within the range of the effect achieved by the invention 318169 9 1326309 described below, for example, in a material process, a wiring circuit forming process, or a 70 process, etc., Used to hinder the incorporation of gas components and other unavoidable impurities that may be mixed. Nickel has an effect of forming an intermetallic compound with aluminum by heat treatment to achieve good bonding characteristics when directly bonded to a transparent electrode layer. If the nickel content is too large, the specific resistance of the wiring circuit itself is increased and it is less practical. In addition, when the nickel content is too small, the amount of the intermetallic compound with aluminum is reduced, and it is impossible to directly bond to the transparent electrode layer, and it has a luke heat (the plastic deformation of the A1 alloy wiring material due to heat) Inhibition) also tends to decrease. For these reasons, the nickel content must satisfy the above formula (1). Specifically, if the nickel content exceeds l〇.〇at%, the ratio of the wiring material: the resistance value becomes excessively large, and it is easy to form a concave defect called a concave depression (dimP) in the surface of the wiring material. However, there is a tendency that heat resistance cannot be ensured. Further, when it is less than 0.5 at%, it is easy to form a projection called a hillock on the surface of the wiring material, and there is a tendency that heat resistance cannot be ensured. The term "dent" refers to a small concave defect formed on the surface of the material due to the stress strain generated when the A1 alloy wiring material is heat-treated. If this recess occurs, the joint characteristics are adversely affected. The joint ketone is reduced. On the other hand, the so-called hillocks, in contrast to the depressions, refer to the protrusions formed on the surface of the material due to the stress strain generated when the A1 alloy wiring material is heat-treated, and if this hillock is generated, The joint characteristics have an adverse effect, and the joint reliability is lowered. This depression and hillock are made of plastic deformation of the A1 alloy wiring material due to heat. 318169 10 1326309 - See common, commonly known as stress migration phenomenon, by the level of generation of these defects 'To determine the heat resistance of the A1 alloy wiring material. Further, when nickel and boron are contained in aluminum as described in the present invention, it is effective in preventing mutual diffusion of A1 and Si in the joint interface when directly bonded to a semiconductor layer such as n Sl. In addition, the deletion is the same as the recording, and has the effect of heat resistance. When the boron content exceeds 11 〇〇 at%, the specific resistance of the wiring electric circuit itself is increased, and it becomes less practical. Further, if the boron content is less than 0.05 at%, the ability to prevent the mutual diffusion of A1 & ^ is lowered, and the semiconductor layer cannot be directly bonded. Specifically, the semiconductor layer is

The Al—Ni—B alloy wiring material is bonded directly and at a predetermined temperature. When heat treatment, mutual diffusion of A1 and Si is likely to occur at the joint portion. In addition to this, there is also a tendency to easily form depressions. Therefore, the boron content must satisfy the above formula (2). Further, the inventors of the present invention found that in the thermal process at a temperature exceeding 240 C when directly bonded to the semiconductor layer, in order to surely prevent interdiffusion of Α1 & Si at the bonding interface, it is necessary to satisfy the above-mentioned (3) Formula. Further, in order to surely maintain the specific resistance of the A1_Ni-B alloy wiring material itself at 10 〇μΩ εηι or less, the above formula (4) must be satisfied. In addition, when the nickel content is 4.0 at% or more and the boron content is 〇% or less in the range satisfying the above formula (1) to the formula (4), the A1_Ni_B alloy wiring which suppresses the occurrence of the above-described depression is suppressed. The material can thus improve the bonding reliability when directly bonded to the semiconductor layer and the transparent electrode layer. Further, 318169 11 1326309, specifically, when the heat treatment is performed for 3 minutes at 35 (TC), the generation rate of the depression generated on the surface of the :Ni-B alloy wiring material can be suppressed to 1.6% or less, which is preferable. As described above, the so-called recess refers to a small concave shape formed on the surface of the wiring material when heat-treating the Al—Ni—B alloy wiring material. The inventor of the present invention is in the A1—Ni—B alloy wiring material. After the heat treatment of the 预:, the surface of the material was observed, and the resulting sag turtle (O.Spni to 〇.5μιη) β was investigated in this sag investigation, and all the depressions generated in the observation field were obtained. The area ratio of the area in which the depression of the observation field is occupied is the rate of generation of the depression. When the heat resistance of the wiring material is investigated, it is found that the range of the above formula (1) to the formula (4) is satisfied. When the content is 4.0 at% or more and the boron content is 〇8 〇 at% or less, the heat generation rate can be suppressed to 16-% or less even when heat treatment is performed for 30 minutes under 35 。 '. Try not to create depressions, Therefore, if the generation rate of the recess is low, even through the thermal process of the component process of the display device, the bonding interface directly bonded to the semiconductive layer and the transparent electrode layer is less likely to cause bonding defects and the like, and the bonding reliability can be improved. In addition, if the generation rate of the depression is suppressed to 16% or less, for example, the ON-OFF (ΟΝ/OFF ratio) of the TFT having the structure directly bonded to the semiconductor layer can be stabilized, and the connection can be improved reliably. The A1_Ni-B alloy wiring material of the present invention is suitable for direct bonding with a semiconductor layer and a transparent electrode layer, but does not hinder the formation of a metal material such as M〇, which is disposed on the side of the semiconductor layer, for example. In addition to the above-mentioned 12 318 169 1326309 for the purpose of directly bonding the semiconductor layer and the transparent electrode layer, the AI-Ni-B alloy wiring material of the present invention, a so-called reflective film, can also be applied. In addition, the inventors of the present invention found that within the range satisfying the above formulas to the formula, if the nickel content is 4.0 at% to 6 〇 at%, and boron The content of 〇.20at% to 0.80at%' can be used as an AI-Ni-B alloy wiring material which is particularly suitable for direct bonding with a semiconductor layer. • 'The wiring circuit layer composed of the A1 alloy wiring material and the semiconductor reed directly When joining, it is known that the diffusion phenomenon is caused by the joint interface. According to the research by the inventors of the present invention, the mold recognizes the influence of the mutual diffusion, and the joint interface at the time of direct bonding will In the case where the A1 -based alloy wiring material is directly bonded to the semiconductor-layer and subjected to a predetermined heat treatment, the A1 -based alloy wiring material is peeled off and the surface of the semiconductor layer is observed. The surface of the semiconductor layer - the altered portion of the observed black dot, or the state of discoloration and roughness of the surface of the semiconductor layer (in the present specification, the surface of the semiconductor layer is referred to as a metamorphic layer) The higher the heat treatment temperature, the more likely it is to be produced, and only the upper σ is used, and it is preferably 2 Å.不会 The above heat treatment (3 〇 minutes) does not occur. In addition, if the thermal history applied by the CVD (Chemical Vapor Deposition) is formed, it is preferable that the metamorphic layer does not occur in the high temperature range of 24 〇r to 300 ° c. In addition, in order to allow the application range of the manufacturing conditions imposed by the heat history of the component to have a large allowable dry circumference, it is preferable to suppress the generation of the deteriorated layer of 33 Å or more. Therefore, it is found that the composition range of the deformed shell layer is not found, and it is found that the nickel content is 4 times % to 318169 13 1326309 «* 6. When 硼at%' and the boron content is 〇2〇%% to 〇8〇%, the tendency of the altered layer can be suppressed even when the heat treatment is performed for 30 minutes. Further, in this composition range t, the I line circuit itself has a ❾匕 resistance value of 5. ΟμΩοπι or less. That is, if it is in this composition range, as described above, the generation of the depression can be suppressed as much as possible, and the specific resistance value can be lowered, so that it is practically applicable to the A1.B alloy for directly bonding to the semiconductor layer. Wiring material. In addition, the inventors of the present invention investigated the surface state change of the semiconductor layer, and investigated the surface roughness Rz of the semiconductor layer exposed by peeling off the alloy wiring material after direct bonding and heat treatment (ten point average) Roughness, JIS B0601: 1994), comparison with the surface roughness rz of the semiconductor layer before direct bonding. In the A1-Ni_B alloy wiring material of the present invention, it is found that the nickel content is 4 〇 at % in the range satisfying the above formulas (1) to (4). When the composition of the semiconductor layer before the direct bonding is set to 6.0at% and the boron content is 〇2〇at% to 〇8〇at%, direct bonding and heat treatment can be performed. The surface roughness ' of the semiconductor layer exposed later becomes a change amount of 1.5 times or less. - Whether the amount of change in the surface roughness of the semiconductor layer is directly related to the interdiffusion of A1 and Si, and it has not been clearly understood so far, but it can be confirmed that the higher the heat treatment temperature, the larger the amount of change . Further, variations in the surface state of the semiconductor layer are expected to affect the switching characteristics of the TFT. That is, it can be presumed to be related to the change of the on-off ratio (ΟΝ/OFF ratio) of the TFT. Therefore, it is directly bonded to the semiconductor layer and enters 14 318169 1326309 « , and after heat treatment, the surface of the semiconductor layer is not made. A large change in state can also be predicted to maintain good switching characteristics of the transistor. Therefore, when the surface roughness of the semiconductor layer before the direct bonding is set to 】, the surface roughness Rz of the semiconductor layer exposed after the A1 alloy wiring material is peeled off after direct bonding and heat treatment is performed, and the semiconductor is directly bonded. The amount of change in the surface roughness of the layer of L5 or less is sufficient to ensure the connection reliability of the TFT switching characteristics and the like. In the present invention, regarding the change in the surface state of the semiconductor layer which is bonded to the bonding, when the surface state is defined, the surface roughness Rz is used, but the surface property parameters described in JIS Na〇1 or the like may be used. For example, the surface roughness Ra (arithmetic mean coarse sugar) and other parameters. Further, the element structure of a display device having a structure in which an A1-based alloy wiring material has a structure in which a transparent electrode layer or a semiconductor layer is directly bonded is used, and the inventors of the present invention have an increase in contact resistance value and a poor connection when directly bonding. As a main factor, the surface roughness of the A1 alloy film was investigated, and it was found that the surface roughness of the alloy film formed of the A1—Ni—B alloy wiring material was preferably 2 Å. The i A1 Ni B alloy wiring material constitutes the above-described wiring circuit directly bonded to the semiconductor layer and/or the transparent electrode layer. When the surface roughness Ra of the Al—Ni—B alloy film formed by the “—Ni—b alloy + wiring material of the present invention is less than 2.0 A, the bonding strength is lowered when directly bonded to the transparent electrode layer, and the bonding strength is lowered. On the other hand, if it exceeds 2 〇〇A, it is confirmed that the contact resistance value tends to increase remarkably. The surface roughness degree Ra refers to the surface roughness of the film forming moxibustion A1 Ni B alloy film. 318169 15 1326309 : The difference in the manufacturing method is that the Al—Ni—B alloy film after film formation may form a semiconductor layer in a staggered structure and a transparent electrode layer in an inverted staggered structure. The surface roughness Ra is measured by an atomic force microscope (AFM: Atomic Force Microscope), and the Ra is calculated according to JIS B0601-1982. The Al-Ni-B alloy wiring material of the present invention is formed... The Al—Ni—B alloy film preferably has a film thickness of 1000 A to 3000 A. - If the film thickness of the Al—Ni—B alloy is less than 1000 A, the effective resistance value when forming the wiring circuit is difficult to satisfy. Sexual level, if more than 3000 A Then, the coverage of the upper layer laminated on the Al-Ni-B alloy film is inconsistent, and it tends to be difficult to form a practical element structure. Further, according to the study by the inventors of the present invention, it has been found in the present invention: In the wiring circuit layer formed of the Al—Ni—B alloy wiring material, the precipitates in the wiring circuit layer are dispersed and precipitated when the components are formed, and segregation is not generated, and the dispersion can be uniformly dispersed. In the study of the human and the like, it has been confirmed that the compound deposited in the wiring circuit, that is, the so-called intermetallic compound, tends to segregate in the specific composition of the conventional A1 alloy wiring material. For example, in the above patent In the A1-Ni-Nd alloy wiring material including Nd, which is disclosed in Document 2, the precipitation in the wiring circuit layer tends to be segregated due to the heat treatment in forming the device (see Fig. 5). As described above, when segregation of precipitates occurs in the wiring circuit layer, there is a difference in bonding position with the wiring circuit layer, and bonding that cannot be directly bonded is possible. The characteristics are good. That is, due to the 16 318169 1326309 in the wiring circuit layer, the precipitated intermetallic compound affects the bonding resistance of the direct bonding, and so on. Therefore, the transparent electrode layer and the semiconductor layer are directly bonded to the wiring circuit. When the portion of the layer is segregated and the portion directly bonded to the portion where no segregation occurs, the bonding property is different. Further, when the wiring formed by the Ai-based alloy wiring material is etched to form a wiring circuit, The portion where segregation occurs is different from the etching rate at which no segregation occurs, and thus a wiring circuit in which an appropriate shape cannot be formed may occur. On the other hand, in the wiring circuit layer formed by the Al—Ni—B alloy wiring material of the present invention, when the element is formed, the Ni compound is dispersed and precipitated, and the thickness of the wiring circuit layer and the thickness of the wiring circuit layer are formed. The existence ratio of the Ni compound on the line orthogonal to the direction is 25% to 45% in the thickness direction of the wiring circuit layer. That is, in the overall thickness of the wiring circuit layer, the compound does not show a tendency to segregate (see Fig. 6). Therefore, it is not necessary to specify a portion where the transparent electrode layer and the semiconductor layer are directly bonded as in the above-mentioned A1-Ni-Nd alloy wiring material, and it is also possible to form a wiring having an appropriate circuit shape by etching. Circuit. The Ni compound dispersed and deposited in the wiring circuit layer formed of the A1-Ni-B alloy wiring material of the present invention is mainly an intermetallic compound of the Al3Ni phase. As a result of investigation of the Ni compound by the present inventors, it was confirmed that when the surface of the wiring circuit was observed by a scanning electron microscope (SEM), there were a diameter of 20 nm to 160 nm, and the average particle diameter of each observation field was 8〇ηπι to 140nm. Further, the area ratio of the Ni compound to the observation field is 5 to 20%, and the density of the Ni compound is 1 ΙΟΟ /ΙΟΟμιη2 to 5000 / ΙΟΟμιη2. Further, when the cross section of the wiring circuit layer is observed by a transmission electron microscope 17 318169 1326309, -(TEM), the size of the Ni compound is 10% to 80% of the thickness of the wiring circuit layer of 200 nm, and the respective Ni compounds are The distance between each other is from 1 〇 nm to 150 nm. When the element of the display is manufactured by the above-described Al-Ni-B alloy wiring material of the present invention, it is preferable to use the nickel content as the atomic percentage Xat% of nickel, and the boron content as the atomic percentage of boron, Yat%. At the time, the position is within the range satisfying the above formulas (1) to (4), and the remainder is an aluminum-long plating target. In particular, in the range satisfying the above formulas (1) to (4), if the nickel content is 4.0 at% to 6.0 at%, and the boron content is 0.20 at% to 0,80 at% of the sputtering target, A wiring circuit that is very suitable for direct bonding with a semiconductor layer can be easily realized. When the sputtering target having such a composition is used, it is somewhat affected by the film formation conditions at the time of sputtering, but an Al-Ni-B alloy film having substantially the same composition as that of the sputtering composition can be easily formed. In the practical use of the Al-Ni-B alloy wiring material of the present invention, it is preferable to form a film by sputtering as described above, but other methods of φ may be employed. For example, a dry method such as a vapor deposition method or a spray homing method, or an alloy particle composed of the Al—Ni—B alloy of the present invention may be used as a wiring material, and aerosol deposition method may be employed. To form a wiring circuit, or to form a wiring circuit by an inkjet method. [Embodiment] Hereinafter, the best mode for carrying out the invention will be described. First Embodiment: In the present embodiment, Al-Ni-B alloy 18 318169 1326309 of each of the examples and comparative examples shown in the first table is formed by sputtering, and the characteristics of the crucible are evaluated. . The sputtering target system is used in aluminum. The metals of the respective compositions are mixed, melted and stirred in a vacuum, and then subjected to pounding in an inert gas atmosphere, and then the obtained ingot is subjected to calendering and molding, and Produced by planar processing of the surface to be sputtered. The evaluation of the characteristics of the film of each composition described in the first table is performed by directly bonding the semiconductor layer to Si diffusion heat resistance, film-specific resistance, film 35 (TC heat resistance, and direct bonding to the transparent electrode layer). At the time - ITO bondability and IZO bondability. The results are shown in Tables j and 2 above.

318169 19 1326309 [Table 1] Composition at% specific resistance y Ω cm Example 1 Al-3.0Ni-0.50B 4.13 Example 2 Al-3.0Ni-0.68B 4.18 Example 3 Al-4.7Ni-0.13B 4.16 Implementation Example 4 Al-4.7Ni-0.50B 4.35 Example 5 Al-4.7Ni-0.68B 4.41 Example 6 Al-4.7Ni-0.86B 4.62 Example 7 Al-4.7Ni-l.02B 4.64 Example 8 Al-4.7 Ni-l.46B 4.96 Example 9 Al-1.0 Ni-l.00B 3.94 Example 10 Al-1.0 Ni-5.00B 7.05 Example 11 Al-1.0 Ni-9.00B 9.86 Example 12 Al-5.0Ni -3.00B 6.63 Example 13 Al-5.0Ni-5.00B 8.19 Example 14 Al-8.0Ni-2.00B 8.05 Comparative Example 1 A1 3.01 Comparative Example 2 A1-0.3C 3.32 Comparative Example 3 Al-0.2Si 3.15 Comparative Example 4 Al-3.0Ni 3.70 Comparative Example 5 Al-4.8Ni 4.12 Comparative Example 6 Al-ll. ONi 10.60 Comparative Example 7 Al-0.3Ni-5.00B 3.58 Comparative Example 8 AM.0Ni-0.50B 3.55 Comparative Example 9 AM.0Ni- 12.00B 12.50 Comparative Example 10 Al-5.0Ni-0.01B 4.03 Comparative Example 11 Al-5.0Ni-6.00B 10.20 Comparative Example 12 Al-8.0Ni-3.00B 10.40 Comparative Example 13 Al-0.2Si-0.68B 3.48 Comparative Example 14 Al-3.0Ni-0.30C 3.76 Comparative Example 15 Al-3.0Ni-0.30C-0.2Si 3.84 20 318169 1326309 [Table 2]

Si diffusion heat resistance ° C 350 ° C heat resistance ιτο conjugate IZO bondability Example 1 240 〇〇〇 Example 2 240 〇〇〇 Example 3 300 〇〇〇 Example 4 330 〇〇〇 Example 5 330 〇 〇〇Example 6 330 〇〇〇Example 7 330 〇〇〇Example 8 330 〇〇δ Example 9 240 〇〇〇, Example 10 260 〇〇〇 Example 11 300 〇〇〇 Example 12 330 〇 〇〇 Example 13 330 〇〇〇 Example 14 330 〇〇〇 Comparative Example 1 170 XXX Comparative Example 2 170 XXX Comparative Example 3 180 XXX Comparative Example 4 200 X 〇〇 Comparative Example 5 250 X 〇〇 Comparative Example 6 300 X 〇〇 Comparative Example 7 230 XXX Comparative Example 8 200 X 〇〇 Comparative Example 9 330 〇〇〇 Comparative Example 10 190 X 〇〇 Comparative Example 11 330 〇〇〇 Comparative Example 12 330 〇〇〇 Comparative Example 13 180 XXX Comparative Example 14 200 X 〇〇Comparative Example 15 220 X 〇〇 The measurement conditions for evaluation of each characteristic are described below.

Si diffusion heat resistance: An evaluation sample for this characteristic is to form an n+-Si semiconductor layer (300 A) on a glass substrate by CVD, by sputtering 21 318169 !326309 : clock (magnetron plating device, power input) 3.0Watt/Cm2, argon gas flow rate lOOsccm, argon gas pressure 〇.5Pa), and each of the constituent films (2000 A) of the second layer was formed on the semiconductor layer. After 150 to 35 〇. In the temperature range of the crucible, the heat treatment temperature of the evaluation sample was set to 10 C. The heat treatment was carried out for 30 minutes in a nitrogen atmosphere, and then immersed in a phosphoric acid-based barium etchant (manufactured by Kanto Chemical Co., Ltd. (Japan) at a liquid temperature of 32 ΐ. Under the A1 mixed acid etchant / composition (capacity ratio) dish acid: oxalic acid: acetic acid: water = 16: :: 2: .1) 10 minutes, only the film formed in the upper layer is dissolved, so that the semi-conductive The Lu body layer is out. The exposed surface of the semiconductor layer was observed with an optical microscope (200 times) to investigate whether or not interdiffusion of Si and A1 occurred. Fig. 2 and Fig. 3 are optical micrographs showing the surface of the exposed semiconductor layer. Fig. 2 shows that the surface of the semiconductor layer which is mutually diffused is not observed at all, and Fig. 3 shows the surface of the semiconductor layer where the trace of mutual diffusion (black spots in the photograph) is observed. (1) Diffusion heat resistance is determined by observing a sample of black spots as shown in Fig. 3, and in the sample which is completely unobserved to interdiffusion in Fig. 2, the highest heat treatment temperature value is taken as & diffusion heat resistance The value of the indicator evaluated is described in Table 2. The specific resistance of the film: the specific resistance-value of each of the constituent films described in the first table is formed by a tantalum ore (conditions as described above) on a glass substrate to form a single film (thickness of about 0.3 μm) in a nitrogen atmosphere. Yu Shi. After heat treatment for % minutes in c, it was measured by a terminal resistance measuring device. 35^: heat-resistant H · The heat-resistant system of each constituent film described in the second table is formed by monolithic β-degree, 'spoon (λ3μιη)' in a nitrogen atmosphere by money plating (conditions are the same as above). Yu Gang to the shed. Temperature of c 318169 22 1326309 After heat treatment for 30 minutes, the surface of the film was observed by a scanning electron microscope 'SEM (10,000 times). Further, this SEM observation was carried out for 5 fields of view in each of the & samples in an observation range of 1 μm μ>< 8 μm. After that, the evaluation of the heat resistance at 350 ° C was carried out in a heat treatment at 350 ° C for 30 minutes, and it was confirmed whether or not the protrusion (valiform) having a diameter of 0.1 μm or more on the observation surface or the concave portion on the observation surface was observed. The number of depressions (diameter 〇.3μπι to -0.5μιη) is four or more, and if any, it is marked as X. There are no protrusions at all, and those with a depression of 3 or less are marked as 〇. ΙΤΟ ΙΤΟ : : : : ΙΤΟ ΙΤΟ ΙΤΟ ΙΤΟ ΙΤΟ IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT IT In this manner, each constituent film layer (thickness 2000 A, circuit width ΙΟμηη) was formed on the above-mentioned ΙΤΟ-electrode layer, and then this test sample (Kelvin element) was used for evaluation. For the preparation of this test sample, first, an A1 alloy film having a thickness of 2000 A was formed on a glass substrate under the above sputtering conditions using each of the A1 | alloy target having the above composition. The substrate temperature at the time of sputtering at this time was set as shown in Table 6, and the film was formed. After that, the surface of each of the A1 alloy films was coated with a photoresist (OFPR800: manufactured by Tokyo Ohka Co., Ltd.), and a pattern film for circuit formation having a width of ΙΟμηη was disposed and exposed to a concentration of 2.38% and a liquid temperature of 23°. The test imaging solution of C tetramethylammonium hydroxide (hereinafter referred to as TMAH developing solution) is subjected to development processing. After the development, the circuit was formed by a phosphoric acid mixed acid etching solution (manufactured by Kanto Chemical Co., Ltd., Japan), and a dimethyl sulfide (hereinafter referred to as 23 318169 1326309: DMSO) stripping solution was used. The photoresist is removed to form an A1 alloy film having a width of ΙΟμπι, and an electric circuit. Then, the substrate on which the A1 alloy film circuit having a width of ΙΟμπι was formed was subjected to pure water washing and drying treatment, and an insulating layer (thickness 4200 A) of SiNx was formed on the surface. The film formation of this insulating layer was carried out by sputtering using a sputtering apparatus under the conditions of sputtering power of RF 3.0 Watt/cm 2 , argon flow rate of 90 sccm, nitrogen gas flow rate, 10 sccm, pressure of 0.5 Pa, and substrate temperature of 300 °C. Then, the surface of the insulating layer is coated with a positive photoresist (Toku-Tokyo, manufactured by Tokyo Ohka Co., Ltd. (Japan): TFR-970), and a pattern film for contact hole opening of ΙΟμηηχΙΟμπι square is placed and exposed to light. Like processing. Thereafter, a dry etching gas of CF4 is used to form a contact hole. The contact holes were formed under the conditions of a CF4 gas flow rate of 50 sccm, an oxygen flow rate of 5 sccm, a pressure of 4.0 Pa, and an output of 150 W. The photoresist stripping treatment was performed by the above DMSO stripping solution. Thereafter, the remaining stripping liquid was removed by using isopropyl alcohol, followed by washing with water and drying. I. For each sample after the stripping treatment to terminate the photoresist, an ITO target (composition of In2〇3 - l〇wt% Sn〇2) was used to form an ITO transparent electrode layer in and around the contact hole. The formation of the ITO transparent electrode layer was performed by sputtering (substrate temperature: 70 ° C, input power: 1.8 Watt/cm 2 , argon gas flow rate: 80 sccm, oxygen gas flow rate of 0.7 seem, pressure: 0.37 Pa) to form an ITO film having a thickness of 1000 A. The surface of the ITO film was coated with a photoresist (OFPR800, manufactured by Tokyo Ohka Co., Ltd., Japan), and a patterned film was placed and exposed to light. The image was processed with a TMAH developing solution, and an acid etching solution was mixed with oxalic acid (Kanto). Chemical 24 318169 1326309 * : A system of ΙΟμπι width formed by ITO05N. After the formation of the ruthenium circuit, the photoresist was removed with a DMSO stripper. Each of the test samples produced by the above production method was subjected to heat treatment at 250 ° C for 30 minutes in an atmospheric environment, and then continuously energized (3 mA from the terminal portion of the arrow portion of the test sample shown in Fig. 4 ) to determine the resistance. The resistance measurement conditions at this time were carried out in an atmospheric environment of 85 ° C under the so-called life acceleration test conditions. Then, under the condition of the accelerated life test, the time (fault time) of the resistance value changed to 1 〇〇 or more of the initial resistance value at the start of the measurement was investigated for each test sample. Under this life-sustaining test condition, a test sample that does not fail even if it exceeds 250 hours is evaluated as 〇. In addition, under this life accelerated test condition, the test sample that caused failure under 250 hours was evaluated as: X. The above-mentioned life-sustaining test conditions are based on Japanese JIS C 5003: 1974, References (title "Efficient Methods and Practices for Accelerated Accelerated Tests": Edited by Lukang Yangji, and issued by Japan Science and Technology Corporation (shares) . IZO bondability: This IZO bondability is the same as the above-mentioned ITO bond. The same as the IZO (In2〇3 - l〇.7wt% ZnO: thickness 1000 A, circuit width 50 μιη) electrode layer, in a crossover manner Each of the A1 alloy film layers (thickness 2000 A, circuit width ΙΟμπι) was formed, and then evaluated using this test sample (Kjeldahl element). The conditions for the preparation of this test sample were the same as those for the above-mentioned ΙΤΟ bondability. Further, the test specimen was subjected to the test conditions under the same life as the above-described crucible bondability, and the electric resistance was measured for the test specimen, and the crucible joint evaluation was performed from the life accelerating test result. The evaluation criteria are also the same as the above-mentioned enthalpy. 25 318169 1326309: As shown in the first table, in the A1-Ni-B alloy wiring material according to each embodiment of the present invention, the specific resistance value is 1 〇μΩ ειη or less and is outside the composition range of the present invention. Comparative Example 9, Comparative Example η, and Comparative Example 12' were specific resistance values exceeding 10 μcm. Further, as shown in the second table, in the Al—Ni—B alloy wiring material of each of the examples, the Si diffusion resistance is 24 (TC or more, even at 330. The high temperature is also present at the bonding interface. No interdiffusion of Si and A1 was observed. Further, as shown in Table 2, - in the Al-Ni-B alloy wiring material of each of the examples, a transparent electrode layer which can be combined with Lusa or IZ0 was also confirmed. Direct bonding. This Si diffusion heat resistance: It is practically not required to be generated in a heat treatment of 200 C or more. If the thermal history applied when forming an insulating layer by CVD is considered, it is reasonable. 240. (: to 30 (there is no deterioration layer in the high temperature range of TC. In addition, in order to make the applicable range of the manufacturing conditions applied by the thermal history of the component process have a large allowable range, it is preferable to have 33〇 On the other hand, in Comparative Examples 1 to 3, it was confirmed that other characteristics except for the specific resistance were practically insufficient. In Examples 4 and 5, the bonding property with the transparent electrode layer was However, in heat resistance and Si diffusion heat resistance, in Comparative Example 6 in which the Ni content is high, the specific resistance of the film exceeds the comparative examples 7 to 12 outside the composition range of the present invention, and is directly related to IT0. The bonding has a problem (Comparative Example 7), Si diffusion heat resistance is 2 〇〇〇 c or less (Comparative Example 8 and Comparative Example 1 〇), and specific resistance value exceeds 10 # Ω cm (Comparative Example 9, Comparative Example π, Comparative Example) 12) Therefore, the film characteristics were not able to meet the overall requirements. Further, in Comparative Example 13 containing yttrium (Si) 318169 26 1326309 instead of nickel, not only the Si diffusion heat resistance was poor, but also the bonding property with the transparent electrode layer was inferior. Further, in the conventional Al-Ni-C alloy wiring material proposed by the applicant of the present application (Comparative Example 14 and Comparative Example 15), although the bonding property with the transparent electrode layer was not problematic, the heat and Si were confirmed. Diffusion is insufficient in heat. Second Embodiment: In the second embodiment, the composition range of the ._A1—Ni—B alloy wiring material according to the present invention is between the heat resistance of the film and the bonding property of the semiconductor layer. Relationship, deeper The third table to the fifth table indicate the specific resistance of the film and the generation rate of the film when changing the content and the content of the shed, and the occurrence of the altered layer when directly bonded to the semiconductor layer. And the result of the change in the surface roughness of the semiconductor layer.

318169 27 1326309 [Table 3]

Composition at% specific resistance # Ω cm depression generation rate % composition at% specific resistance β Q cm depression generation rate Ni B 350 〇 C 400 ° C Ni B 350 〇 C 400. . 3.0 0.30 4.07 1.61 2.03 5.0 0.05 4.03 0.53 1.42 3.0 0.40 4.11 1.63 1.63 5.0 0.10 4.07 0.57 1.60 3.0 0.50 4.13 1.70 1.67 5.0 0.20 4.53 0.67 1.62 3.0 0.60 4.18 1.67 2.11 5.0 0.30 4.50 1.27 1.50 3.0 0.80 4.22 1.75 3.55 5.0 0.40 4.55 1.52 1.73 3.0 1.00 4.28 1.71 4.15 5.0 0.50 4.58 1.56 1.79 3.0 1.80 4.35 1.87 4.97 5.0 0.60 4.62 1.50 1.73 4.0 0.05 3.85 1.21 1.72 5.0 0.80 4.67 1.60 185 4.0 0.10 3.92 1.20 1.65 5.0 1.00 4.73 1.72 1.94 4.0 0.20 4.01 1.22 1.97 6.0 0.05 4.30 0.60 1.32 4.0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4.0 1.00 4.52 1.73 1.90 6.0 0.60 4.74 0.98 1.33 6.0 0.80 4.98 1.42 1.65 6.0 1.00 5.05 1.70 1.88 7.0 0.30 5.19 0.87 1.23 8.0 0.50 5.50 1.22 1.57 8.0 1.00 5.70 1.75 1.95 28 318169 1326309 [Table 4] Group·at at% Metamorphic layer Composition at% metamorphic layer Ni B 300 °C 330〇C 350〇C Ni Β 300°C 330〇C 350〇C 3.0 0.30 Δ Δ X 5.0 0.05 〇Δ △ 3.0 0.40 Δ Δ X 5.0 0.10 〇〇△ 3.0 0.50 Δ Δ X 5.0 0.20 〇〇△ 3.0 0.60 Δ Δ X 5.0 0.30 〇〇〇3.0 0.80 〇Δ X 5.0 0.40 〇〇〇3.0 1.00 〇Δ X 5.0 0.50 〇〇〇3.0 1.80 〇〇Δ 5.0 0.60 〇〇△ 4.0 0.05 〇Δ Δ 5.0 0.80 〇〇Δ 4.0 0.10 〇Δ Δ 5.0 1.00 〇〇Δ 4.0 0.20 〇〇Δ 6.0 0.05 〇〇Δ 4.0 0.30 〇〇Δ 6.0 0.10 〇〇△ 4.0 0.40 〇〇〇6.0 0.20 〇〇△ 4.0 0.50 〇〇Δ 6.0 0.30 〇〇△ 4.0 0.60 〇〇Δ 6.0 0.40 〇〇〇4.0 0.80 〇〇Δ 6.0 0.50 〇〇△ 4.0 1.00 〇〇Δ 6.0 0.60 〇〇△ 6.0 0.80 〇〇Δ 6.0 1.00 〇〇△ 7.0 0.30 〇〇△ 8.0 0.50 〇〇△ 8.0 1.00 〇〇Δ 29 318169

Composition at% Roughness variation Ni B 300°C 330〇C 350〇C 5.0 0.05 1.14 0.98 1.58 5.0 0.10 1.12 1.02 1.32 5.0 0.20 1.01 1.10 1.38 5.0 0.30 1.03 1.08 1.35 5.0 0.40 1.14 0.92 1.20 5.0 0.50 1.37 1.42 1.50 5.0 0.60 1.04 0.99 0.96 5.0 0.80 1.01 1.01 1.06 5.0 1.00 0.99 0.97 1.12 6.0 0.05 1.02 0.95 1.03 6.0 0.10 1.00 1.08 1.08 6.0 0.20 1.05 0.98 0.94 6.0 0.30 1.06 0.91 0.92 6.0 0.40 0.95 0.93 1.02 6.0 0.50 1.30 1.20 0.92 6.0 0.60 0.94 0.93 1.18 6.0 0.80 0.91 1.03 1.04 6.0 1.00 0.95 0.95 1.10 7.0 0.30 1.06 1.12 1.11 8.0 0.50 1.02 0.92 1.08 8.0 1.00 0.91 0.96 1.04 The third table shows the specific resistance value and the generation rate of the depression of the film of each composition. The measurement conditions of the specific resistance value of 臈 are evaluated in the same manner as in the first embodiment described above, and the heat generation temperature is 35 Torr under the same conditions as those of the heat resistance of the first embodiment. 〇, 4〇〇t: The results obtained by sem observation of each of the 1 羡. In order to evaluate the heat resistance of the second embodiment, the heat resistance-depression of the above-described first embodiment was examined in detail. Therefore, the investigation of the generation rate of the depression was performed. The 0 generation rate is determined by the observation surface to be a concave portion (straight protection: two 0.5 m), and the depression is calculated from the size and number thereof; and the depression area is determined relative to the observation area. The area ratio is used to determine the value of the depression. The calculation of the area of the depression is performed by 318169 30 image analysis for the existence of the concave part of the concave part: the concave part is binarized, and the trapping time is about 'in the measurement of several concave pairs Observe the value of the rate of occurrence of the sag of the sample, and the mean value. _ (4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In the following, the ratio is 5.0 μΩ (; ηη or less. In addition, the 铋笸 value is recognized, the 埶 is processed, and the 厗 厗 厗 , , , , , , , , , 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各 各The tendency to increase is the tendency to be smaller, and the tendency to increase 35 〇m is confirmed when the increase is increased. From the results of the 帛3 table, it can be known that the rail treatment is carried out at 350C for 30 minutes. In order to suppress the generation rate of the depression at 1.6 M, it is only necessary to set the nickel content to be (in the case of 心.80 at% or less in the center of the heart. The third is in the joint interface shown in Table 4). The investigation result of the change of the y layer was carried out. The metamorphic layer investigation was an evaluation sample prepared under the same conditions as the evaluation of the Si diffusion heat resistance described in the first embodiment, specifically, by CVD on a glass substrate. Form n + - with semiconductor layer (300 A) 'by sputtering (magnetron sputtering device, input power 3 〇 Wat ^ m2, helium flow L〇〇sccm, argon pressure 05Pa), an A1_Ni_B alloy film of each composition shown in Table 4 is formed on the semiconductor layer (after 2〇〇〇Abu, the evaluation sample is 300, 33〇, 35〇< At each temperature of t, after heat treatment for 30 minutes in a nitrogen atmosphere, the above-mentioned linonic acid-based A1 etching solution was used to dissolve only the A1-based alloy film formed on the upper layer, and the conductor layer was exposed by half 318169 31 1326309. The surface of the exposed semiconductor layer was observed by an optical microscope (200 times), and the presence of a modified portion of the black dot indicated by the third circle was confirmed, or the surface of the semiconductor layer was discolored or roughened. In Table 4 If a large number of black spots are observed due to the interdiffusion of Si and A1, it is evaluated as x. If the presence or absence of several black spots is observed or no black spots are observed, the discoloration and roughness of the observed surface are observed. The state is evaluated as △, - if the surface is completely free of black spots, and no discolored or rough surface-surface state is observed, it is evaluated as 〇. • Next, the fifth table indicates that the above deterioration is accompanied. Layer survey check

The surface state of the semiconductor layer is changed. The change in the surface state of the semiconductor layer is carried out by measuring the surface roughness of the semiconductor layer. Specifically, the surface roughness (hereinafter referred to as as_dep〇 thick chain degree) after forming the n+—Si semiconductor layer (300 A) on the glass substrate, and the evaluation sample of the above-described metamorphic layer investigation are respectively measured. The surface roughness of the exposed semiconductor layer (hereinafter referred to as direct joint roughness) is calculated (the value of the direct joint roughness call) / (the value of the aS-deP〇 roughness, that is, as shown in the fifth table) The larger the value of the amount of roughness change is, the coarser the surface state of the semiconductor layer after direct bonding and heat treatment. The measurement of the surface roughness of the semiconductor layer is determined by the step/surface roughness/fine shape. Device (KLA

Tencor company: p_i5 type), and according to b〇601: 1994, the ten point average roughness RZ is obtained. From the results of the fourth table, it was confirmed that the more nickel, the more the tendency of the metamorphic layer to be suppressed. Also confirmed, at 33 〇. In the heat treatment of bismuth, if the nickel content is 4.0 at% to 6 』at%, the boron content is 〇20 at% to 〇 8 〇 at%, 318169 32 1326309 .., the occurrence of the metamorphic layer is more inhibited. Further, it has been confirmed that if the nickel content is from 4.0 at% to 6.0 at% and the boron content is from 0.30 at% to 0.50 at%, the deterioration layer is not formed even at a high temperature of 350 °C. Regarding the amount of change in the roughness of the fifth table, it was found that the tendency to be roughly related to the result of the altered layer of the third table was exhibited. As a result of the amount of change in the roughness of the fifth table, it was found that even after the direct bonding and the heat treatment at 330 ° C, the joint surface of the semiconductor layer did not become extremely rough, that is, as The composition of the amount of change within -1.5 times the value of -depo coarseness is from 4.Oat% to 6.Oat%, and the boron content is from 0.20 at% to 0.60 at%. Third Embodiment: In the third embodiment, the results of investigation of the surface roughness when the film is formed by money plating will be described. In the third embodiment, the A1-Ni-B alloy film of the composition of Al-5.0 at%Ni - 0.4 at% B in the Al-Ni-B alloy wiring material of the present invention (Example 15) is compared. The pure A1 film (the same as the first embodiment described above was set as Comparative Example 1) and the Al-2.0 at% Nd alloy film (Comparative Example 16) were investigated. First, the film formation conditions of Example 15, Comparative Example 1, and Comparative Example 16 were the A1 alloy target of the above composition, and the sputtering conditions were an input power of 3.0 Watt/cm 2 , an argon flow rate of 100 sccm, and an argon pressure of 0.5. Under Pa, a magnetically controlled reduction; a plating apparatus (manufactured by Tokki Co., Ltd.: Multichamber • Type sputtering apparatus MSL464) was used to form each alloy film having a thickness of 2000 A on a glass substrate (manufactured by Corning Incorporated (USA), #1737). . Further, the substrate temperature at the time of sputtering was set as shown in Table 6. Next, the surface roughness Ra of each alloy film shown in Table 6 was measured. In the measurement of the surface roughness, an atomic force microscope (SPI-3800N, manufactured by Seik0 Instruments Co., Ltd., Japan) was used to obtain an arithmetic mean roughness Ra (JIS B0601-1982). Further, this measurement was carried out by measuring five points on the surface of each alloy film to calculate the average value. The result is shown in Table 6. In Table 6, Examples 15 - 1 to 3 show the substrate temperature of 1 Torr to 25 Å. 〇 The result of A1-5.0 at%Ni—〇.4at%B alloy film. Further, in this - the sixth table, the result of the A]-5 alloy film at the substrate temperature at room temperature is Comparative Example 17, and the substrate temperature is 31-times at the time of A1-5.0 at%Ni-〇.4at The result of the %B alloy film was Comparative Example 18. Further, Comparative Example 1 shows a pure ruthenium film, and Comparative Example 16 shows the result of an Al-2. 〇at alloy film. Further, the value of the average surface roughness (Ra) of the surface of the glass substrate was 1.8 A. [Table 6] 1 plate temperature (°δΤ

i Comparative Example 17 f Example 15 15^2 From the results of Table 6, it was confirmed that the surface roughness of the Α1 - State-6 alloy film varies depending on the substrate temperature. Further, in the pure Al film of Comparative Example 1, a very rough surface state was formed, and in the A1-2.0 at/Nd alloy film of Comparative Example 16, even if the substrate temperature was just. c or so, also 318169 34 1326309 ^ Ra over 20 A rough surface state. Next, the results of investigation of the contact resistance value directly bonded to the transparent electrode layer and the bonding strength will be described. First, the measurement of the contact resistance value will be described. As described above for the measurement of the surface roughness, an A1 alloy film having a thickness of 2000 A was formed on the glass substrate under the above sputtering conditions using the A1 alloy target of the above composition. At this time, the substrate temperature at the time of sputtering was each formed at the temperature shown in Table 6. After that, the surface of each of the A1 alloy films is coated with a photoresist _ (OFPR800: manufactured by Tokyo Ohka Co., Ltd.), and a pattern film for circuit formation of 20 μm width is placed and exposed, and the first embodiment is used. Explain the development of the imaging solution. After the development process, the circuit was formed by the phosphoric acid mixed acid etching solution described in the first embodiment, and the photoresist was removed by a DMSO stripping solution to form a 20 μm wide tantalum 1 alloy film circuit. Thereafter, the substrate on which the Α1 series alloy film circuit having a width of 20 μm was formed was subjected to pure water washing and drying treatment to form an insulating layer of SiNx (thickness: 4200 A) on the surface thereof. The film formation of this insulating layer was carried out by using a sputtering apparatus under the sputtering conditions of a power of RF of 3.0 Watt/cm 2 , an argon flow rate of 90 sccm, a nitrogen gas flow rate of 10 sccm, a pressure of 0.5 Pa, and a substrate temperature of 300 °C. Then, a positive-type photoresist (TFR-970, manufactured by Tokyo Ohka Co., Ltd.) was placed on the surface of the insulating layer, and a pattern film for contact hole opening of ΙΟμπίχΙΟμιη square was placed and exposed to light to perform development with a sputum developing solution. deal with. Thereafter, a dry etching gas of CF4 is used to form a contact hole. The contact holes were formed under the conditions of a CF4 gas flow rate of 50 sccm, an oxygen flow rate of 5 sccm, a pressure of 4.0 Pa, and an output of 150 W. 35 318169 1326309. The photoresist stripping treatment was then carried out by a DMSO stripper. After the residual stripping solution was removed by using isopropyl alcohol, it was washed with water and dried. For each sample after the stripping treatment to terminate the photoresist, an ITO target (composition ln203 - 10 wt% SnO2) was used to form an ITO transparent electrode layer in and around the contact hole. The formation of the transparent electrode layer was performed by sputtering (substrate temperature: 70 ° C, input power: 1.8 Watt/cm 2 , argon gas flow rate: 80 sccm, oxygen gas flow rate - 0.7 sccm, pressure: 0.37 Pa) to form an ITO film having a thickness of 1000 A. The surface of the ITO film is coated with a photoresist (Tokyo Kasei Co., Ltd. (Japan) _: OFPR800), and a patterned film is placed and exposed to light. The development process is carried out with TMAH developing solution, and the oxalic acid mixed acid etching solution is used. (made by Kanto Chemical Co., Ltd. (Japan): ITO05N) to form a circuit having a width of 20 μm. After the • film circuit is formed, remove the photoresist with a DMSO stripper. The contact resistance was measured for the evaluation sample in which the contact hole was formed in the above-described step, and the Α1 conjugated-gold film and the transparent electrode layer were directly bonded via the contact hole. This contact resistance value is measured by the I four-point terminal method shown in Fig. 4, after the components of the evaluation sample are annealed at 250 ° C for 30 minutes in the atmosphere, and the resistance value of each evaluation sample is measured. . The measurement results of this contact resistance value are shown in Table 7. The four-point terminal method shown in Fig. 4 measures the resistance by energizing 1 〇〇 μΑ from the terminal portion of the heat-treated evaluation sample. Next, the measurement of the bonding strength directly bonded to the transparent electrode layer will be described. This joint strength was carried out by a checkerboard test according to JIS C 5012. In the same manner as in the measurement of the above surface roughness, each of the ruthenium-based alloy films (2000 Å) was formed on the glass substrate, and the ruthenium film 36 318169 1326309 (1000 A) was laminated thereon. The film formation conditions are the same as those described above. For each evaluation sample made in this way, use the (four) device from the side of the enamel surface to form 40 squares with 5 mm per side: a square-shaped cut (a square of 5 mm square is vertical) 4 (2 〇 god horizontal H) (50mm)). Thereafter, the tape (4) e) was attached to the surface, and then the tape was peeled off, and the state of the square set on the surface of the film after peeling of the tape was visually confirmed. And measuring the area of the portion of the film which was peeled off in 4 squares to calculate the ratio of the total area of the squares of 4 squares (peeling rate %), and evaluating the bonding strength 4 peeling rate of each evaluation sample to 20% is 〇, with a peeling rate of 21 to 6〇% as Δ, and a peeling rate to %. The test results of this joint strength are shown in Table 7. [Table 7]

From the results of the sixth table and the seventh table, it is found that the larger the rough surface degree of the Α1 alloy film, the greater the contact resistance value at the time of element formation, and the opposite the 'joint strength has the surface roughness. The smaller the smaller the tendency. From the above results, it is understood that when the contact resistance value is 200 Ω or less, the surface roughness of the practical joint strength can be ensured, and it is preferable that Ra is 2.0 Α to 37 318169 1326309 *, and the range of 20 A is more preferably Ra 10 A to 20 A range. Fourth Embodiment In the fourth embodiment, a result of investigation of precipitates of a wiring circuit formed of the Al-Ni-B alloy wiring material of the present invention will be described. The investigation of the precipitates in the wiring circuit is performed by analyzing the dispersion state. Here, the method of producing the sample for cross-sectional observation of the fourth embodiment will be described. - The sample for cross-section observation was formed by sputtering to form an Al-5.0 at%Ni-0.4at%B alloy film having a thickness of 200 nm on a glass substrate, and entering 1-♦ 2.0 at%Ni~~ i.0at The %Nd alloy film and the A1_3 〇at%Ni alloy film were formed by forming an ITO film on each alloy film and then heat-treating at 250 ° C in the air. Fig. 5 and Fig. 6 show a through-transmission electron microscope (manufactured by Hitachi, Ltd.) in Al-2.0at%Ni -1.0at%Nd alloy and Al - 5.0at%Ni - 0.4at%B alloy. /η- 9000 TEM: 2 million times magnification) A schematic cross-sectional view of the result of observing the cross section of the wiring circuit layer (film). The symbols 第 in FIGS. 5 and 6 are enamel films, and the symbol Β is a glass substrate. φ Next, a method of evaluating the dispersion state of the precipitate from the above-mentioned ΤΕΜ observation photograph will be described. The central strip portion of Fig. 6 shows the wiring circuit, and the disperse therein is a Ni compound (the distribution state of the Al-Ni-based intermetallic compound with respect to the Νι compound, and the wiring circuit layer is measured as shown in the schematic cross-sectional view. The line orthogonal to the thickness direction cuts the total length of the Ni compound (1 ι + 丨 2+ 丨 3 + U + ls + 1 ό = Σ 1), and finds the ratio (%) to the overall length of the line, and takes the value In addition, when the compound is identified by EDX analysis, it is an A1_5 〇at%Ni—〇4 elbow% B alloy wiring material, and the Ni compound is dispersed and deposited in the wiring circuit layer.

3S 318169 1326309, an intermetallic compound of the Al3Ni phase. In the case of Al-2.0 at% Ni-1.0 at % Nd alloy wiring material, an intermetallic compound of A1 - Ni system, A1 - Nd system, Al - Ni - Nd system is precipitated. Further, as shown in the schematic view of Fig. 5, when A1 - 2.Oat%Ni - 1.0 at% Nd alloy is used, it is confirmed that a large amount of Al-Ni-Nd system is segregated on the glass substrate side (symbol B). Intermetallic compound. On the other hand, when it is A1 - 5.0 at%Ni - 0.4at% B alloy - the precipitate in the wiring circuit layer is an intermetallic compound of the Al3Ni phase, and it is not particularly segregated, and can be uniformly dispersed. Lu 7 shows the results of investigation of the existence rate of Ni compound at a predetermined thickness position in the thickness direction of each wiring circuit layer. As shown in Fig. 7, when it is Al-2.0at%Ni-1.0at%Nd alloy, it can be known that the existence ratio of the Ni compound is 75% from the glass substrate side (B) to the ITO film surface side (A). Change to 0%. Similarly, with respect to the A1 - 3.0 at% Ni alloy wiring material, the presence rate of the -Ni compound was also investigated, and it was found that the existence ratio was changed from 40% to 0% from the substrate side to the film surface side. On the other hand, in the case of the A1 $ -5.0 at%Ni-0.4at%B alloy wiring material of the present invention, the existence ratio of the Ni compound does not have a large numerical difference from the substrate side to the film surface side, about 25 In the range of % to 45%, it was found that segregation of the Ni compound did not occur and the dispersion was uniform. (Industrial Applicability) As described above, according to the present invention, even if a coating layer composed of a high melting point metal material such as Mo is omitted, it can be formed to be directly bonded to a transparent electrode layer such as ITO or IZO, and can be bonded to a film. A wiring circuit in which a semiconductor layer such as n+-Si of a transistor is directly bonded. In particular, in the process of heat generation at a temperature exceeding 240 ° C, in the process of bonding the wiring circuit composed of the A1-Ni-B alloy wiring material of the present invention directly to the semiconductor layer, A1 and Si can be suppressed. Mutual diffusion. Further, the Al-Ni-B alloy wiring material of the present invention is excellent in heat resistance and has a specific resistance of 10.0 pQCm or less, and is therefore suitable as a constituent material of a display having a large screen. As described above, the present invention is a technology of a display device which can reduce cost and can achieve good characteristics in all aspects of the material surface, the equipment surface, and the process-surface of the manufacture of a display device such as a liquid crystal display. Eight [Simplified description of the drawings] Fig. 1 is a schematic cross-sectional view of a TFT. Fig. 2 is an optical micrograph of the evaluation of Si diffusion heat resistance. Fig. 3 is an optical micrograph of the evaluation of Si diffusion heat resistance. Fig. 4 is a schematic perspective view showing a test sample in which an ITO (IZO) electrode layer and an A1 alloy electrode layer are laminated and laminated. • Figure 5 is an overview of the photograph of Al-2.0at%Ni—l.〇at%Nd alloy. Fig. 6 is a schematic view of a photograph of an Al-5.0 at% Ni-〇.4 at% B alloy. - Fig. 7 is a graph showing the measurement of the existence rate of the Ni compound. [Main component symbol description] Glass substrate 2 Electrode wiring circuit layer Covering layer 4 Gate insulating film 4' Insulating film 5a_Si Semiconductor layer 318169 40 1326309 6 Channel protective film layer 7n+- Si Semiconductor layer 7, Transparent electrode layer G Gate Electrode portion D drain electrode portion S source electrode portion 41 318169

Claims (1)

1326309 Know [丨月修iE.3 Patent scope: No. 4 patent application T丄丄月4日) 1. A kind of A1—Ni—B alloy wiring material, which is made of aluminum containing a nickel and boron A1— The Al—Ni—B alloy wiring material used in the element structure of the wiring circuit layer formed of the Ni—B alloy wiring material and the display device of at least one of the semiconductor layer and the transparent electrode layer is: The content is set to the atomic percentage Xat% of nickel, and the boron content is determined to be the atomic percentage Yat% of the deletion, which is in the following formula. Also • 〇.5^X^l〇.〇 0.05^Y^ll.〇〇 0.25+0.25X^1.〇〇 Y+l.15X^11.5〇 The area of the area, and the remaining part is aluminum. • 2· If you apply for a patent scope! Item A1 - See "Gold wiring material" in which the nickel content is 4.0 at% or more and the boron content is 〇 8 〇 at% or less. #3. For example, the A1_Ni — B$ gold wiring material of the second item of the patent application scope, wherein, at 350. After the heat treatment for 30 minutes under the armpit, the generation rate of the depression generated on the surface of the wiring material was i or less. 4. For the A1—Ni_B alloy wiring material in any of the items 1 to 3 of the patent application, wherein the nickel content is 4.〇at% to 6.0at%, and the boron content is 0.20at% to 〇.80at. %. 5. The A1_Ni-β alloy wiring material according to item 4 of the patent application, wherein the 'specific resistance value is 5.0 μΩ οηη or less. 6. The component structure of the display device is determined by the patent application scope 1 (amendment) 318169 • Patent No. 95114832, T5T-production (November 4, 1998 > to item 5) Any one of a wiring circuit layer formed of an AI-Ni-B alloy wiring material, and a semiconductor layer or a transparent electrode layer. The wiring layer is directly bonded to the wiring circuit layer, and is characterized in that: The Ni compound is dispersed and deposited on the circuit layer; the existence ratio of the Ni compound on the line perpendicular to the thickness direction of the wiring layer of the wiring circuit layer is 25% to 45% in the thickness direction of the wiring layer; _ will be directly bonded The surface roughness (Rz) of the surface of the semiconductor layer after peeling off the wiring circuit layer is 1.5 times or less of the surface roughness (RZ) of the surface of the semiconductor layer after the semiconductor layer is formed; • Al-Ni-B alloy wiring material The surface roughness Ra of the formed Al-Ni_B alloy film is 2·0 A to 20·0 A, and the A1—Nl—B alloy wiring material is formed by directly bonding the semiconductor layer and/or the transparent electrode layer. Wiring circuit layer 7. A sputter target used to form a wiring circuit formed by the A1_Ni-B alloy shouting material of the scope of the patent application range i to 苐$ _ towel--the characteristic is: nickel When the inner content is set to the atomic percentage Xat% of nickel, and the boron content is set to the atomic percentage Yat% of boron, the system is located in the following formula: 〇·5^Χ^ι〇.〇〇.〇5^Y^ ii. Oo Y+0.25X^ l.oo Y+l.15X^11.50 within the range of the area, and the rest is aluminum. (Revised) 3] 8169 43