WO2006117884A1

WO2006117884A1 - Al-Ni-B ALLOY WIRING MATERIAL AND DEVICE STRUCTURE USING SAME

Info

Publication number: WO2006117884A1
Application number: PCT/JP2005/015697
Authority: WO
Inventors: Hironari Urabe; Yoshinori Matsuura; Takashi Kubota
Original assignee: Mitsui Mining & Smelting Co., Ltd.
Priority date: 2005-04-26
Filing date: 2005-08-30
Publication date: 2006-11-09
Also published as: JP4657882B2; CN101090985A; JP2006330662A; CN100564560C

Abstract

Disclosed is an Al-based alloy wiring material which can be directly bonded not only with a transparent electrode such as ITO or IZO but also with a semiconductor layer such as n+-Si in a display device comprising a thin film transistor and a transparent electrode. Specifically disclosed is an Al-Ni-B alloy wiring material wherein the nickel content and the boron content are within the ranges satisfying the following formulae: 0.5 ≤ X ≤ 10.0, 0.05 ≤ Y ≤ 11.0, Y + 0.25X ≥ 1.0 and Y + 1.15X ≤ 11.5 when the atomic percentage of the nickel content is expressed as X at% and the atomic percentage of the boron content is expressed as Y at%, and the balance is composed of aluminum.

Description

Specification

Al-Ni-B alloy wiring material and device structure using it

Technical field

TECHNICAL FIELD [0001] The present invention relates to an A1-based alloy wiring material used for an element of a display device such as a liquid crystal display, and in particular, an Al—Ni—B alloy wiring material suitable for a display device including a thin film transistor and a transparent electrode. It relates to the element structure used.

Background art

In recent years, wiring materials made of aluminum (hereinafter sometimes simply referred to as “A1”) alloy have been widely used as a constituent material for display devices such as thin-screen televisions typified by liquid crystal displays. The reason for this is that the specific resistance value of the A1-based alloy wiring material is low and the wiring process is easy.

[0003] For example, in the case of an active matrix type liquid crystal display, a thin film transistor (hereinafter abbreviated as TFT) as a switching element, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), etc. An element is composed of the transparent electrode and a wiring circuit made of an Al-based alloy wiring material. In such an element structure, there are a portion where a wiring circuit made of an A1-based alloy wiring material is bonded to a transparent electrode and a portion where n + -Si (phosphorus-doped semiconductor layer) is bonded in a TFT.

[0004] In the currently used A1 alloy wiring material, when the above-described element is configured, the influence of the aluminum oxide formed on the A1 alloy wiring material is considered, and the wiring circuit and the transparent A refractory metal material such as molybdenum (Mo) or titanium (Ti) is formed between the electrodes as a so-called cap layer. In addition, in the connection between a semiconductor layer such as n + -Si and a wiring circuit, the thermal process during the manufacturing process prevents the interdiffusion of A1 and Si between the semiconductor layer and the wiring circuit. The same refractory metal material such as molybdenum (Mo) and titanium (Ti) as the cap layer is interposed! /.

The above element structure will be specifically described with reference to FIG. Figure 1 shows a schematic cross-sectional view of an a-Si TFT for a liquid crystal display. In this TFT structure, an electrode made of an A1-based alloy wiring material constituting the gate electrode portion G is formed on the glass substrate 1. A wiring layer 2 and a cap layer 3 made of Mo, Mo—W, or the like are formed. The gate electrode portion G is provided with a SiNx gate insulating film 4 as a protection. On this gate insulating film 4, an a-Si semiconductor layer 5, a channel protective film layer 6, an _n + -Si semiconductor layer 7, a cap layer 3, an electrode wiring layer 2, and a cap layer 3 are sequentially deposited. By forming the pattern, the drain electrode portion D and the source electrode portion S are provided. On the drain electrode portion D and the source electrode portion S, a surface flattening resin or SiNx insulating film 4 is coated. Further, on the source electrode portion S side, a contact hole CH is provided in the insulating layer 4 ′, and a transparent electrode layer 7 made of ITO or IZO is formed there. As described above, when an A1-based alloy wiring material is used for the electrode wiring layer 1 which is a wiring circuit, the transparent electrode layer 7 and the electrode between the n + -Si semiconductor layer 6 and the electrode wiring layer 1 or in the contact hole CH. The cap layer 3 is interposed between the wiring layer 1 and the wiring layer 1.

In the element structure shown in FIG. 1, since a cap layer such as Mo is formed, the cost of materials and manufacturing equipment is unavoidably increased, and the complexity of the manufacturing process has been pointed out. For this reason, the applicant of the present application has already proposed a technique that makes it possible to omit the cap layer in such a conventional element structure (see Patent Document 1). In this patent document 1, a wiring material of A1—C—Ni alloy or A1—C—Ni—Si alloy capable of direct bonding with ITO is disclosed. Patent Document 1: Japanese Unexamined Patent Publication No. 2003-89864

Disclosure of the invention

Problems to be solved by the invention

[0007] However, the A1 alloy wiring material according to the prior art described above can be directly bonded to a transparent electrode layer such as ITO or IZO, but it can be connected to a semiconductor layer such as n + -Si. In the case of direct bonding, it did not have sufficient characteristics. For example, when an A1-based alloy wiring material and a semiconductor layer are directly bonded, a diffusion phenomenon of A1 and Si may occur at the bonding interface, and the bonding characteristics may not be satisfied.

[0008] The present invention has been made in the background as described above, and in a display device including a thin film transistor and a transparent electrode, direct bonding with a transparent electrode such as ITO or IZO is possible. At the same time, it provides A1-based alloy wiring materials that can be directly bonded to semiconductor layers such as n + -Si. Means for solving the problem

[0009] The inventors of the present application have made extensive studies on Al-Ni alloys, and found that the above problems can be solved by adding a certain amount of boron (B) to the Al-Ni alloy. I came up with an idea.

[0010] In the present invention, in an Al—Ni—B alloy wiring material containing aluminum and nickel and boron, the nickel content is defined as atomic percentage Xat% of nickel, and the boron content is defined as atomic percentage Yat%. ,

Equation 0.5 5≤X≤10. 0 (1)

0. 05≤Y≤11. 0 (2)

Υ + Ο. 25 Χ ≥ 1. 0 (3)

Υ + 1. 15 Χ ≤ 11.5 (4)

An Al—Ni—Β alloy wiring material in which the balance is within the region satisfying each of the formulas and the balance is aluminum. Incidentally, the Al—Ni—K—alloy wiring material in the present invention does not prevent inevitable impurities from being mixed within a range not departing from the effects of the present invention described below.

[0011] Nickel has an effect of forming an intermetallic compound with aluminum by heat treatment to improve bonding characteristics in direct bonding with a transparent electrode. However, if the nickel content increases, the specific resistance of the wiring circuit itself increases and becomes impractical. In addition, if the nickel content is low, the formation of intermetallic compounds with aluminum is reduced, making direct bonding with the transparent electrode impossible, and heat resistance (to prevent plastic deformation of the A1 alloy wiring material due to heat) It tends to decrease. For these reasons, the nickel content must satisfy the above formula (1).

[0012] Specifically, if the nickel content exceeds 10.0 &%, the specific resistance value of the wiring material becomes too large, and a dimple-like defect called dimple is easily formed on the surface of the wiring material. Heat resistance decreases. On the other hand, if it is less than 0.5 at%, a so-called hillock protrusion is easily formed on the surface of the wiring material, and the heat resistance is lowered. This dimple is a small dent-like defect formed on the surface of the material due to the stress strain generated when heat-treating the A1-based alloy wiring material. Adversely affects the bonding reliability. On the other hand, hillocks, contrary to dimples,

Projections formed on the surface of the material due to stress strain generated when heat-treating A1-based alloy wiring material. Even if this hillock occurs, it adversely affects the bonding characteristics and decreases the bonding reliability. These dimples and hillocks are common in that they are plastic deformation of the A1 alloy wiring material due to heat, and are collectively referred to as stress migration. Depending on the level of these defects, the A1 alloy wiring material The heat resistance of can be judged.

[0013] As in the present invention, when boron is added to aluminum in addition to nickel, when A1 and Si are directly bonded to a semiconductor layer such as n + —Si, mutual diffusion between A1 and Si at the bonding interface It has the effect | action which prevents this effectively. Moreover, this boron acts on heat resistance as well as nickel. If the boron content exceeds 11. OOat%, the resistivity of the wiring circuit itself becomes high and becomes impractical. On the other hand, if the content is less than 0.05 at%, the ability to prevent interdiffusion between A1 and Si decreases, and direct bonding to the semiconductor layer becomes impossible. Specifically, when the semiconductor layer and the A1-Ni-B alloy wiring material are directly bonded and heat-treated at a predetermined temperature, interdiffusion between A1 and Si is likely to occur at the bonded portion. Furthermore, dimples tend to occur easily. For this reason, the boron content must satisfy the above formula (2).

[0014] Further, according to the study by the inventors of the present application, the mutual bonding between A1 and Si at the bonding interface is also in the case of direct bonding with the semiconductor layer, even in a thermal process at a temperature exceeding 240 ° C. It was found that the above formula (3) must be satisfied in order to reliably prevent diffusion. Then, it has been found that in order to reliably maintain the specific resistance of the A1-Ni-B alloy wiring material itself at 10 Ωcm or less, the above formula (4) must be satisfied.

[0015] Further, in the range satisfying the above formulas (1) to (4), when the nickel content is 4. Oat% or more and the boron content is 0.80 at% or less, the above-mentioned dimples are generated. As a result, Al-Ni-B alloy wiring material is suppressed as much as possible, and the bonding reliability when directly bonding to the semiconductor layer and the transparent electrode layer can be improved. More specifically, when heat treatment is performed at 350 ° C. for 1 hour, the rate of occurrence of dimples generated on the surface of the Al—Ni—B alloy wiring material can be suppressed to 1.6% or less. [0016] As described above, the dimple is a microscopic defect formed on the surface of the wiring material when the Al—Ni—B alloy wiring material is heat-treated. After performing the prescribed heat treatment on the Ni-B alloy wiring material, the surface of the material was observed and the generated dimples (0.3 to 0.5 m) were investigated. In this dimple survey, the area of all the dimples generated in the observation field was obtained, and the area ratio of the dimples in the observation field was used as the dimple generation rate. As a result, the above-mentioned (1) to (4 ) If the nickel content is 4.0 &% or more and the boron content is 0.80at% or less, the dimple is generated even when heat treatment is performed at 350 ° C for 1 hour. It was found that the rate can be suppressed to 1.6% or less. If the dimple generation rate is low in this way, even if it passes through the thermal process in the element manufacturing process of the display device, it becomes difficult to generate a bonding defect or the like at the bonding interface directly bonded to the semiconductor layer or the transparent electrode. Reliability is improved.

[0017] Further, the inventors of the present application have a nickel content of 4.0 at% to 6. Oat% and a boron content of 0.20 at% within the range satisfying the above formulas (1) to (4). It was found that when it is ˜0.8 at%, it becomes a particularly suitable Al—Ni—B alloy wiring material when directly bonding to a semiconductor layer.

[0018] It is known that when an A1-based alloy wiring material and a semiconductor layer are directly bonded, a diffusion phenomenon between A1 and Si occurs at the bonding interface. They confirmed the phenomenon that an altered layer was formed at the joint interface when they were directly joined due to the effect of mutual diffusion. This altered layer is a direct bond between the A1 alloy wiring material and the semiconductor layer, and after applying a predetermined heat treatment, the A1 alloy wiring material is peeled off and the surface of the semiconductor layer is observed. This refers to an altered portion that becomes a black spot recognized on the surface of the layer, or a state of discoloration or roughness of the surface of the semiconductor layer (in this specification, such a surface of the semiconductor layer is referred to as an altered layer). This deteriorated layer tends to be generated more easily as the heat treatment temperature becomes higher, and it is considered that it is desirable that the deteriorated layer should not be generated by heat treatment (1 hour) at 300 ° C or higher. As a result of examining the composition range in which such a deteriorated layer does not occur, the nickel content is 4.0 at% to 6. Oat% in the range satisfying the above formulas (1) to (4), and the boron content is When the temperature is from 0.20 at% to 0.80 at%, the altered layer can be formed even after heat treatment at 300 ° C for 1 hour. It was found to be suppressed. The specific resistance of the wiring material itself is also 5 Ωcm or less. Furthermore, as described above, since the dimple occurrence rate is extremely low, it is practically very suitable as an Al—Ni—B alloy wiring material for realizing direct bonding with the semiconductor layer.

[0019] Further, the inventors of the present application investigated the change in the surface state of the semiconductor layer. This survey is based on the surface roughness Rz (ten-point average roughness) of the semiconductor layer exposed by peeling off the A1 alloy wiring material after direct bonding and heat treatment, and the surface roughness Rz of the semiconductor layer before direct bonding. This was done by comparing From the investigation results of this surface state change, assuming that the semiconductor layer surface roughness value before direct bonding is 1, the amount of change in which the exposed semiconductor layer surface roughness value after direct bonding and heat treatment is 1.5 times or less In the range satisfying the above formulas (1) to (4), the nickel content is 4.0 at% to 6. Oat% and the boron content is 0.20 at% to They also found out that it was necessary to set it at 0.8.

[0020] Although it is not clear whether the amount of change in the surface roughness of this semiconductor layer is a parameter directly related to the interdiffusion between Si and A1, it changes as the heat treatment temperature increases. It has been confirmed that the amount increases. In addition, changes in the surface state of the semiconductor layer are expected to be affected by the switching characteristics of the TFT. In other words, it is presumed that this leads to a change in the on / off ratio (onZoff ratio) in the thin film transistor. Therefore, even if direct bonding and heat treatment are performed, the surface state of the semiconductor layer does not change so much. It is expected that the characteristics can be maintained well. Regarding the surface state change of the semiconductor layer in direct bonding, the present invention adopts the surface roughness Rz when specifying the semiconductor layer surface state. However, the surface properties described in JIS B0601 etc. Parameters such as surface roughness Ra (arithmetic mean roughness) can also be adopted.

[0021] When an element of a display is manufactured using the Al—Ni—B alloy wiring material according to the present invention described above, the nickel content is set to an atomic percentage Xat% of nickel, and the boron content is set to boron atoms. When the percentage is Yat%, it is preferable to use a sputtering target that is in the range of the region satisfying the above formulas (1) to (4) and the balance being aluminum. In particular, among the ranges satisfying the above formulas (1) to (4), the nickel content is 4.0. A sputtering target having at% to 6. Oat% and a boron content of 0.20 at% to 0.80 at% can easily realize a wiring circuit extremely suitable for direct bonding with a semiconductor layer. When a sputtering target having such a composition is used, an Al—Ni—B alloy thin film having almost the same composition as the force target composition, which may be somewhat affected by the film formation conditions during sputtering, can be easily formed.

Brief Description of Drawings

[0022] FIG. 1 is a schematic sectional view of a TFT.

[Figure 2] Optical micrograph of Si diffusion heat resistance evaluation.

[Figure 3] Optical micrograph of Si diffusion heat resistance evaluation.

FIG. 4 is a schematic oblique view of a test sample in which an ITO (IV) electrode layer and an Al alloy electrode layer are crossed and laminated.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the best embodiment of the present invention will be described.

First Embodiment: In this embodiment, A1—Ni—B alloy wiring materials having respective compositions of Examples and Comparative Examples shown in Table 1 were formed by sputtering, and the characteristics of the films were evaluated. . The sputtering target was prepared by mixing aluminum with metals having the respective compositions shown in Table 1, melting and forging, rolling and molding, and processing the surface to be sputtered flat. The film characteristics of each composition listed in Table 1 were evaluated for Si diffusion heat resistance, film specific resistance, 350 ° C heat resistance, ITO bondability, and IZO bondability. The results are shown in Tables 1 and 2.

[0025] [Table 1]

Si diffusion 350 ^ ITO IZO

Heat resistance Heat resistance Bondability Bondability Example 1 2 4 0 ○ ○ ○

Example 2 2 4 0 ○ ○ ○

Example 3 3 0 0 ○ ○ ○

Example 4 3 3 0 o o ○

Example 5 3 3 0 ○ ○ ○

Example 6 3 3 0 ○ ○ ○

Example 7 3 3 0 I ○ ○ ○

Example 8 3 3 0 ○ ○ ○

Example 9 2 4 0 ○ ○ ○

Example 10 2 6 0 1 ○ ○ ○

Example 11 3 0 0 ○ ○ ○

Example 12 1 3 3 0 ○ ○ ○

Example 13 3 3 0 ○ ○ ○

Example 14 1 3 3 0 ○ ○ ○

Comparative Example 1 1 7 0 X X X

Comparative Example 2 1 7 0 X X X

Comparative Example 3 1 8 0 X X X

Comparative Example 4 2 0 0 X ○ ○

Comparative Example 5 2 5 0 X ○ ○

Comparative Example 6 3 0 0 ○ ○ ○

Comparative Example 7 2 3 0 X X X

Comparative Example 8 2 0 0 X ○ ○

Comparative example 9 3 3 0 ○ ○ ○

Comparative Example 10 1 9 0 X ○ ○

Comparative Example 11 3 3 0 ○ ○ ○

Comparative example 12 3 3 0 1 ○ ○ ○

Comparative Example 13 1 8 0 I X I X X

Comparative Example 14 2 0 0 X ○ ○

Comparative Example 15 2 2 0 I X 1 ○ ○ The measurement conditions for each characteristic evaluation are described below.

Si diffusion heat resistance: As an evaluation sample of this property, an n +-Si semiconductor layer (30 OA) is formed on a glass substrate by CVD, and sputtering (magnetron 'sputtering equipment, input power 3.OWatt / cm ² , an argon gas flow rate of 100 ccm, and an argon pressure of 0.5 Pa) were used in which each composition film (2000 A) shown in Table 1 was formed. Then, the heat treatment temperature of the evaluation sample is set every 10 ° C in the temperature range of 150 to 350 ° C, and after heat treatment for 30 minutes in a nitrogen gas atmosphere, a phosphoric acid-based A1 etching solution (Kanto A1 Mixed Acid Etchant Z Composition (Volume Ratio) Phosphoric Acid: Succinic Acid: Acetic Acid: Water = 1: 1: 2: 1) By soaking at 32 ° C. for 10 minutes, only each composition film formed in the upper layer was dissolved, and the semiconductor layer was exposed. The exposed surface of the semiconductor layer was observed with an optical microscope (200 times) to investigate whether or not interdiffusion between Si and A1 occurred.

FIG. 2 and FIG. 3 show typical optical micrographs on the exposed semiconductor layer surface. Fig. 2 shows the surface of the semiconductor layer where no interdiffusion is observed, and Fig. 3 shows traces of interdiffusion (black spots in the photo). As for Si diffusion heat resistance, the sample with black spots as shown in Fig. 3 is regarded as defective, and among the samples with no mutual diffusion as shown in Fig. 2, the highest heat treatment temperature value is set to Si diffusion heat resistance. Table 2 shows the index values for sex assessment.

[0029] Specific resistance of film: The specific resistance value of each composition film shown in Table 1 is obtained by forming a single film (thickness of about 0.3 m) on a glass substrate by sputtering (the conditions are the same as above), After heat treatment at 300 ° C. for 30 minutes in a gas atmosphere, the measurement was performed with a four-terminal resistance measuring device.

[0030] Heat resistance at 350 ° C: The heat resistance of each composition film shown in Table 1 is that a single film (thickness of about 0.3 m) is formed on a glass substrate by sputtering (the conditions are the same as above), and nitrogen is added. The film surface was observed with a scanning electron microscope (SEM: 10,000 times) after heat treatment for 30 minutes at a temperature in the range of 100 ° C to 400 ° C in a gas atmosphere. In addition, in this SEM observation, 5 fields of observation range 10 m × 8 m were confirmed for each observation sample. The 350 ° C heat resistance was evaluated based on whether or not protrusions (hillocks) of sub / zm or more were observed on the observation surface in a heat treatment at 350 ° C for 30 minutes, or a depression (diameter 0) was observed on the observation surface. X was determined to be more than 3 dimple forces of 3 μm to 0.5 m). A dimple with no protrusions and no more than 3 dimples was marked as ◯.

[0031] ITO bonding property: This ITO bonding property is obtained by applying ITO (In O 10w on a glass substrate as shown in FIG.

2 3 t% SnO) electrode layer 40 (1000 A thickness, circuit width 10 m) is formed on each composition film layer 1

2

Evaluation was performed using a test sample (Kelvin element) formed to cross 0 (thickness of 2000 A, circuit width 10 μm). This test sample was heat-treated at 250 ° C. for 30 minutes in the air atmosphere, and then the terminal part force continuous energization (3 mA) in the arrow part of the test sample shown in FIG. The resistance measurement conditions at this time were so-called life acceleration test conditions in an air atmosphere of 85 ° C. Under these life acceleration test conditions, each test In the test sample, the time (failure time) when the resistance value changed to 100 or more times the initial resistance value at the start of measurement was examined. A test sample that was not broken under this accelerated life test condition for more than 250 hours was rated as ○. In addition, the test sample that failed in 250 hours or less under the accelerated life test condition was designated as evaluation X. As for the above-mentioned accelerated life test, JIS C 5003: 1974, reference literature (book title “Efficient method of accelerated acceleration test and its practicality”: edited by Yoji Kanuma, publisher, Japan Techno Center Co., Ltd.) )

[0032] IZO bondability: This IZO bondability is similar to the IZO bondability evaluation described above.

twenty three

7wt% ZnO: 1000A thickness, circuit width 50m) Test sample (Kelvin device) formed on the electrode layer 40 so that each A1 alloy film layer 10 (20000A thickness, circuit width 50μm) crosses ). The resistance of this test sample was measured under the same life acceleration test conditions as in the case of the ITO bondability, and IZO bondability was evaluated from the results of the life acceleration test. The evaluation criteria were the same as the ITO bondability.

[0033] As shown in Table 1, in the Al-Ni-B alloy wiring material of each Example relating to the present invention, the specific resistance value is 10 Ωcm or less, and Comparative Example 9 out of the composition range of the present invention is compared. In Example 11 and Comparative Example 12, the specific resistance value exceeded 10 Ωcm. In addition, as shown in Table 2, the Al-Ni-B alloy wiring material of each example has a Si diffusion heat resistance of 240 ° C or higher, and even at a high temperature of 330 ° C, A1 and Si There were some cases where no mutual diffusion was observed. As shown in Table 2, it was confirmed that the Al—Ni—B alloy wiring material of each example could be directly bonded to ITO and IZO transparent electrodes. It should be noted that the Si diffusion heat resistance of 240 ° C or higher is considered to be a practically sufficient characteristic considering that the thermal process applied when manufacturing the current TFT device is about 270 ° C. .

On the other hand, in Comparative Examples 1 to 3, it was confirmed that all the characteristics other than the specific resistance were practically insufficient. In Comparative Examples 4 and 5 of the Al-Ni alloy, the bonding characteristics with the transparent electrode are good, but the heat resistance and Si diffusion heat resistance are insufficient, and in Comparative Example 6 where the Ni content is high The film specific resistance exceeded 10 Ωcm. In the case of Comparative Examples 7 to 12 outside the composition range of the present invention, there are problems in direct bonding with ITO (Comparative Example 7), and the Si diffusion heat resistance is 200 ° C. or less (Comparative Example 8). , Comparative example 10), specific resistance The value exceeded Ωcm (Comparative Example 9, Comparative Example 11, Comparative Example 12), and it could not be said that the film characteristics were totally satisfactory. Further, in Comparative Example 13 containing silicon (Si) instead of nickel, the result was that the bonding property with the transparent electrode was poor due to the Si diffusion heat resistance. Furthermore, with the conventional A1—Ni—C alloy wiring materials proposed by the applicant (Comparative Example 14 and Comparative Example 15), although there is no problem in bonding with the transparent electrode, the heat resistance and Si diffusion heat resistance It was confirmed that the characteristics were insufficient.

Second Embodiment: In this second embodiment, the relationship between the heat resistance and the bonding characteristics of the semiconductor layer is examined in more detail with respect to the composition range of the A1-Ni—B alloy wiring material according to the present invention. The results will be described. Tables 3 to 5 show the results of examining the resistivity value of the film, the dimple generation rate, and the amount of change in the roughness of the semiconductor layer when the nickel content and boron content are varied! / Speak.

[0036] [Table 3]

[0037] [Table 4] / v: / O / -69SSS00ifcl £ s8 / -n900iAV ε_

[U [] ∞εοοs

Composition Roughness change Composition Roughness change

at% at%

Ni B 300 ^ 330 * C 350¾ Ni B 300¾ 330 "C 350¾

3.0 0.30 1.59 1.99 3.52 5.0 0.05 1.14 0.98 1.58

3.0 0.40 2.21 2.11 3.05 5.0 0.10 1.12 1.02 1.32

3.0 0.50 2.33 2.15 2.45 5.0 0.20 1.01 1.10 1.38

3.0 0.60 2.14 1.92 2.32 5.0 0.30 1.03 1.08 1.35

3.0 0.80 1.88 1.95 2.06 5.0 0.40 1.14 0.92 1.20

3.0 1.00 1.65 1.76 1.82 5.0 0.50 1.37 1.42 1.50

3.0 1.80 1.30 1.44 1.58 5.0 0.60 1.04 0.99 0.96

4.0 0.05 1.55 1.72 1.85 5.0 0.80 1.01 1.01 1.06

4.0 0.10 1.29 1.49 1.72 5.0 1.00 0.99 0.97 1.12

4.0 0.20 1.13 1.43 1.48 6.0 0.05 1.02 0.95 1.03

4.0 0.30 1.41 1.76 1.88 6.0 0.10 1.00 1.08 1.08

4.0 0.40 1.15 1.36 1.46 6.0 0.20 1.05 0.98 0.94

4.0 0.50 1.30 1.47 1.58 6.0 0.30 1.06 0.91 0.92

4.0 0.60 1.12 1.24 1.32 6.0 0.40 0.95 0.93 1.02

4.0 0.80 1.11 1.22 1.28 6.0 0.50 1.30 1.20 0.92

4.0 1.00 1.02 1.10 1.20 6.0 0.60 0.94 0.93 1.18

6.0 0.80 0.91 1.03 1.04

6.0 1.00 0.95 0.95 1.10

7.0 0.30 1.06 1.12 1.11

8.0 0.50 1.02 0.92 1.08

8.0 1.00 0.91 0.96 1.04

[0039] Table 3 shows the specific resistance value and dimple generation rate of the film in each composition. The measurement conditions of the specific resistance value of the film are the same as in the first embodiment. Further, the dimple generation rate is a result obtained by SEM observation of each evaluation sample with heat treatment temperatures of 350 ° C. and 400 ° C. under the same conditions as the heat resistance evaluation in the first embodiment. However, in the heat resistance evaluation in the second embodiment, the occurrence rate of dimples was examined in order to perform a more detailed heat resistance evaluation than the heat resistance evaluation in the first embodiment. The dimple occurrence rate is determined by detecting the dimples that are indentations (diameter: 0.3 μπ! To 0.5 m) on the observation surface, calculating the size and number of power that the dimples occupy. It is a value substituted for the area ratio obtained for the ratio to. The calculation of the dimple area was performed by approximating the hollow portion existing on the observation surface by image analysis and approximating the hollow portion to a circle. The dimple occurrence values shown in Table 3 are average values in 5 fields of observation range 10 μm X 8 m for each observation sample.

[0040] From the results of specific resistance values in Table 3, it was found that when nickel was 6.0 &% or less and boron was 0.80at% or less, 5 / XΩcm or less. The results of the dimple occurrence rate in Table 3 As can be seen from the graph, the higher the heat treatment temperature, the greater the incidence, and the more the nickel, the smaller the incidence. And when boron increases

, A tendency to increase the incidence of dimples was observed. From the results shown in Table 3, in order to reduce the dimple generation rate to 1.6% or less in a heat treatment at 350 ° C for 30 minutes, nickel is 4.0% or more and boron is 0.80at% or less. It turned out to be good.

[0041] Next, the results of the investigation of the occurrence of a deteriorated layer at the joint interface shown in Table 4 will be described.

In this altered layer investigation, an evaluation sample prepared under the same conditions as those of the Si diffusion heat resistance evaluation described in the first embodiment was used. Specifically, an n + -Si semiconductor layer (300 A) is formed on a glass substrate by CVD, and sputtering (magnetron sputtering device, input power 3. OWatt / cm ² , argon gas flow rate 100 ccm In this case, an Al—Ni—B alloy film (2000A) having each composition shown in Table 1 was formed under an argon pressure of 0.5 Pa). Then, this evaluation sample was heat-treated at 300, 330, and 350 ° C. for 30 minutes in a nitrogen gas atmosphere, and then the A1 formed on the upper layer using the phosphoric acid-based A1 etching solution described above. Only the alloy film was dissolved to expose the semiconductor layer. The exposed surface of the semiconductor layer was observed with an optical microscope (200 times magnification), and the presence of the altered portion that became a black spot shown in FIG. 3 or the discoloration or roughness of the surface of the semiconductor layer was confirmed. Table 4 evaluates the case where a large number of black spots were observed due to the interdiffusion between Si and A1. X, the presence of several black spots or the presence of black spots was not observed, and the observed surface was discolored or rough. Evaluate what was observed △, and evaluate that no discoloration or rough surface condition with no black spots on the observation surface was observed. It was.

[0042] Table 5 shows the results of examining the change in the surface state of the semiconductor layer in connection with the above-mentioned investigation of the deteriorated layer. This change in the surface state of the semiconductor layer was carried out by measuring the surface roughness of the semiconductor layer. Specifically, the surface roughness immediately after forming the n + -Si semiconductor layer (300A) on the glass substrate (hereinafter referred to as as-depo roughness) and the exposed semiconductor layer of the evaluation sample of the above-mentioned altered layer investigation The surface roughness (hereinafter referred to as direct bonding roughness) was measured, and (direct bonding roughness value) Z (as-depo roughness value) was calculated. In other words, the larger the numerical value of roughness change shown in Table 5, the more rough the surface state of the semiconductor layer after direct bonding and heat treatment. For measuring the surface roughness of the semiconductor layer, the step / surface roughness (roughness) ) · Ten-point average roughness R _Z was determined according to JIS B0601: 1994 using a fine shape measuring device (KLA Tencor, P-15 type).

[0043] From the results in Table 4, it was found that the more nickel, the more likely the generation of the altered layer was suppressed. Also, in the case of heat treatment of 330 ^o C, Niggenore force S4. Less than six. In Oat ^_0/0, Bo P linker 0.20 to 0. If it is 80at%, the generation of the altered layer is particularly suppressed There was found. In addition, when the Nikkenore force is 4.0 to 6. Oat% and the boron force is 0.30 to 0.50 at%, there is a tendency that a deteriorated layer does not occur even at a high temperature of 350 ° C. It was.

[0044] Then, it was found that the roughness change amount in Table 5 shows a tendency that is almost correlated with the result of the altered layer in Table 3. From the results of the roughness change in Table 5, even after heat treatment at 330 ° C after direct bonding, the bonding surface of the semiconductor layer does not become extremely rough, that is, within 1.5 times the as-depo roughness value. It was found that the composition range, which is the amount of change, is 4.0 to 6. Oat% for nickel and 0.20 to 0.60 at% for boron.

Industrial applicability

[0045] As described above, according to the present invention, even when a cap layer having a high melting point metal material such as Mo is omitted, it can be directly bonded to a transparent electrode such as ITO or IZO, and n + -Si of a thin film transistor can be used. It is possible to form a wiring circuit that can be directly bonded to the semiconductor layer. In particular, when a thermal process exceeding 240 ° C is applied, the mutual connection between A1 and Si occurs at the bonding interface where the wiring circuit and the semiconductor layer, which are the Al-Ni-B alloy wiring material of the present invention, are directly bonded. Diffusion is suppressed. In addition, the Al-Ni-B alloy wiring material according to the present invention has extremely good heat resistance, and its specific resistance is as low as 10 Ωcm or less, so it is extremely suitable as a constituent material for large display displays. It is. For this reason, the present invention relates to a material surface, equipment surface, and process in manufacturing a display device such as a liquid crystal display.

This is a technology that enables cost reduction and the realization of display devices with superior characteristics.

Claims

The scope of the claims

[1] A1—Ni—B alloy wiring material containing nickel and boron in aluminum, where the nickel content is nickel atomic percentage Xat%, and the boron content is boron atomic percentage Yat% , Formula

0. 5≤X≤10. 0

0. 05≤Y≤1 1.00

Υ + 0.25Χ≥1.00

Υ + 1.15Χ≤1 1.50

A to M—B alloy wiring material, characterized in that it is within the range of the area satisfying each of the formulas, and the balance is aluminum.

[2] The A1-Ni-B alloy wiring material according to claim 1, wherein the nickel content is 4.0% or more and the boron content is 0.80at% or less.

[3] The A1-Ni-B alloy wiring material according to claim 2, wherein the dimple generation rate generated on the surface of the wiring material after heat treatment at 350 ° C. for 1 hour is 1.6% or less.

[4] Nickel content is 4.0at% ～ 6.0 &%, boron content is 0.20at% ～ 0.80at

The A1-Ni-B alloy wiring material according to claim 1 to claim 3, wherein the wiring material is at least%.

[5] The Al—Ni—Β alloy wiring material according to claim 4, wherein the specific resistance value is 5. Ο μ Q cm or less.

[6] An element structure of a display device comprising a wiring circuit formed of the A1-Ni-B alloy wiring material according to any one of claims 1 to 5, a semiconductor layer, and a transparent electrode layer, An element structure of a display device, wherein the wiring circuit has a portion directly bonded to a semiconductor layer.

[7] An element structure of a display device comprising a wiring circuit formed of the A1-Ni-B alloy wiring material according to any one of claims 1 to 5, a semiconductor layer, and a transparent electrode layer, An element structure of a display device, wherein the wiring circuit has a portion directly bonded to a transparent electrode layer.

[8] An element structure of a display device comprising the element structure according to claim 6 and claim 7.

[9] The surface roughness value (Rz) of the surface of the semiconductor layer from which the directly bonded wiring circuit is peeled is 1.5 times or less of the surface roughness value (Rz) of the semiconductor layer surface after the semiconductor layer is formed. Item 6 or claim Item 9. The element structure of the display device according to Item 8.

[10] A sputtering target for forming a wiring circuit having the Al—Ni—B alloy wiring material force according to any one of claims 1 to 5,

If the nickel content is nickel atomic percentage Xat% and the boron content is boron atomic percentage Yat%, the formula

0. 5≤X≤10. 0

0. 05≤Y≤11.00

Υ + 0.25Χ≥1.00

Υ + 1. 15 Χ ≤ 11. 50

A sputtering target characterized by being in the range of a region satisfying each of the formulas above, with the balance being aluminum.