JP2007186779A - Al-Ni-B ALLOY WIRING MATERIAL, AND ELEMENT STRUCTURE USING THE SAME - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an Al-based alloy wiring material which, in a display device comprising a thin-film transistor and a transparent electrode layer, can be bonded directly to a transparent electrode layer such as ITO and IZO and also can be bonded directly to a semiconductor layer such as n<SP>+</SP>-Si. <P>SOLUTION: The Al-Ni-B alloy wiring material has a composition in which the nickel content and the boron content are within the ranges satisfying inequalities 0.5≤X≤10.0, 0.05≤Y≤11.0, Y+0.25X≥1.0 and Y+1.15X≤11.5 (wherein X represents the content of nickel in atomic percentage (at%) and Y represents the content of boron in atomic percentage (at%)) and the balance is composed of aluminum. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an Al-based alloy wiring material used for an element of a display device such as a liquid crystal display, and in particular, an Al-Ni-B alloy wiring material suitable for a display device including a thin film transistor and a transparent electrode, and an element using the same Concerning structure.

  2. Description of the Related Art In recent years, wiring materials made of aluminum (hereinafter sometimes simply referred to as “Al”)-based alloys are widely used as constituent materials in display devices such as thin-screen televisions typified by liquid crystal displays. This is because the specific resistance value of the Al-based alloy wiring material is low and the wiring process is easy.

For example, in the case of an active matrix type liquid crystal display, a thin film transistor (Thin Film Transistor, hereinafter abbreviated as TFT) as a switching element, a transparent electrode (hereinafter, referred to as Indium Tin Oxide), ITO (Indium Tin Oxide), or the like. An element is composed of a transparent circuit layer (sometimes referred to as a transparent electrode layer) and a wiring circuit formed from an Al-based alloy wiring material (hereinafter also referred to as a wiring circuit layer). In such an element structure, there are a portion where a wiring circuit made of an Al-based alloy wiring material is bonded to a transparent electrode and a portion where n ⁺ -Si (phosphorus-doped semiconductor layer) is bonded in the TFT.

In the Al-based alloy wiring material currently used, when configuring the element as described above, considering the influence of aluminum oxide formed in the Al-based alloy wiring material, between the wiring circuit and the transparent electrode, A refractory metal material such as molybdenum (Mo) or titanium (Ti) is formed as a so-called cap layer. In addition, in the junction between a semiconductor layer such as n ⁺ -Si and a wiring circuit, in order to prevent Al and Si from interdiffusion due to a thermal process during the manufacturing process, the semiconductor layer and the wiring circuit are not connected. In addition, a refractory metal material such as molybdenum (Mo) or titanium (Ti), which is the same as the cap layer, is interposed.

The above element structure will be specifically described with reference to FIG. FIG. 1 is a schematic cross-sectional view of an a-Si type TFT relating to a liquid crystal display. In this TFT structure, an electrode wiring circuit layer 2 made of an Al-based alloy wiring material constituting the gate electrode portion G and a cap layer 3 made of Mo, Mo—W, or the like are formed on the glass substrate 1. The gate electrode portion G is provided with a SiNx gate insulating film 4 as protection. On the gate insulating film 4, an a-Si semiconductor layer 5, a channel protective film layer 6, an n ⁺ -Si semiconductor layer 7, a cap layer 3, an electrode wiring circuit layer 2, and a cap layer 3 are sequentially deposited. A drain electrode portion D and a source electrode portion S are provided by appropriately forming a pattern. On the drain electrode portion D and the source electrode portion S, an element surface flattening resin or SiNx insulating film 4 ′ is coated. Further, on the source electrode portion S side, a contact hole CH is provided in the insulating layer 4 ′, and a transparent electrode layer 7 ′ of ITO or IZO is formed in that portion. In the case where an Al alloy wiring material is used for such an electrode wiring circuit layer 2, the transparent electrode layer 7 ′ and the electrode wiring layer 2 between the n ⁺ -Si semiconductor layer 7 and the electrode wiring layer 2 and in the contact hole CH The cap layer 3 is interposed between the two.

In the element structure shown in FIG. 1, since a cap layer of Mo or the like is formed, an increase in the cost of materials and manufacturing equipment is inevitable, and it has been pointed out that the manufacturing process is complicated. Therefore, the applicant of the present application has already proposed a technique that enables the omission of the cap layer in such a conventional element structure (see Patent Document 1). In this patent document 1, the wiring material of Al-C-Ni alloy and Al-C-Ni-Si alloy which can be directly joined with ITO was disclosed.
JP 2003-89864 A

However, the Al-based alloy wiring material disclosed in Patent Document 1 can be directly bonded to a transparent electrode layer such as ITO or IZO. However, when it is directly bonded to a semiconductor layer such as n ⁺ -Si. However, they did not have sufficiently satisfactory characteristics. For example, when a wiring circuit layer made of an Al-based alloy wiring material and a semiconductor layer are directly bonded, a diffusion phenomenon between Al and Si may occur at the bonding interface, and the bonding characteristics may not be satisfied.

More specifically, when the cap layer of the element structure shown in FIG. 1 is omitted, an Al-based alloy wiring material that satisfies the following characteristics is required. The electrode wiring circuit layer 2 of the gate electrode G in the element structure of FIG. 1 needs to be able to be directly bonded to a transparent electrode layer such as ITO at the lead wiring portion, although not shown in the drawing. It is required to satisfy heat resistance. The reason is that, when a gate insulating film formed on the gate electrode G is formed, a high-temperature thermal history is added, so that the electrode wiring circuit layer does not cause defects such as hillocks even at a temperature of 350 ° C. or higher. This is because a high heat resistance is required. Further, the electrode wiring circuit layer 2 of the drain electrode portion D and the source electrode portion S in the element structure of FIG. 1 can be directly bonded to a transparent electrode layer such as ITO, and a semiconductor such as n ⁺ -Si. It is required that direct bonding with the layer is possible. In direct bonding with a semiconductor layer such as n ⁺ -Si, it is necessary that a diffusion phenomenon between Al and Si does not occur even when a thermal history of 200 ° C. or higher is applied. The electrode wiring circuit layer 2 of the drain electrode portion D and the source electrode portion S is also required to have heat resistance that does not cause defects such as hillocks even when a thermal history of about 250 ° C. is applied. Furthermore, the Al-based alloy wiring material for forming the gate electrode portion G, drain electrode portion D, source electrode portion S, and other wiring portions naturally has a low specific resistance, that is, 10 μΩ · cm or less, preferably It is required to satisfy a specific resistance value of 5 μΩ · cm or less. That is, the present situation is that an Al-based alloy wiring material that satisfies all of the required characteristics is desired.

In addition, in the conventional Al-based alloy wiring material, deposits such as intermetallic compounds exist in the wiring circuit, and it is assumed that the presence of this deposit enables direct bonding to the transparent electrode layer (pixel electrode). (For example, refer to Patent Document 2). However, as far as the inventors of the present application know, it is not clear whether the precipitates in the wiring circuit formed from the Al-based alloy wiring material directly affect the bonding when in a dispersed state. Not in. Therefore, in order to realize more ideal direct bonding, it is the present situation that further phenomenon elucidation is required for the precipitates in the Al-based alloy wiring material.
JP 2004-214606 A

  And in the conventional Al type alloy wiring material, when forming a wiring circuit, it is known that the surface of the Al type alloy film formed by sputtering will be considerably roughened. In such a rough surface state, when a transparent electrode layer, a semiconductor layer, or the like is directly laminated on the Al-based alloy film, coverage by the laminated material cannot be satisfactorily performed, that is, the surface unevenness There is concern that it cannot be completely covered with the material laminated to the part. For this reason, further studies are required for a technique for smoothing the surface state of the Al-based alloy film forming the wiring circuit.

The present invention has been made in the background as described above, and in a display device including a thin film transistor and a transparent electrode layer, it can be directly bonded to a transparent electrode layer such as ITO or IZO, and n ⁺ − An Al-based alloy wiring material that can be directly bonded to a semiconductor layer such as Si is provided. In addition, regarding a display device element having a structure in which a wiring circuit layer formed of an Al-based alloy wiring material is directly bonded to a transparent electrode layer or a semiconductor layer, an increase in contact resistance value or a bonding failure when directly bonded. The present invention proposes an element structure of a display device that does not occur.

  The inventors of the present application have conducted intensive studies on Al-Ni alloys, and found that the above-mentioned problems can be solved by adding a predetermined amount of boron (B) to the Al-Ni alloy, leading to the present invention. It was.

In the present invention, in the Al-Ni-B alloy wiring material containing nickel and boron in aluminum, when the nickel content is the atomic percentage Xat% of nickel and the boron content is the atomic percentage Yat%,
Formula 0.5 ≦ X ≦ 10.0 (1)
0.05 ≦ Y ≦ 11.0 (2)
Y + 0.25X ≧ 1.0 (3)
Y + 1.15X ≦ 11.5 (4)
This is an Al—Ni—B alloy wiring material that is in the range of the region satisfying each of the formulas, with the balance being aluminum. The Al—Ni—B alloy wiring material in the present invention may be mixed in, for example, a material manufacturing process, a wiring circuit forming process, an element manufacturing process, or the like, without departing from the effects of the present invention described below. It does not prevent the mixing of certain gas components and other inevitable impurities.

  Nickel has an effect of forming an intermetallic compound with aluminum by heat treatment to improve the bonding characteristics in direct bonding with the transparent electrode layer. However, when the nickel content is increased, the specific resistance of the wiring circuit itself is increased and becomes impractical. Also, if the nickel content is low, the amount of intermetallic compound produced with aluminum decreases, making direct bonding to the transparent electrode layer impossible, and heat resistance (suppressing action against plastic deformation of Al-based alloy wiring materials due to heat) ) Also tends to decrease. Therefore, the nickel content needs to satisfy the above formula (1).

  Specifically, when the nickel content exceeds 10.0 at%, the specific resistance value of the wiring material becomes too large, and a dimple-like defect called dimple is easily formed on the surface of the wiring material, and heat resistance can be secured. There is a tendency to disappear. On the other hand, if it is less than 0.5 at%, a so-called hillock projection is likely to be formed on the surface of the wiring material, and the heat resistance tends not to be ensured. This dimple is a micro-dent defect formed on the surface of the material due to stress strain generated when heat treating Al-based alloy wiring material. When this dimple is generated, it adversely affects the bonding characteristics and Reliability decreases. On the other hand, hillocks, contrary to dimples, are protrusions that are formed on the material surface due to stress strain generated when heat treating Al-based alloy wiring material. Even if hillocks occur, the bonding characteristics are adversely affected. And the bonding reliability is lowered. These dimples and hillocks are common in that they are plastic deformation of the Al-based alloy wiring material due to heat, and are collectively referred to as a stress migration phenomenon. Heat resistance can be judged.

And, when boron is contained in aluminum in addition to nickel as in the present invention, the interdiffusion between Al and Si at the bonding interface is effective when directly bonded to a semiconductor layer such as n ⁺ -Si. It has the effect of preventing. Moreover, this boron acts on heat resistance similarly to nickel. If the boron content exceeds 11.00 at%, the specific resistance of the wiring circuit itself becomes high and becomes impractical. On the other hand, when the content is less than 0.05 at%, the ability to prevent mutual diffusion between Al and Si is lowered, and direct bonding with the semiconductor layer is not possible. Specifically, when a semiconductor layer and an Al—Ni—B alloy wiring material are directly bonded and heat-treated at a predetermined temperature, mutual diffusion between Al and Si is likely to occur at the bonded portion. In addition, dimples tend to occur easily. Therefore, the boron content needs to satisfy the formula (2).

  In addition, the inventors of the present application are the case where the semiconductor layer is directly bonded, and even in a thermal process at a temperature exceeding 240 ° C., in order to reliably prevent the mutual diffusion of Al and Si at the bonding interface, It has been found that the above formula (3) needs to be satisfied. And in order to maintain reliably the specific resistance of Al-Ni-B alloy wiring material itself to 10 microhm-cm or less, it discovered that it was necessary to satisfy said (4) Formula.

  Further, in the range satisfying the above formulas (1) to (4), when the nickel content is 4.0 at% or more and the boron content is 0.80 at% or less, the above-described dimple generation is suppressed as much as possible. The resulting Al—Ni—B alloy wiring material can improve the bonding reliability when directly bonding the semiconductor layer and the transparent electrode layer. More specifically, when heat treatment is performed at 350 ° C. for 30 minutes, the dimple generation rate generated on the surface of the Al—Ni—B alloy wiring material can be suppressed to 1.6% or less, which is more preferable. .

  As described above, the dimple is a microscopic defect formed on the surface of the wiring material when the Al—Ni—B alloy wiring material is heat-treated. After performing a predetermined heat treatment on the wiring material, the surface of the material was observed, and the generated dimples (0.3 to 0.5 μm) were examined. In this dimple investigation, the area of all the dimples generated in the observation visual field was obtained, and the area ratio of the dimples in the observation visual field was used as the dimple generation rate. As a result, the heat resistance characteristics of the wiring material were investigated. When the nickel content is 4.0 at% or more and the boron content is 0.80 at% or less in the range satisfying the formula, even when heat treatment is performed at 350 ° C. for 30 minutes, the dimple generation rate is reduced. It has been found that it can be suppressed to 1.6% or less. It is desirable that this dimple is not generated as much as possible. If this dimple generation rate is low, even if it passes through the thermal process in the device manufacturing process of the display device, it is at the bonding interface directly bonded to the semiconductor layer or the transparent electrode layer. Further, it becomes difficult to generate a bonding defect and the like, and the bonding reliability is improved. Further, when the dimple occurrence rate is suppressed to 1.6% or less, for example, the on / off ratio (on / off ratio) in a TFT having a structure directly bonded to a semiconductor layer is stabilized, and connection reliability is improved. Is thought to improve. The Al—Ni—B alloy wiring material according to the present invention is suitable for direct bonding to a semiconductor layer or a transparent electrode layer. For example, a cap made of a refractory metal material such as Mo on the semiconductor layer side. This does not prevent application in an element structure provided with layers. Furthermore, in addition to the use for direct bonding with the semiconductor layer and the transparent electrode layer described above, the Al—Ni—B alloy wiring material according to the present invention according to the present invention can be applied as a so-called reflective film.

  Further, the inventors of the present application have a nickel content of 4.0 at% to 6.0 at% and a boron content of 0.20 at% to 0.00 in the range satisfying the above formulas (1) to (4). It has been found that when it is 80 at%, it becomes a particularly suitable Al—Ni—B alloy wiring material when directly bonding to the semiconductor layer.

  It is known that when a wiring circuit layer made of an Al-based alloy wiring material and a semiconductor layer are directly bonded, a diffusion phenomenon between Al and Si occurs at the bonding interface. As a result, a phenomenon in which a deteriorated layer is formed at the bonding interface when directly bonded is confirmed by the influence of the mutual diffusion. This altered layer refers to a semiconductor layer formed by directly bonding an Al-based alloy wiring material and a semiconductor layer, applying a predetermined heat treatment, peeling off the Al-based alloy wiring material, and observing the surface of the semiconductor layer. This refers to an altered portion that is a black spot recognized on the surface, or a state such as discoloration or roughness of the surface of the semiconductor layer (in this specification, the surface of the semiconductor layer is referred to as an altered layer). This deteriorated layer tends to be generated more easily as the heat treatment temperature becomes higher, and it is preferable that the deteriorated layer is not generated by heat treatment (30 minutes) at 200 ° C. or higher. Further, in consideration of the thermal history applied when forming the insulating layer by CVD, it is desirable that a deteriorated layer does not occur even in a high temperature range of 240 ° C. to 300 ° C. Further, the manufacturing in which each thermal history is added in the device manufacturing process In order to provide a margin for the application range of conditions, it is considered desirable to suppress the generation of a deteriorated layer at 330 ° C. or higher. Therefore, as a result of examining a composition range in which such a deteriorated layer does not occur, the nickel content is 4.0 at% to 6.0 at% in the range satisfying the above formulas (1) to (4), and boron is contained. When the amount was 0.20 at% to 0.80 at%, it was found that the formation of the deteriorated layer was suppressed even in heat treatment at 330 ° C. for 30 minutes. In this composition range, the specific resistance value of the wiring material itself is 5 μΩcm or less. In other words, in such a composition range, as described above, the generation of dimples is extremely suppressed and the specific resistance value is low. Therefore, an Al—Ni—B alloy for realizing direct bonding with the semiconductor layer. As a wiring material, it is very suitable for practical use.

  Further, the inventors of the present application investigated the change in the surface state of the semiconductor layer. In this investigation, the surface roughness Rz (10-point average roughness, JIS B0601: 1994) of the semiconductor layer exposed by peeling and exposing the Al-based alloy wiring material after direct bonding and heat treatment, and the semiconductor before direct bonding This was done by comparing the layer surface roughness Rz. From the investigation results of the surface state change, the Al alloy wiring material of the present invention has a nickel content of 4.0 at% to 6.0 at% within the range satisfying the above formulas (1) to (4). When the content is in the composition range of 0.20 at% to 0.80 at%, when the semiconductor layer surface roughness value before direct bonding is 1, the semiconductor layer surface roughness exposed after direct bonding and heat treatment It was further found out that the value can be changed by a factor of 1.5 or less.

  Although it is not clear whether the amount of change in the surface roughness of the semiconductor layer is a parameter directly related to the interdiffusion between Si and Al, the amount of change increases as the heat treatment temperature increases. Has been confirmed. In addition, the change in the surface state of the semiconductor layer is expected to affect the switching characteristics of the TFT. That is, it is presumed that this leads to a change in the on-off ratio (on / off ratio) in the TFT, and the surface state of the semiconductor layer does not change so much even if heat treatment is performed with direct bonding to the semiconductor layer. It is expected that the switching characteristics of the transistor can be maintained well. Therefore, when the surface roughness Rz of the semiconductor layer exposed by peeling off the Al-based alloy wiring material after direct bonding and heat treatment is 1 when the surface roughness value of the semiconductor layer before direct bonding is 1, direct bonding is performed. It is considered that the connection reliability considering the switching characteristics of the TFT can be sufficiently ensured that the amount of change is 1.5 times or less of the previous semiconductor layer surface roughness value. In the present invention, regarding the surface state change of the semiconductor layer in the direct bonding, the surface roughness Rz is adopted when specifying the surface state, but the surface property parameter described in JIS B0601 etc., for example, Parameters such as surface roughness Ra (arithmetic average roughness) can also be employed.

  Then, the inventors of the present application relate to an element structure of a display device having a structure in which an Al-based alloy wiring material is directly bonded to a transparent electrode layer or a semiconductor layer, resulting in an increase in contact resistance or a bonding failure when directly bonded. As a factor to make the surface roughness Ra of the Al-based alloy film, Al was formed by the Al—Ni—B alloy wiring material constituting the wiring circuit directly bonded to the semiconductor layer and / or the transparent electrode layer. It has been found that the surface roughness Ra of the Ni-B alloy film is desirably 2.0 to 20.0. When the surface roughness Ra of the Al—Ni—B alloy film formed of the Al-based alloy wiring material of the present invention is less than 2.0 mm, the bonding strength is lowered when the transparent electrode layer is directly bonded. It was recognized that when the value exceeds 20.0 mm, the tendency of increasing the contact resistance value becomes remarkable. The surface roughness Ra is the surface roughness of the Al—Ni—B alloy film after film formation. Depending on the manufacturing method of the display device, the deposited Al—Ni—B alloy film has a structure in which a semiconductor layer is further formed in the case of a staggered structure or a transparent electrode layer is formed in the case of an inverted staggered structure. The surface roughness Ra is obtained by performing non-contact measurement with an atomic force microscope (AFM) and calculating Ra according to JIS B0601-1982.

  Regarding the Al—Ni—B alloy film formed of the Al—Ni—B alloy wiring material of the present invention, it is desirable that the film thickness is 1000 to 3000 mm. If the Al—Ni—B alloy film thickness is less than 1000 mm, it is difficult to satisfy the practical level of the effective resistance when the wiring circuit is formed. This is because the coverage of the upper layer to be laminated becomes non-uniform, and it tends to be difficult to form a practical element structure.

  In addition, according to the study by the inventors of the present application, in the wiring circuit layer formed of the Al—Ni—B alloy wiring material of the present invention, precipitates that are dispersed and precipitated in the wiring circuit layer when the element is configured are present. It was found that the particles were uniformly dispersed without segregation.

  In the research by the inventors of the present application, it has been confirmed that a compound that precipitates in a wiring circuit, that is, a so-called intermetallic compound tends to segregate in a specific composition of an Al-based alloy wiring material that has been proposed conventionally. For example, in the Al—Ni—Nd alloy wiring material containing Nd disclosed in Patent Document 2, precipitates in the wiring circuit layer tend to segregate due to the heat treatment when the element is formed (FIG. 5). reference).

  Thus, when segregation of precipitates occurs in the wiring circuit layer, there is a concern that the bonding characteristics in direct bonding may not be improved depending on the bonding position with the wiring circuit layer. In other words, since the intermetallic compound precipitated in the wiring circuit layer affects the bonding resistance in direct bonding, the transparent electrode layer and the semiconductor layer are directly bonded to the segregated portion of the wiring circuit layer. In the case of being directly joined to a portion without segregation, the joining characteristics are different. In addition, when a wiring circuit is formed by etching a thin film formed with an Al-based alloy wiring material, a wiring circuit having an appropriate shape cannot be formed due to a difference in etching rate between a segregated portion and a non-segregated portion. It also happens.

  On the other hand, in the wiring circuit layer formed of the Al—Ni—B alloy wiring material of the present invention, the Ni compound is dispersed and deposited when the element is configured, and this Ni compound has a wiring circuit layer thickness in the section of the wiring circuit layer. On the line segment orthogonal to the direction, the existence ratio is 25% to 45% in the thickness direction of the wiring circuit layer. That is, the Ni compound does not tend to segregate over the entire thickness of the wiring circuit layer (see FIG. 6). Therefore, unlike the Al-Ni-Nd alloy wiring material described above, it is not necessary to specify a place where the transparent electrode layer or the semiconductor layer is directly joined, and a wiring circuit having an appropriate circuit shape can be reliably formed by etching. It becomes.

The Ni compound dispersed and precipitated in the wiring circuit layer formed of the Al—Ni—B alloy wiring material according to the present invention is mainly an Al ₃ Ni phase intermetallic compound. As a result of investigating the Ni compound by the present inventors, when the surface of the wiring circuit is observed with a scanning electron microscope (SEM), those having a size of 20 nm to 160 nm exist, and the average particle size in each observation field is 80 nm to It was confirmed to be 140 nm. Moreover, the area ratio which the Ni compound occupies the observation visual field was 5 to 20%, and the density of the Ni compound was 1000/100 μm ^{2 to} 5000/100 μm ² . Further, when the cross section of the wiring circuit layer is observed with a transmission electron microscope (TEM), the Ni compound has a diameter of 10% to 80% with respect to the wiring circuit layer thickness of 200 nm. The distance was 10 nm to 150 nm.

  In the case of manufacturing a display device using the Al—Ni—B alloy wiring material according to the present invention described above, the nickel content is set to an atomic percentage Xat% of nickel, and the boron content is set to an atomic percentage Yat% of boron. In this case, it is preferable to use a sputtering target that is in the range of the region satisfying each of the formulas (1) to (4) and the balance is aluminum. In particular, among the ranges satisfying the above formulas (1) to (4), a sputtering target having a nickel content of 4.0 at% to 6.0 at% and a boron content of 0.20 at% to 0.80 at%. Then, it is possible to easily realize a wiring circuit that is extremely suitable for direct bonding with the semiconductor layer. When a sputtering target having such a composition is used, an Al—Ni—B alloy thin film having almost the same composition as the target composition can be easily formed, although it may be somewhat affected by the film forming conditions during sputtering.

  In addition, although it is practically desirable to form the Al—Ni—B alloy wiring material according to the present invention by sputtering as described above, other different methods may be adopted. For example, a dry method such as a vapor deposition method or a spray homing method may be used. An alloy particle made of the Al—Ni—B alloy composition of the present invention is used as a wiring material, and a wiring circuit is formed by an aerosol deposition method. For example, a wiring circuit may be formed by a method.

As described above, according to the present invention, even if a cap layer made of a refractory metal material such as Mo is omitted, it can be directly bonded to a transparent electrode layer such as ITO or IZO, and n ⁺ -Si of a thin film transistor can be used. A wiring circuit that can be directly bonded to the semiconductor layer can be formed. In particular, when a thermal process exceeding 240 ° C. is applied, the interdiffusion between Al and Si is suppressed at the bonding interface where the wiring circuit made of the Al—Ni—B alloy wiring material of the present invention and the semiconductor layer are directly bonded. Is done.

  In addition, since the Al—Ni—B alloy wiring material according to the present invention has extremely good heat resistance and a specific resistance as low as 10 μΩcm or less, it is extremely suitable as a constituent material for a display with a large screen. For this reason, the present invention makes it possible to reduce costs in all aspects of materials, facilities, and processes in the production of display devices such as liquid crystal displays, and to realize a display device with excellent characteristics. Technology.

  Hereinafter, the best embodiment of the present invention will be described.

First Embodiment: In this embodiment, films were formed by sputtering on Al—Ni—B alloy wiring materials having the compositions shown in Table 1 and the comparative examples, and the characteristics of the films were evaluated. The sputtering target was prepared by mixing the metals having the compositions shown in Table 1 with aluminum, dissolving and stirring in vacuum, casting in an inert gas atmosphere, rolling the obtained ingot, and molding the resulting ingot. A surface produced by processing the surface to be sputtered was used. The characteristics of the film in each composition shown in Table 1 are as follows: Si diffusion heat resistance when directly bonded to the semiconductor layer, specific resistance of the film, 350 ° C. heat resistance of the film, ITO bondability when directly bonded to the transparent electrode layer And IZO bondability. The results are shown in Tables 1 and 2.

The measurement conditions for each characteristic evaluation will be described below.
Si diffusion heat resistance: As an evaluation sample of this characteristic, an n ⁺ -Si semiconductor layer (300 Å) was formed on a glass substrate by CVD, and sputtering (magnetron sputtering apparatus, input power 3.0 Watt / What formed each composition film | membrane (2000 kg) shown in Table 1 by cm < ² >, argon gas flow rate 100sccm, argon pressure 0.5Pa) was used. And after setting the heat processing temperature for every 10 degreeC in the temperature range of 150-350 degreeC and performing the heat processing for 30 minutes in nitrogen gas atmosphere for an evaluation sample, phosphoric acid type Al etching liquid (made by Kanto Chemical Co., Inc.) , By dissolving for 10 minutes in an Al mixed acid etchant / composition (volume ratio) phosphoric acid: succinic acid: acetic acid: water = 16: 1: 2: 1) at a liquid temperature of 32 ° C., only each composition film formed in the upper layer is dissolved. Then, the semiconductor layer was exposed. The exposed surface of the semiconductor layer was observed with an optical microscope (200 times) to examine whether mutual diffusion between Si and Al occurred.

  2 and 3 show typical optical micrographs on the exposed semiconductor layer surface. FIG. 2 shows the surface of the semiconductor layer where no interdiffusion is observed, and FIG. 3 shows the traces of interdiffusion (black spots in the photograph). As for the Si diffusion heat resistance, a sample with black spots as shown in FIG. 3 is regarded as defective, and among the samples where no mutual diffusion is recognized as shown in FIG. 2, the highest heat treatment temperature value is evaluated for Si diffusion heat resistance. The index values are shown in Table 2.

Specific resistance of film: The specific resistance value of each composition film described in Table 1 is as follows: a single film (thickness of about 0.3 μm) is formed on a glass substrate by sputtering (the conditions are the same as above), and 300 in a nitrogen gas atmosphere. After performing a heat treatment at 30 ° C. for 30 minutes, the measurement was performed with a four-terminal resistance measuring device.

Heat resistance at 350 ° C .: The heat resistance of each composition film shown in Table 1 is as follows: a single film (thickness of about 0.3 μm) is formed on a glass substrate by sputtering (the conditions are the same as above), and 100 ° C. in a nitrogen gas atmosphere. After heat treatment for 30 minutes at a temperature in the range of ˜400 ° C., the film surface was observed with a scanning electron microscope (SEM: 10,000 times). Moreover, this SEM observation was made to confirm five visual fields of observation range 10 micrometers x 8 micrometers about each observation sample. The heat resistance at 350 ° C. was evaluated by confirming that projections (hillocks) having a diameter of 0.1 μm or more were observed on the observation surface in a heat treatment at 350 ° C. for 30 minutes, or a depression-like portion (diameter 0.3 μm in the observation surface). A case where 4 or more dimples having a diameter of ~ 0.5 μm were confirmed was rated as x. A sample having no protrusions and having 3 or less dimples was marked as ◯.

ITO bondability: The ITO bondability form a _{ITO (In 2 O 3 -10wt%} SnO 2) electrode layer (1000 Å thick, circuit width 10 [mu] m) on a glass substrate as shown in the schematic perspective view of FIG. 4, It evaluated using the test sample (Kelvin element) formed so that each composition film layer (2000-thickness, circuit width 10micrometer) might be crossed on it.

  For the production of this test sample, first, an Al-based alloy film having a thickness of 2000 mm was formed on a glass substrate under the sputtering conditions using each Al-based alloy target having the above composition. The substrate temperature during sputtering at this time was set as shown in Table 6 to perform each film formation. Then, the surface of each Al-based alloy film is coated with a resist (OFPR800: Tokyo Ohka Kogyo Co., Ltd.), a pattern film for forming a 10 μm wide circuit is disposed and exposed to light, and the concentration is 2.38% and the liquid temperature is 23 ° C. The film was developed with an alkali developer containing tetramethylammonium hydroxide (hereinafter abbreviated as TMAH developer). After the development process, circuit formation is performed with a phosphoric acid mixed acid etching solution (manufactured by Kanto Chemical Co., Inc.), and the resist is removed with a dimethyl sulfoxide (hereinafter abbreviated as DMSO) stripping solution. An alloy film circuit was formed.

Then, the substrate on which the 10 μm wide Al-based alloy film circuit was formed was subjected to pure water cleaning and drying treatment, and an SiNx insulating layer (thickness 4200 mm) was formed on the surface. This insulating layer was formed using a sputtering apparatus under sputtering conditions of an input power of RF 3.0 Watt / cm ² , an argon gas flow rate of 90 sccm, a nitrogen gas flow rate of 10 sccm, a pressure of 0.5 Pa, and a substrate temperature of 300 ° C.

Subsequently, a positive resist (manufactured by Tokyo Ohka Kogyo Co., Ltd .: TFR-970) is coated on the surface of the insulating layer, a 10 μm × 10 μm square pattern film for opening a contact hole is placed, exposed, and subjected to TMAH development. Development processing was performed with the solution. Then, a contact hole was formed using a dry etching gas of CF ₄ . The contact hole formation conditions were a CF ₄ gas flow rate of 50 sccm, an oxygen gas flow rate of 5 sccm, a pressure of 4.0 Pa, and an output of 150 W.

The resist was stripped with the DMSO stripper described above. And after removing residual peeling liquid using isopropyl alcohol, it washed with water and performed the drying process. An ITO transparent electrode layer was formed in and around the contact hole by using an ITO target (composition In ₂ O ₃ -10 wt% SnO ₂ ) for each sample after the resist peeling process was completed. The transparent electrode layer is formed by sputtering (substrate temperature 70 ° C., input power 1.8 Watt / cm ² , argon gas flow rate 80 sccm, oxygen gas flow rate 0.7 sccm, pressure 0.37 Pa) to form an ITO film having a thickness of 1000 mm. did.

  The ITO film surface is coated with a resist (manufactured by Tokyo Ohka Kogyo Co., Ltd .: OFPR800), a pattern film is placed and exposed, developed with a TMAH developer, and an oxalic acid mixed acid etchant (Kanto). A 10 μm-wide circuit was formed by using Chemical Industries, Ltd. (ITO05N). After forming the ITO film circuit, the resist was removed with a DMSO stripping solution.

  Each test sample obtained by the manufacturing method as described above is subjected to a heat treatment at 250 ° C. for 30 minutes in an air atmosphere, and then continuous energization (3 mA) is performed from the terminal portion indicated by the arrow in the test sample shown in FIG. And measured the resistance. The resistance measurement conditions at this time were so-called life acceleration test conditions in an air atmosphere at 85 ° C. Then, under this life acceleration test condition, the time (failure time) during which each test sample changed to a resistance value 100 times or more the initial resistance value at the start of measurement was examined. A test sample that did not fail even after 250 hours under this accelerated life test condition was rated as “Good”. A test sample that failed in 250 hours or less under the life acceleration test condition was evaluated as x. In addition, about the above-mentioned life acceleration test, JIS C 5003: 1974, reference literature (book name "Efficient method of the reliability acceleration test and its practice": edited by Yoji Kanuma, publisher, Japan Techno Center Co., Ltd.) Is compliant.

IZO bondability: This IZO bondability is the same as that of the IZO bondability evaluation described above, and each Al-based alloy film is formed on an IZO (In ₂ O ₃ −10.7 wt% ZnO: 1000Å thickness, circuit width 50 μm) electrode layer. Evaluation was performed using a test sample (Kelvin device) formed so as to cross the layer (thickness of 2000 mm, circuit width 50 μm). The test sample was prepared under the same conditions as the ITO bondability. The resistance of this test sample was measured under the same life acceleration test conditions as in the case of the ITO bondability, and IZO bondability was evaluated from the results of the life acceleration test. The evaluation criteria were also the same as the ITO bondability.

  As shown in Table 1, in the Al—Ni—B alloy wiring material of each example relating to the present invention, the specific resistance value is 10 μΩcm or less, and Comparative Example 9, Comparative Example 11, and Comparative Example that deviate from the composition range of the present invention About 12, it was a specific resistance value exceeding 10 μΩcm. Further, as shown in Table 2, in the Al—Ni—B alloy wiring material of each example, the Si diffusion heat resistance is 240 ° C. or higher, and even at a high temperature of 330 ° C., mutual diffusion of Al and Si at the bonding interface. There was something that could not be recognized. As shown in Table 2, it was confirmed that the Al—Ni—B alloy wiring material of each example can be directly bonded to the ITO and IZO transparent electrode layers. In addition, it is desirable that this Si diffusion heat resistance is not practically generated by heat treatment at 200 ° C. or higher. Considering the thermal history applied when forming an insulating layer by CVD, the heat treatment is also altered in a high temperature range of 240 ° C. to 300 ° C. It is desirable that no layer occurs. Furthermore, it is desirable to have Si diffusion heat resistance at 330 ° C. or higher in order to provide a sufficient range of application of manufacturing conditions to which each thermal history is applied in the device manufacturing process.

  On the other hand, in Comparative Examples 1 to 3, it was confirmed that all the characteristics other than the specific resistance were practically insufficient. In Comparative Examples 4 and 5 of the Al—Ni alloy, although the bonding characteristics with the transparent electrode layer are good, the characteristics are insufficient in heat resistance and Si diffusion heat resistance, and Comparative Example 6 having a high Ni content. Then, the film specific resistance exceeded 10 μΩcm. In the case of Comparative Examples 7 to 12 outside the composition range of the present invention, there is a problem in direct bonding with ITO (Comparative Example 7), or the Si diffusion heat resistance is 200 ° C. or less (Comparative Example 8, Comparative Example 10), the specific resistance value exceeded 10 μΩcm (Comparative Example 9, Comparative Example 11, Comparative Example 12), and it could not be said that the film characteristics were totally satisfactory. Further, in Comparative Example 13 containing silicon (Si) instead of nickel, not only the Si diffusion heat resistance but also the bonding property with the transparent electrode layer was deteriorated. Furthermore, the conventional Al—Ni—C alloy wiring materials proposed by the applicant of the present application (Comparative Example 14 and Comparative Example 15) have no problem in the heat resistance and Si diffusion heat resistance, although there is no problem in the bondability with the transparent electrode layer. It was confirmed that the characteristics were sufficient.

Second Embodiment: In the second embodiment, the composition range of the Al—Ni—B alloy wiring material according to the present invention is the result of examining the relationship between the heat resistance of the film and the bonding characteristics of the semiconductor layer in more detail. Will be described. Tables 3 to 5 show the specific resistance value of the film when the nickel content and boron content are changed, the dimple generation rate of the film, the occurrence of the altered layer when directly bonded to the semiconductor layer, and the semiconductor layer. The result of investigating the surface roughness variation is shown.

  Table 3 shows the specific resistance value and dimple generation rate of the film in each composition. The measurement conditions of the specific resistance value of the film are the same as in the first embodiment. Further, the dimple generation rate is a result obtained by SEM observation of each evaluation sample having heat treatment temperatures of 350 ° C. and 400 ° C. under the same conditions as the heat resistance evaluation in the first embodiment. However, in the heat resistance evaluation in the second embodiment, the occurrence rate of dimples was examined in order to conduct a more detailed examination than the heat resistance evaluation in the first embodiment. The dimple occurrence rate is obtained by detecting dimples having a hollow portion (diameter: 0.3 μm to 0.5 μm) on the observation surface, calculating the area occupied by the dimples from the size and number of the dimples, and determining the ratio to the observation area. It is a value substituted by the area ratio. The calculation of the dimple area was performed by binarizing a hollow portion existing on the observation surface by image analysis and approximating the hollow portion to a circle. The depth of this dimple was about 100 mm when several dimples were measured. Moreover, the value of the dimple occurrence rate shown in Table 3 indicates an average value in five visual fields in the observation range of 10 μm × 8 μm for each observation sample.

  From the results of specific resistance values in Table 3, it was found that when nickel was 6.0 at% or less and boron was 0.80 at% or less, the value was 5 μΩcm or less. Further, as can be seen from the results of the dimple generation rate in Table 3, the higher the heat treatment temperature, the higher the generation rate, and the more nickel, the lower the generation rate. As boron was increased, the dimple generation rate tended to increase. From the results in Table 3, in order to reduce the dimple generation rate to 1.6% or less in a heat treatment at 350 ° C. for 30 minutes, nickel is 4.0 at% or more and boron is 0.80 at% or less. It turned out to be good.

Next, the results of the investigation on the occurrence of a deteriorated layer at the joint interface shown in Table 4 will be described. In this deteriorated layer investigation, an evaluation sample created under the same conditions as the Si diffusion heat resistance evaluation described in the first embodiment was used. Specifically, an n ⁺ -Si semiconductor layer (300 （) is formed on a glass substrate by CVD, and sputtering (magnetron sputtering apparatus, input power 3.0 Watt / cm ² , argon gas flow rate 100 sccm, Argon pressure of 0.5 Pa was used to form an Al—Ni—B alloy film (2000 kg) having each composition shown in Table 4. And after performing heat processing for 30 minutes in nitrogen gas atmosphere at each temperature of 300, 330, and 350 ° C. for this evaluation sample, an Al-based alloy film formed as an upper layer using the phosphoric acid-based Al etching solution described above Only the semiconductor layer was dissolved to expose the semiconductor layer. The exposed surface of the semiconductor layer was observed with an optical microscope (200 times), and the presence of a denatured portion that became a black spot shown in FIG. 3 or the discoloration or roughness of the surface of the semiconductor layer was confirmed. Table 4 evaluates the case where a large number of black spots were observed due to the mutual diffusion of Si and Al. X The presence of several or fewer black spots or no black spots were observed, and discoloration of the observation surface or a rough state was observed. The evaluation was evaluated as Δ, and the observation surface had no black spots, and no discoloration or rough surface condition was observed as evaluation ○.

Table 5 shows the result of examining the surface state change of the semiconductor layer in accordance with the above-mentioned deteriorated layer investigation. The change in the surface state of the semiconductor layer was performed by measuring the surface roughness of the semiconductor layer. Specifically, the surface roughness immediately after forming the n ⁺ -Si semiconductor layer (300 し た) on the glass substrate (hereinafter referred to as as-depo roughness), and the exposed semiconductor layer of the evaluation sample of the altered layer investigation The surface roughness (hereinafter referred to as direct bonding roughness) was measured, and (direct bonding roughness value) / (as-depo roughness value) was calculated. That is, the larger the numerical value of the roughness variation shown in Table 5 is, the more rough the surface state of the semiconductor layer after direct bonding and heat treatment is. For measuring the surface roughness of the semiconductor layer, a ten-point average roughness according to JIS B0601: 1994 was used using a step, surface roughness (roughness), and fine shape measuring device (KLA Tencor, Inc .: P-15 type). Rz was determined.

  From the result of Table 4, the tendency which can suppress generation | occurrence | production of a deteriorated layer was recognized, so that nickel increased. In addition, in the case of heat treatment at 330 ° C., it has been found that the generation of a deteriorated layer is particularly suppressed when nickel is 4.0 to 6.0 at% and boron is 0.20 to 0.80 at%. Further, when nickel was 4.0 to 6.0 at% and boron was 0.30 to 0.50 at%, there was a tendency that the deteriorated layer did not occur even at a high temperature of 350 ° C.

  And it turned out that about the roughness variation | change_quantity of Table 5, the tendency substantially correlated with the result of the deteriorated layer of Table 3 was shown. From the results of the roughness change in Table 5, even after heat treatment at 330 ° C. after direct bonding, the bonding surface of the semiconductor layer does not become extremely rough, that is, within 1.5 times the as-depo roughness value. It was found that the composition range as the change amount was 4.0 to 6.0 at% for nickel and 0.20 to 0.60 at% for boron.

Third Embodiment: In this third embodiment, the investigation results of the surface roughness when a film is formed by sputtering will be described. In this third embodiment, among the Al—Ni—B alloy wiring materials according to the present invention, an Al—Ni—B alloy film having a composition of Al—5.0 at% Ni—0.4 at% B (Example 15) and A pure Al film for comparison (referred to as Comparative Example 1 as in the first embodiment) and an Al-2.0 at% Nd alloy film (Comparative Example 16) were investigated.

First, the film formation conditions for Example 15, Comparative Example 1, and Comparative Example 16 were as follows: sputtering conditions, input power 3 using each Al-based alloy target having the above composition on a glass substrate (manufactured by Corning: # 1737). Each alloy film having a thickness of 2000 mm was formed using a magnetron sputtering apparatus (manufactured by Tokki Co., Ltd .: multi-chamber type sputtering apparatus MSL464) at 0.0 Watt / cm ² , an argon gas flow rate of 100 sccm, and an argon pressure of 0.5 Pa. The substrate temperature during sputtering was set as shown in Table 6 to form a film.

  And the surface roughness Ra of each alloy film shown in Table 6 was measured. For the surface roughness measurement, an arithmetic average roughness Ra (JIS B0601-1982) was determined using an atomic force microscope (Seiko Instruments Co., Ltd .: SPI-3800N). Moreover, this measurement measured five places on each alloy film surface, and computed the average value. The results are shown in Table 6. In Table 6, Examples 15-1 to 3 show the results of an Al-5.0 at% Ni-0.4 at% B alloy film at a substrate temperature of 100 ° C. to 250 ° C. Further, in Table 6, the result of the Al 5.0 at% Ni-0.4 at% B alloy film at the substrate temperature of room temperature is referred to as Comparative Example 17, and Al-5.0 at% Ni-0.4 at at the substrate temperature of 300 ° C. The result of% B alloy film is shown as Comparative Example 18. Comparative Example 1 shows the result for a pure Al film, and Comparative Example 16 shows the result for an Al-2.0 at% Nd alloy film. In addition, the average surface roughness value (Ra) of the glass substrate surface was 1.8 mm.

  From the results in Table 6, it was confirmed that the surface roughness of the Al—Ni—B alloy film varies depending on the substrate temperature. In addition, the pure Al film of Comparative Example 1 was in a very rough surface state, and the Al-2.0 at% Nd alloy film of Comparative Example 16 was rough enough to exceed Ra 20 mm even when the substrate temperature was about 100 ° C. It was a surface condition.

  Next, the results of investigating the contact resistance value and the bonding strength in direct bonding with the transparent electrode layer will be described. First, contact resistance value measurement will be described. As described in the surface roughness measurement, an Al-based alloy film having a thickness of 2000 mm was formed on the glass substrate using the Al-based alloy target having the above composition under the sputtering conditions. As for the substrate temperature during sputtering at this time, each film formation was performed at the temperature shown in Table 6. Then, a resist (OFPR800: Tokyo Ohka Kogyo Co., Ltd.) is coated on the surface of each Al-based alloy film, and a pattern film for forming a 20 μm width circuit is disposed for exposure treatment, and the TMAH development described in the first embodiment is performed. Development processing was performed with the solution. After the development processing, a circuit was formed with the phosphoric acid mixed acid etching solution described in the first embodiment, and the resist was removed with a DMSO stripping solution to form an Al-based alloy film circuit with a width of 20 μm.

Then, the substrate on which the 20 μm wide Al-based alloy film circuit was formed was subjected to pure water cleaning and drying treatment, and an SiNx insulating layer (thickness 4200 mm) was formed on the surface. This insulating layer was formed using a sputtering apparatus under sputtering conditions of an input power of RF 3.0 Watt / cm ² , an argon gas flow rate of 90 sccm, a nitrogen gas flow rate of 10 sccm, a pressure of 0.5 Pa, and a substrate temperature of 300 ° C.

Subsequently, a positive resist (manufactured by Tokyo Ohka Kogyo Co., Ltd .: TFR-970) is coated on the surface of the insulating layer, a 10 μm × 10 μm square pattern film for opening a contact hole is placed, exposed, and subjected to TMAH development. Development processing was performed with the solution. Then, a contact hole was formed using a dry etching gas of CF ₄ . The contact hole formation conditions were a CF ₄ gas flow rate of 50 sccm, an oxygen gas flow rate of 5 sccm, a pressure of 4.0 Pa, and an output of 150 W.

Thereafter, the resist was stripped with a DMSO stripper. And after removing residual peeling liquid using isopropyl alcohol, it washed with water and performed the drying process. An ITO transparent electrode layer was formed in and around the contact hole by using an ITO target (composition In ₂ O ₃ -10 wt% SnO ₂ ) for each sample after the resist peeling process was completed. The transparent electrode layer is formed by sputtering (substrate temperature 70 ° C., input power 1.8 Watt / cm ² , argon gas flow rate 80 sccm, oxygen gas flow rate 0.7 sccm, pressure 0.37 Pa) to form an ITO film having a thickness of 1000 mm. did.

  The ITO film surface is coated with a resist (manufactured by Tokyo Ohka Kogyo Co., Ltd .: OFPR800), a pattern film is placed and exposed, developed with a TMAH developer, and an oxalic acid mixed acid etchant (Kanto). A 20 μm-wide circuit was formed by using Chemical Corporation (ITO05N). After forming the ITO film circuit, the resist was removed with a DMSO stripping solution.

  A contact hole was formed by the procedure as described above, and the contact resistance value of the evaluation sample in which the Al-based alloy film and the transparent electrode layer were directly joined via the contact hole was measured. This contact resistance value measurement method was based on the four-terminal method as shown in FIG. 4, and the resistance value of each evaluation sample was measured after annealing the element of the evaluation sample in the atmosphere at 250 ° C. for 30 minutes. Table 7 shows the measurement results of the contact resistance value. In the four-terminal method shown in FIG. 4, 100 μA is energized from the terminal portion of the evaluation sample after heat treatment, and the resistance is measured.

  Subsequently, measurement of bonding strength in direct bonding with the transparent electrode layer will be described. About this joining strength, it carried out by the cross-cut test based on JISC5012. As in the case of the surface roughness measurement, each Al-based alloy film (2000 mm) was first formed on a glass substrate, and an ITO film (1000 mm) was laminated thereon. The film forming conditions are the same as the above sputtering conditions.

  About each evaluation sample produced in this way, a grid-like cut was formed using a cutter from the ITO film surface side so that 40 squares with a side of 5 mm were formed (5 mm squares with 4 vertical squares). (20 mm) × 10 horizontal (50 mm)). And the tape was affixed on the surface, the tape was peeled off after that, and the lattice state provided in the ITO film | membrane surface after tape peeling was confirmed visually. The area of the part where the film was peeled in 40 squares was measured, and the ratio (peeling rate%) to the total area of 40 squares was calculated to evaluate the bonding strength of each evaluation sample. A peeling rate of 0 to 20% was evaluated as ◯, a peeling rate of 21 to 60% as Δ, and a peeling rate of 61 to 100% as x. Table 7 shows the test results of the bonding strength.

  As can be seen from the results of Table 6 and Table 7, when the surface roughness value of the Al-based alloy film is increased, the contact resistance value when the element is formed also tends to be increased. As the roughness value decreased, the strength tended to decrease. From the above results, it was considered that the surface roughness with which the contact resistance value is 200Ω or less and the practical bonding strength can be ensured is in the range of Ra 2.0 to 20 mm, more preferably 10 to 20 mm.

Fourth Embodiment: In the fourth embodiment, the results of investigation on precipitates in a wiring circuit formed of the Al—Ni—B alloy wiring material according to the present invention will be described. The investigation of the precipitate in the wiring circuit was performed by analyzing the dispersion state.

  Here, the manufacturing method of the sample for cross-sectional observation in this 4th embodiment is demonstrated. This sample for observing the cross-section is an Al-5.0 at% Ni-0.4 at% B alloy film, Al-2.0 at% Ni-1.0 at% Nd alloy film having a thickness of 200 nm on a glass substrate, Al-3. A 0 at% Ni alloy film was formed by sputtering, and an ITO film was formed on each alloy film, followed by heat treatment at 250 ° C. in the atmosphere. FIGS. 5 and 6 show a transmission electron microscope (Hitachi Co., Ltd./H in the case of an Al-2.0 at% Ni-1.0 at% Nd alloy and an Al-5.0 at% Ni-0.4 at% B alloy. -9000 TEM: The schematic sectional drawing of the result of having observed the wiring circuit layer (film | membrane) cross section by 200,000 times magnification is shown. 5 and 6, the symbol A indicates an ITO film, and the symbol B indicates a glass substrate.

Next, a method for evaluating the distribution of precipitates from the above TEM observation photograph will be described. The central band portion in FIG. 6 shows the wiring circuit layer, and the dispersed material in the central band portion shows the Ni compound (Al—Ni intermetallic compound). As shown in this schematic cross-sectional view, the distribution state of the Ni compound is measured by the total length (l ₁ + l ₂ + l ₃ + l ₄ + l ₅ + l ₆ = Σl) in which the line segment perpendicular to the layer thickness direction cuts the Ni compound. And the ratio (%) with respect to the whole line segment length (L) was calculated | required, and this value was made into the presence rate of Ni compound. Further, when an Ni compound was identified by EDX analysis, in the case of an Al-5.0 at% Ni-0.4 at% B alloy wiring material, it was Al ₃ Ni phase that was dispersed and precipitated in the wiring circuit layer. It was an intermetallic compound. In the case of Al-2.0 at% Ni-1.0 at% Nd alloy wiring material, it was found that Al-Ni-based, Al-Nd-based, and Al-Ni-Nd-based intermetallic compounds were precipitated. did. Furthermore, as shown in the schematic diagram of FIG. 5, in the case of an Al-2.0 at% Ni-1.0 at% Nd alloy, an Al-Ni-Nd-based intermetallic compound is present on the glass substrate side (symbol B). Many segregations were observed. On the other hand, in the case of Al-5.0 at% Ni-0.4 at% B alloy, the intermetallic compound of the Al ₃ Ni phase, which is a precipitate in the wiring circuit phase, is uniformly dispersed without segregation. Turned out to be.

In FIG. 7, the result of having investigated the abundance ratio of Ni compound in the predetermined thickness position in the thickness direction of each wiring circuit layer is shown. As shown in FIG. 7, in the case of an Al-2.0 at% Ni-1.0 at% Nd alloy, the abundance of the Ni compound is from 75% from the glass substrate side (B) to the ITO film surface side (A). It turned out that it changed to 0%. Similarly, regarding the Al-3.0 at% Ni alloy wiring material, similarly, when the abundance ratio of the Ni compound was examined, the abundance ratio changed from 40% to 0% from the substrate side to the film surface side. Turned out to be. On the other hand, in the case of the Al-5.0 at% Ni-0.4 at% B alloy wiring material according to the present invention, the abundance of the Ni compound does not vary greatly from the substrate side to the film surface side. It was found that the content was in the range of 25% to 45%, and the Ni compound was not segregated and was uniformly dispersed.

TFT schematic sectional drawing. Photomicrograph of Si diffusion heat resistance evaluation. Photomicrograph of Si diffusion heat resistance evaluation. The test sample schematic perspective view which crossed and laminated | stacked the ITO (IZO) electrode layer and the Al alloy electrode layer. The schematic of the TEM observation photograph in the case of an Al-2.0at% Ni-1.0at% Nd alloy. The schematic of the TEM observation photograph in the case of Al-5.0at% Ni-0.4at% B alloy. The measurement graph of the abundance ratio of Ni compound.

Claims (11)

In an Al-Ni-B alloy wiring material containing nickel and boron in aluminum,
When the nickel content is the atomic percentage Xat% of nickel and the boron content is the atomic percentage Yat% of boron, the formula 0.5 ≦ X ≦ 10.0
0.05 ≦ Y ≦ 11.00
Y + 0.25X ≧ 1.00
Y + 1.15X ≦ 11.50
An Al—Ni—B alloy wiring material characterized by being in the range of a region satisfying each of the formulas, with the balance being aluminum. The Al-Ni-B alloy wiring material according to claim 1, wherein the nickel content is 4.0 at% or more and the boron content is 0.80 at% or less. The Al-Ni-B alloy wiring material according to claim 2, wherein a dimple generation rate generated on the surface of the wiring material after heat treatment at 350 ° C for 30 minutes is 1.6% or less. 4. The Al—Ni—B alloy wiring according to claim 1, wherein the nickel content is 4.0 at% to 6.0 at% and the boron content is 0.20 at% to 0.80 at%. material. The Al—Ni—B alloy wiring material according to claim 4, which has a specific resistance value of 5.0 μΩcm or less. An element structure of a display device comprising a wiring circuit layer formed of the Al-Ni-B alloy wiring material according to any one of claims 1 to 5, a semiconductor layer, and a transparent electrode layer,
An element structure of a display device, wherein the wiring circuit layer has a portion directly bonded to a semiconductor layer. An element structure of a display device comprising a wiring circuit layer formed of the Al-Ni-B alloy wiring material according to any one of claims 1 to 5, a semiconductor layer, and a transparent electrode layer,
An element structure of a display device, wherein the wiring circuit layer has a portion directly bonded to a transparent electrode layer. An element structure of a display device comprising the element structure according to claim 6. 7. The surface roughness value (Rz) of the semiconductor layer surface from which the directly bonded wiring circuit layer is peeled is 1.5 times or less of the surface roughness value (Rz) of the semiconductor layer surface after the semiconductor layer is formed. Or the element structure of the display device of Claim 8. A wiring circuit layer formed of the Al-Ni-B alloy wiring material according to any one of claims 1 to 5, and at least one of a semiconductor layer or a transparent electrode layer and the wiring circuit layer are directly bonded. An element structure of a display device,
In the wiring circuit layer, Ni compound is dispersed and deposited,
An element structure of a display device, wherein an abundance ratio of the Ni compound on a line segment orthogonal to the wiring circuit layer thickness direction in the wiring circuit layer cross section is 25% to 45% in the wiring circuit layer thickness direction. A sputtering target for forming a wiring circuit comprising the Al-Ni-B alloy wiring material according to any one of claims 1 to 5,
When the nickel content is the atomic percentage Xat% of nickel and the boron content is the atomic percentage Yat% of boron, the formula 0.5 ≦ X ≦ 10.0
0.05 ≦ Y ≦ 11.00
Y + 0.25X ≧ 1.00
Y + 1.15X ≦ 11.50
A sputtering target characterized by being in the range of a region satisfying each of the formulas, with the balance being aluminum.