Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/42—Plated through-holes or plated via connections
  • H05K3/421—Blind plated via connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
  • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
  • H05K3/462—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar double-sided circuit boards
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/03—Conductive materials
  • H05K2201/0332—Structure of the conductor
  • H05K2201/0335—Layered conductors or foils
  • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/03—Conductive materials
  • H05K2201/0332—Structure of the conductor
  • H05K2201/0388—Other aspects of conductors
  • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/09563—Metal filled via
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/095—Conductive through-holes or vias
  • H05K2201/096—Vertically aligned vias, holes or stacked vias
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09745—Recess in conductor, e.g. in pad or in metallic substrate
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
  • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
  • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/46—Manufacturing multilayer circuits
  • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
  • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Definitions

• the present invention relates to a multilayer printed wiring board, and more particularly to a build-up multilayer printed wiring board that can be suitably used for a circuit board for mounting an IC chip.
• build-up type multilayer printed wiring boards (mainly the method of manufacturing printed wiring boards by additive method) and multilayered multilayers with interlayer connection by via holes
• a printed wiring board (mainly a method of manufacturing a printed wiring board by the subtra method).
• an interlayer insulating resin is formed on both sides or one side of a core substrate having a through hole by a drill or the like, and a via hole for interlayer conduction is opened by laser or photo etching. Then, an interlayer resin insulation layer having via holes is formed. If necessary, a roughened layer is formed on the inner wall of the interlayer insulating layer or the no-hole. A conductor layer is formed on the inner wall of the via hole by plating or the like, and after etching, a pattern is formed on the interlayer insulating layer to form a conductor circuit. Furthermore, a build-up type multilayer printed wiring board can be obtained by repeatedly forming an interlayer insulating layer and a conductor layer.
• a conductor layer (covering layer) covering the surface of the through hole is provided, a via hole is formed on the covering, and a filled via that fills the via hole with a conductor is formed.
• a so-called stacked via structure in which a filled via is provided immediately above the filled via is used.
• a multilayer multilayer printed wiring board an opening (via hole) that penetrates the insulating layer is formed in the copper-clad laminate by laser or drill, and a conductor layer is formed in the opening by plating, conductive paste, etc.
• a laminated multilayer printed wiring board can be obtained by stacking a plurality of these substrates as a unit and laminating them sequentially or collectively by pressing or the like.
• a filled via may be used as a via hole of this multilayer multilayer printed wiring board, or it may be formed as a stacked via for forming a filled via immediately above the filled via.
• Patent Document 1 As a prior art of a build-up type multilayer printed wiring board, there is Patent Document 1, and as a prior art of a build-up type multilayer printed wiring board having a filled via, there is Patent Document 2. Further, there is Patent Document 3 as a prior art of a multilayer multilayer printed wiring board.
• Patent Document 1 Japanese Patent Laid-Open No. 2001-127435
• Patent Document 2 Japanese Patent Laid-Open No. 11-251749
• Patent Document 3 Japanese Patent Laid-Open No. 2003-37366
• the upper conductor layer (the conductor circuit on the interlayer insulating layer or the conductor circuit including the via hole) is connected to the lower conductor layer in the via hole via the interlayer insulating layer.
• the area is also reduced.
• the bond strength between the no-hole and the land tends to decrease, and when a reliability test such as a heat cycle condition or a high temperature and high humidity condition is performed, the connection resistance tends to increase between the two.
• the via hole is formed by forming an electroless plating film and an electrolytic plating film in this order. Since the electroless plating film formed earlier has low ductility, it is considered that cracks and fractures are likely to occur in the electroless plating film. In addition, if the printed wiring board is warped when an electronic component such as an IC chip is mounted, the electroless adhesive film cannot follow the warp, so it is considered that the noise hole is easy to peel off from the land.
• the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a multilayer printed wiring board capable of ensuring via hole connectivity and reliability. is there.
• an interlayer insulating layer and an upper conductor layer are formed on a lower conductor layer, and the lower conductor layer and the upper conductor layer are electrically connected via via holes.
• a technical feature is that a recess is provided on the lower conductor layer side at a connection portion with the bottom of the via hole.
• connection interface between the upper conductor layer and the lower conductor layer is shifted downward from the upper surface of the lower conductor layer at the connection portion between the bottom of the via hole and the lower conductor layer.
• the via hole A technical feature is that a recess is provided on the lower conductor layer side in a connection portion with the bottom of the via hole, and the size of the recess is equal to or larger than the bottom region of the via hole. .
• connection interface between the bottom conductor layer and the lower conductor layer is shifted from the upper surface of the lower conductor layer to the lower side, and the size of the recess in the lower conductor layer is Its technical feature is that it is the same size or larger than the bottom area of the via hole.
• the upper conductor layer is technically characterized in that the upper conductor layer has a bowl shape.
• an interlayer insulating layer and an upper conductor layer are formed on the lower conductor layer, and the lower layer conductor layer and the upper conductor layer are electrically connected via via holes.
• the via hole is a stack via that forms a via hole immediately above the via hole
• connection portion between the bottom of the via hole that is the stacked via and the lower conductor layer at least one connection interface between the upper conductor layer and the lower conductor layer is shifted downward from the upper surface of the lower conductor layer. It is a technical feature.
• the via hole Is a stack via that forms a via hole immediately above the via hole
• connection portion between the bottom of the via hole that is the stacked via and the lower conductor layer at least one connection interface between the upper conductor layer and the lower conductor layer is shifted downward from the upper surface of the lower conductor layer.
• size of the recess is a technical feature that is equal to or larger than the bottom area of the via hole.
• the multilayer printed wiring board in which the interlayer insulating layer and the upper conductor layer are formed on the lower conductor layer, and the lower conductor layer and the upper conductor layer are electrically connected via the via hole, Is a stack via that forms a via hole immediately above the via hole,
• the upper conductive layer as the stack via is technically characterized as having a bowl shape.
• an interlayer insulating layer and an upper layer conductor layer are formed on the lower layer conductor layer, and the lower layer conductor layer and the upper layer conductor layer are electrically connected via via holes.
• connection interface can be on the lower side.
• thermal stress such as heat shrinkage and stress generated at the time of impact are concentrated, and this is the largest via hole connection, and in the case where the position of the connection is the upper surface of the conventional lower conductor layer, Since the stress is not easily buffered, cracks and the like are generated in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, thereby reducing the connection reliability of the via hole.
• connection interface at the connection portion of the via hole is below the upper surface of the lower conductor layer. Therefore, the connection interface can be shifted downward from the point where stress is concentrated (the upper surface position of the lower conductor layer), and breakage hardly occurs along the connection interface.
• the stress generated at the connection interface can be buffered, the connection reliability of the via hole can be ensured without the occurrence of a conductive layer concavity near the interlayer insulating layer or via hole. As a result, the manufactured printed wiring board can ensure resistance to thermal stress and resistance to impact.
• the effect is the same, and the effect is not hindered by the size of the area. It is.
• connection interface is shifted downward from the upper surface of the lower conductor layer.
• the thermal stress such as heat shrinkage and the stress generated at the time of impact are concentrated, it is the largest via hole connection, and the position of the connection is the position of the upper surface of the conventional lower conductor layer. Since the stress is not easily buffered, cracks and the like have occurred in the interlayer insulating layer and the conductor layer in the via hole, and the connection reliability of the via hole has been reduced.
• the connection interface at the connection portion of the via hole is below the upper surface of the lower conductor layer.
• the stress (the upper surface position of the lower conductor layer) force on which the stress is concentrated can also shift the connection interface downward, and breakage hardly occurs along the connection interface.
• the stress generated at the connection interface can be buffered, it is difficult to cause cracks in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, and the connection reliability of the via hole can be ensured.
• the printed wiring board manufactured according to the present application can ensure resistance to thermal stress and resistance to impact. Further, even if the via hole diameter is reduced and the connection area at the via hole connection portion is reduced, The effect is the same, and the effect is not hampered by the size of the area.
• connection interface In the stacked via, the connection interface is shifted downward from the upper surface of the lower conductor layer at the connection portion between the bottom of the via hole and the lower conductor layer.
• the thermal stress during heat shrinkage and the stress generated during impact are concentrated, and this is the maximum hole connection, and if the connection is at the upper surface of the conventional lower conductor layer, the stress is reduced. Because it is hard to be buffered, cracks occur in the interlayer insulation layer and the conductor layer near the via hole! /, In some cases, the reliability of connection of the hall was reduced.
• the connection interface can be shifted downward from the point where stress is concentrated (the upper surface position of the lower conductor layer), and breakage hardly occurs along the connection interface.
• the stress generated at the connection interface can be buffered, it is possible to ensure the connection reliability of the via hole without causing a crack in the conductor layer near the interlayer insulating layer or via hole.
• the printed wiring board manufactured according to the present application can ensure resistance to thermal stress and resistance to impact.
• the force stack can achieve the maximum effect by shifting the connection interface below the upper surface of the lower conductor layer over the via hole connection located at the bottom layer of the stack.
• the effect can be obtained by positioning the via interface of the via or one via hole or the connection interface of all via holes below the upper surface of the corresponding lower conductor circuit. .
• the size (diameter) of the dent is preferably equal to or larger than the via hole diameter.
• the metal layer which is the upper conductor layer, penetrates into the recess.
• the metal layer is integrated inside the via hole and the lower conductor layer, and is fitted to the interlayer insulating layer. It becomes easy to ensure the bonding strength in the no hole. As a result, electrical connectivity and reliability are unlikely to decline.
• the integrated structure makes it easy to ensure drop resistance. Furthermore, it is more desirable that the size (diameter) of the recess is larger than the via hole diameter.
• the via hole which is the upper conductor layer has a bowl shape.
• This shape has two characteristics. One is shifting the via hole connection down. The other is that the side surface is widened outside the via hole, so that the resin layer and the via hole are fitted together. As a result, it is easy to ensure electrical connectivity and reliability, and resistance to thermal stress and resistance to impact can be ensured.
• connection interface between the bottom of the via hole, the upper conductor layer, and the lower conductor layer is shifted downward from the upper surface of the lower conductor layer. For this reason, the thermal stress during heat shrinkage and the stress generated at the time of impact are concentrated, and it is the top surface position of the lower conductor layer that maximizes, and the connection interface where cracks are most likely to enter is more reliable than the upper surface of the lower conductor layer. As a result, it is possible to shift the connecting force of stress to the lower side. As a result, it is difficult to cause defects such as cracks in the interlayer insulating layer and the conductor layer near the via hole. It is possible to ensure connection reliability.
• the printed wiring board manufactured by this application can ensure the tolerance with respect to a thermal stress, and the resistance at the time of an impact.
• connection interface between the upper conductor layer and the lower conductor layer at the bottom of the via hole is shifted from the upper surface of the lower conductor layer to the lower side of the upper surface of the lower conductor layer. For this reason, the connection interface where cracks are most likely to occur is surely below the upper surface of the lower conductor layer, and the stress concentrates more than the upper surface position of the lower conductor layer where the stress during thermal contraction and impact is maximum. As a result, it is possible to ensure via hole connection reliability because it is less prone to breakage at the connection interface, cracks in the interlayer insulation layer and conductor layers near the via hole, etc. Become.
• the applied stress value is reduced and the resistance can be ensured.
• the connecting interface is displaced by 5 m or more
• the applied stress value does not decrease.
• the lower conductor layer is recessed more than this, the lower conductor layer becomes thinner at that part depending on the thickness of the lower conductor layer. As a result, cracks are likely to occur in the recesses of the lower conductor layer, which is the part, and it may be difficult to ensure connectivity.
• the via hole has a bowl shape, the interlayer insulating layer and the via hole are in a fitted state, and the upper conductor layer and the lower conductor layer are easily joined. For this reason, it is easy to ensure connectivity and reliability.
• FIG. 8 shows a cross-sectional view of the multilayer printed wiring board 10
• FIG. 9 shows a state in which the IC chip 90 is attached to the multilayer printed wiring board 10 shown in FIG.
• a conductor circuit 34 is formed on the surface of the core substrate 30.
• the front surface and the back surface of the core substrate 30 are connected via a through hole 36.
• the through hole 36 includes a lidded layer 36a constituting the through hole land and a side wall conductor layer 36b, and the side wall conductor layer 36b is filled with a resin filler 37.
• a solder resist layer 70 is formed on the upper layer of the filled via 260, and bumps 78 U and 78 D having a soldering force are formed on the filled via 260 constituting the solder pad via the opening 71 of the solder resist layer 70. Yes.
• solder bump 78 U on the upper surface side of the multilayer printed wiring board 10 is connected to the land 92 of the IC chip 90.
• the lower solder bump 78D is connected to the land 96 of the daughter board 94.
• FIG. 10 shows an enlarged view of the lidded layer 36a, finalorevia 60, finalorevia 160, finalorevia (solder pad) 260, and bump 78U having soldering force in circle C in FIG.
• a recess 36h is provided on the side of the lidded layer 36a at the connecting portion between the bottom portion of the bottom filled via 60 having a stacked via structure and the lidded layer (lower conductor layer) 36a.
• the connection interface between the upper conductor layer and the cover layer (lower conductor layer) is from the upper surface of the cover layer (lower conductor layer) 36a.
• the depth is shifted by d 1 minute.
• the recess 36h has a diameter kl wider than the bottom of the via hole (the diameter at the upper surface position of the via hole lid layer 36a).
• connection interface between the upper conductor layer and the lower conductor layer is covered at the connection portion between the bottom of the bottom filled via 60 and the cover layer (lower conductor layer) 36a. Since the depth is shifted by dl from the upper surface of the attachment layer 36a, the connection interface is covered Compared with the case where it is formed on the upper surface of the layer 36a, the connection interface is on the lower side, and the position force for concentrating stress can also shift the connection interface, and as a result, breakage at the connection interface can be prevented. In addition, since it is difficult for defects such as cracks to occur in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, it is possible to ensure the connection reliability of the via hole. Moreover, the printed wiring board manufactured according to the present application can ensure resistance to thermal stress and resistance to impact.
• the connection interface between the upper conductor layer and the lower conductor layer is shifted by the width kl in the outer peripheral direction of the cover layer 36a, the metal layer of the upper conductor circuit penetrates into the via hole and the recess.
• a metal layer is formed integrally with the via hole and the lower layer conductor layer, and is configured to be fitted to the interlayer insulating layer. It becomes easy to secure the bonding strength in the hole. Therefore, electrical connectivity and reliability are unlikely to deteriorate. Moreover, since it is an integrated structure, it becomes easy to ensure drop resistance.
• a recess 60h is provided on the side of the lowermost filled via 60 at the connection between the bottom of the filled via 160 located in the middle layer of the stacked via structure and the lowermost filled via 60! Yes. That is, at the connection between the bottom of filled via 160 and filled via 60, the connection interface between the middle filled via conductor layer and the lower filled via conductor layer is deeper below the upper surface of the lower filled via 60 conductor layer. It is shifted by d2 minutes.
• the uppermost filled via 260 and the middle filled via 160 are similarly provided with a recess 160h in the conductor layer of the middle filled via 160, and the conductor layer of the uppermost filled via 260 and the conductor layer of the middle filled via 160 The connection interface is shifted by a depth of d3 from the upper surface of the conductor layer of the filled via 160 in the middle layer to be connected.
• the lidded layer (lower conductor layer) 60a is shifted by k2 from the bottom of the no hole. Further, the recess 60h has a k2 partial diameter wider than the bottom of the via hole 160 (the diameter of the via hole 160 at the upper surface position of the via hole 60). Similarly, the recess 160h has a k3 partial diameter wider than the bottom of the via hole 260 (the diameter of the via hole 260 at the upper surface position of the via hole 160).
• the filled via conductor layer of the middle layer and the filled layer of the lowermost layer are connected to the connection portion between the bottom portion of the filled via 160 of the middle layer and the field via 60 of the lowermost layer.
• the connection interface of the via conductor layer is shifted by a depth of d2 below the top surface of the filled via 60. Therefore, the connection interface can be shifted from the position where stress is concentrated (the top surface position of the filled via). Breaking is less likely to occur. As a result, cracks are less likely to occur in the interlayer insulating layer and the conductor layer near the via hole, and the connection reliability of the via hole can be ensured.
• the printed wiring board manufactured by this application can raise the tolerance with respect to a thermal stress, and the tolerance at the time of an impact.
• the connection interface between the upper conductor layer and the lower conductor layer is shifted by a width k2 in the outer peripheral direction of the cover layer 60, the metal layer of the upper conductor circuit enters the via hole and the recess. It is included.
• a metal layer that is integrated into the via hole and the lower-layer conductor layer becomes a structure that fits into the interlayer insulating layer. It becomes easy to secure the bonding strength in the hole. Therefore, the electrical connectivity and reliability are not easily lowered.
• it is an integrated structure it becomes easy to ensure drop resistance.
• connection reliability between the filled via 60 in the lowermost layer and the filled via 160 in the middle layer increases the connection reliability between the filled via 160 in the middle layer and the filled via 260 in the uppermost layer.
• filled vias 60 and 160 are formed by filling metal, stress is difficult to escape inside unlike via holes (non-filled via shape) filled with resin.
• the via hole connection reliability can be ensured by providing the concave portion on the conductor layer side which is the filled via corresponding to the lower layer of the filled via of all the filled vias in the inner layer.
• the tolerance with respect to a thermal stress and the tolerance at the time of an impact can be improved.
• the recesses have a size (diameter) equal to or larger than that of the via hole on the lower circuit side connected to each via hole. That is, the end of the recess is displaced.
• the metal layer of the upper conductor circuit penetrates into the via hole and the recess.
• a metal layer is formed integrally with the via hole and the lower-layer conductor layer, and is configured to be fitted to the interlayer insulating layer. It becomes easy to secure the bonding strength in the via hole. Therefore, electrical connectivity and reliability are unlikely to deteriorate.
• it since it has an integral ridge structure, it is easy to ensure drop resistance.
• the filled via 60, the filled via 160, and the filled via 260 force include the electroless plating layer 52 and the electrolytic plating layer 56.
• the electroless plating layer 52 is more fragile and contains impurities than the electrolytic plating layer 56.
• the force to concentrate stress can be increased. It can be displaced, and breakage at the electroless plating layer 52 can be prevented.
• defects such as cracks are less likely to occur in the interlayer insulating layer and the conductor layer in the vicinity of the via hole, and the via hole connection reliability can be ensured.
• resistance to thermal stress and resistance during impact can be increased.
• the concave portion be equal to or larger than the via hole on the lower circuit side connected to each via hole. That is, the end of the recess is displaced.
• the metal layer of the upper conductor circuit penetrates into the via hole and the recess.
• a metal layer is formed integrally with the via hole and the lower layer conductor layer, and is configured to be fitted to the interlayer insulating layer. It becomes easy to secure the bonding strength in the hole. Therefore, electrical connectivity and reliability are unlikely to deteriorate. Moreover, since it is an integrated structure, it becomes easy to ensure drop resistance.
• the connecting interface force between the bottom of the upper filled via and the lower filled via or the lower filled via and the cover layer 36a is shifted downward by 2 m or more from the upper surface of the lower filled via or the cover layer 36a. It is desirable. By setting it to 2 / zm, the connection interface can be arranged below the upper surface of the lower conductor layer, even if the thickness of the electroless plating and the thickness of the lower conductor layer are taken into account. It can be done. Therefore, compared to the case where the connection interface is positioned on the upper surface of the lower filled via or the lidded layer 36a, the connection interface is surely on the lower side, and the fracture at the connection interface is eliminated. Since it is difficult for defects such as cracks to occur in the conductor layer near the via hole, it is possible to ensure via hole connection reliability. In addition, resistance to thermal stress and impact resistance can be increased.
• the buffering of stress may be hindered depending on the thickness of the adhesive used or the thickness of the conductor layer on the lower layer side.
• via hole connectivity may not be improved, and resistance to thermal stress and impact resistance may not be improved.
• connection interface between the upper conductor layer and the lower conductor layer is shifted to the lower side by 3 ⁇ m or more from the upper surface of the conductor layer of the lower filled via and lid cover layer 36a. Is desirable.
• the stress value becomes highest in the stacked filled via and in the lowermost filled via.
• the connection interface is shifted downward from the upper surface of the lid-covering layer 36a at the connection portion between the bottom surface of the bottom layer filled via 60 and the lid plating layer 36a. For this reason, the stress concentration point can be shifted, the interlayer insulating layer is less prone to crack in the conductor layer near the via hole, the via hole connectivity can be improved, the resistance to thermal stress and the impact It increases resistance.
• solder with low toughness compared to lead solder is easy to peel off from the solder pad.
• FIG. 17 shows an example of filled vias subjected to stress analysis.
• the lower filled via 3rdV, the middle filled via 2ndV, and the upper filled via 1 stV are arranged so as to be displaced.
• the arrangement example of Fig. 17 (B) and Fig. 17 (E) In the arrangement example, the lower filled via 3rdV, the middle filled via 2ndV, and the upper filled via 1stV are arranged so as to be displaced.
• the difference between the arrangement example in FIG. 17 (A) and the arrangement example in FIG. 17 (B) is that in FIG.
• the conductor circuits lstC, 2ndC, and 3rdC are arranged away from the filled vias. In (B), they are located close to each other. Furthermore, the difference between the layout example in Fig. 17 (A) and the layout example in Fig. 17 (E) is that in Fig. 17 (A), the middle filled via 2ndV and the upper filled via 1stV are in the horizontal direction with respect to the lower filled via 3rdV. In contrast, the effect of stress is small, whereas in Fig. 17 (E), the displacement is small and the effect of stress is large.
• the lower layer filled via 3rdV, the middle layer filled via 2n dV, and the upper layer filled via IstV are arranged on a straight line.
• the conductor circuits lstC, 2ndC, and 3rdC are arranged close to the filled via, and in FIG. 17B, they are arranged apart from each other.
• FIG. 18 shows the result of simulating the stress applied to the left and right points of the lower end of the lower filled via 3rdV, the middle filled via 2ndV, and the upper filled via 1stV.
• the stress force in the arrangement example of Fig. 17 (C) and Fig. 17 (D) with three layers is higher than the arrangement example of Fig. 17 (A) and Fig. 17 (B), and from the top filled via IstV
• the stress value applied to the lower filled via 3rdV is larger than the middle filled via 2ndV where the stress applied to the middle filled via 2ndV is larger.
• the stress value increases as it goes down.
• the arrangement example shown in FIG. 17 (E) since the displacement amount of the middle filled via 2ndV and the upper filled via IstV is small in the lateral direction with respect to the lower filled via 3rdV, they are greatly affected by the mutual stress.
• the stress value applied to the lower filled via 3rdV is increasing.
• FIG. 19 shows the result of simulating the stress value acting on the lower end of the middle filled via 2ndV.
• Fig. 19 (A) is a schematic diagram of the middle filled via 2ndV
• Fig. 19 (B) is a graph showing simulation values.
• a force that forms a three-layer stack via is a two-layer stack via.
• the same effect can be obtained by shifting the connection interface downward by 2 m or more from the upper surface of the lower filled via and the lid covering layer.
• Example 1 when filled vias 60, 160, and 260 are formed by electroless plating film 52 and electrolytic plating film 56, filled vias are formed by a conductor such as spatter and paste. Has the same effect. Further, for example, a combination of conductor layers of different plating methods such as upper layer: electrolytic plating film, middle layer: non-electrolytic plating film, and lower electrolytic plating film has the same effect.
• a reduction treatment using an aqueous solution containing 4 as a reducing bath is performed to form a sidewall conductor layer 36b of the through hole 36 and a roughened surface 36a on the surface (FIG. 1 (D)).
• a filler 37 containing copper particles with an average particle size of 10 ⁇ m (non-conductive hole filling copper paste made by Tatta Electric Wire, product name: DD paste) is screen-printed on the through hole 36. Fill, dry, and cure (Fig. 1 (E)). This is applied to the substrate on which a mask having an opening in the through hole portion is placed by a printing method so that the through hole is filled, and after filling, dried and cured.
• the filler 37 protruding from the through-hole 36 was removed by belt sander polishing using # 600 belt polishing paper (manufactured by Sankyori Kagaku), and this belt sun was further removed.
• the surface of the substrate 30 is flattened by performing puff polishing to remove scratches caused by dur polishing (see FIG. 2 (A)). In this way, the substrate 30 is obtained in which the side wall conductor layer 36b of the through hole 36 and the resin filler 37 are firmly adhered to each other through the rough coating layer 36a.
• An electroless copper having a thickness of 0.6 m is obtained by applying a palladium catalyst (manufactured by Atotech) to the surface of the substrate 30 flattened in the above (3) and applying electroless copper plating.
• a plating film 23 is formed (see FIG. 2 (B)).
• electrolytic copper plating is performed under the following conditions to form an electrolytic copper plating film 24 having a thickness of 15 m, thickening the portion to become the conductor circuit 34, and filling the through hole 36 A part to be a capped layer (through hole land) covering the filled filler 37 is formed (FIG. 2 (C)).
• electrolytic plating solution [Electrolytic plating solution]
• the resin film for the interlayer resin insulation layer is permanently bonded onto the substrate under the conditions of a vacuum of 67 Pa, a pressure of 0.4 MPa, a temperature of 85 ° C, and a bonding time of 60 seconds, and then at 170 ° C. Heat cured for 40 minutes.
• a recess 36h having a depth of 3 m is formed on the surface of the lid capping layer 36a exposed through the opening 51 with an etching solution mainly composed of salty cupric copper. This depth is set to a desired value by adjusting the time of light etching (Fig. 4 (B)). In Fig. 11 (B), the opening 51 indicated by C2 is enlarged.
• catalyst nuclei are attached to the surface of the interlayer resin insulation layer and the inner wall surface of the filled via opening.
• the above substrate is made of palladium chloride (PbCl) and salt stannic acid (SnCl
• the catalyst was applied by precipitating palladium metal. [0067] (13) Next, the catalyst was placed in an electroless copper plating aqueous solution (Sulcup PEA) manufactured by Uemura Kogyo Co., Ltd. The surface of the interlayer resin insulation layer 50 including the inner wall of the opening 51 for the hole 51 is formed by immersing the applied substrate to form an electroless copper plating film having a thickness of 0.3 to 3.0 m over the entire rough surface. A substrate with a 2 m electroless copper plating film 52 formed thereon was obtained (Fig. 4 (C)).
• the substrate 30 is washed with 50 ° C. water for degreasing, washed with 25 ° C. water, further washed with sulfuric acid, and then subjected to electrolytic plating under the following conditions.
• An electroplated film 56 was formed, and a filled via 60 and a conductor circuit 58 made of an electroless film 52, an electroplated film were provided (FIG. 5A).
• Fig. 11 shows an enlarged view of filled via 60 in 011 (C).
• the electroless plating layer 52 having a thickness of 2 m of the filled via 60 is provided in the recess 36h having a depth of 3 m, so that the electroless plating layer 52 having low toughness is provided on the upper surface of the lid coating layer 36a. It is provided on the lower side.
• cracks are less likely to occur between the filled via 60 and the lidded layer 36a, and resistance to thermal stress and resistance to impact can be increased.
• the electroless plating film under the plating resist is etched and dissolved with a mixed solution of sulfuric acid and hydrogen peroxide.
• an interlayer insulating layer 150 having an opening 151 is formed on the filled via 60 and the conductor circuit 58 (FIG. 5D).
• the opening 151 indicated by C4 in the figure is enlarged and shown in FIG. 13 (A).
• the interlayer insulating layer 150 having the filled via 160 and the conductor circuit 158 is formed (FIG. 6B).
• the filled via 160 indicated by C6 in the figure is enlarged and shown in FIG. 13 (C).
• the filled via 160 is further enlarged and shown in FIG.
• the electroless plating layer 52 having a thickness of 2 ⁇ m of the filled via 160 is provided in the recess 60h having a depth d2 (3 ⁇ m), so that the electroless plating layer 52 having low toughness is formed in the filled via 60. It is provided below the top surface. As a result, cracks are less likely to occur between filled via 60 and filled via 160, and resistance to thermal stress and resistance to impact can be increased.
• solder resist composition 70 is applied to both sides of the multilayer wiring board at a thickness of 20 ⁇ m, and the conditions are 70 minutes at 20 ° C. and 30 minutes at 70 ° C.
• a photomask with a thickness of 5 mm on which the pattern of the opening of the solder resist is drawn is brought into close contact with the solder resist layer 70 and exposed to UV light of lOOOiuJ / cm 2 and developed with a DMTG solution.
• An opening 71 having a diameter of 200 m was formed (FIG. 7 (A)).
• solder resist layer was cured by heat treatment under the respective conditions to form a solder resist pattern layer having openings and a thickness of 15 to 25 ⁇ m. Opening indicated by C7 in the figure 7
• Figure 1 (A) shows an enlarged view of 1.
• OSP Organic Solderability Preservative
• solder paste containing lead-free (SnZAgZCu 65Z32. 5 / 2.5) solder is printed in the opening 71 of the solder resist layer 70 on the surface on which the IC chip of the substrate is placed. Furthermore, after printing a solder base containing tin-antimony on the opening of the solder resist layer on the other side, solder bumps (solder bodies) are formed by reflowing at 200 ° C.
• a multilayer printed wiring board having solder bumps 78U and 78D was manufactured (FIG. 8).
• FIG. 15 (B) the region surrounded by the circle C is enlarged.
• Fig. 16 shows an enlarged view of the filled via (solder pad) in Fig. 15 (B).
• solder bump 78U solder bump
• Example 1-2 the four-part depth by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 1-1 was adjusted to 0.5 / zm.
• Example 1-3 the depth of the four parts by the etching of the force capping layer 36a and filled vias 60, 160, and 260, which are the same as those of Example 1-1, was adjusted.
• Example 1-2 the four-part depth by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 1-1 was adjusted to 2 / zm.
• Example 1-5 the depth of the four parts by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 1-1 was adjusted to 4 / zm.
• Example 16 is similar to Example 1-1 above in the force capping layer 36a and filled bilayer.
• the depth of the four parts by etching 60, 160 and 260 was adjusted to 5 / zm.
• Example 1-7 the depth of the four parts by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 1-1 was adjusted to 6 / zm.
• Example 18 the depth of the recessed portion by etching of the force capping layer 36a and filled vias 60, 160, 260 similar to Example 1-1 was adjusted to 1 m.
• Example 11 1 there was a maximum of three stacked layers of filled vias.
• Example 18 the filled vias were stacked up to two layers.
• Example 1-9 the same force filled vias as in Example 1-8 were not stacked.
• Example 110 the bottom diameter of the force filled via, which is the same as that of Example 11 above, was set to 60 ⁇ m.
• Example 1-12 the depth of the recesses due to the etching of the force capping layer 36a and the fill vias 60, 160, 260 similar to those in Examples 1-10 above was adjusted to 1 m.
• Example 1-15 In Example 1-15, the depth of the concave portion obtained by etching the force capping layer 36a and the fill vias 60, 160, and 260 was adjusted to 5 m, which was the same as in Examples 1-10 above.
• Example 1-16 the depth of the concave portions obtained by etching the force capping layer 36a and the fill vias 60, 160, 260 similar to those in Examples 1-10 above was adjusted to 6 m.
• Example 11 the structure was the same as that of Example 11 described above with reference to FIG. 8, but the concave structure was not provided in the force lid plating layer 36 a and filled vias 60, 160, and 260.
• solder bumps 78U and 78D are provided on filled via 260.
• solder bumps 78U and 78D are provided on the filled via 260 and the conductor circuit 258.
• the OSP layer 72 was provided on the filled via 260 in the opening 71 of the solder resist layer 70.
• the solder bump 78U is disposed in the opening 71 of the solder resist layer 70 through the nickel plating layer 73 and the gold plating layer 74 formed on the fill via 260 and the conductor circuit 258. 78D is provided.
• Example 2-1 the depth of the four portions by the etching of the capping layer 36a and the filled vias 60, 160, and 260 was adjusted to 3 / zm in the same manner as in Example 1-1.
• Example 2-2 the four-part depth by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 2-1 was adjusted to 0.5 / zm.
• Example 2-3 In Example 2-3, the depth of the four parts by the etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 2-1 was adjusted.
• Example 2-2 the four-part depth by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 2-1 was adjusted to 2 / zm.
• Example 2-5 the depth of the four parts by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 2-1 was adjusted to 4 / zm.
• Example 2-6 the four-part depth by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 2-1 was adjusted to 5 / zm.
• Example 2-7 the four-part depth by etching of the force capping layer 36a and filled vias 60, 160, and 260 similar to those in Example 2-1 was adjusted to 6 / zm.
• Example 2-8 the depth of the concave portion obtained by etching the force capping layer 36a and the filled vias 60, 160, and 260, which is the same as that of Example 2-1 above, was adjusted to 1 m.
• Example 21 there was a maximum of three stacked layers of filled vias.
• Example 2-8 filled vias were stacked up to two layers.
• Example 2-9 the same force filled via as in Example 2-8 was used.
• Example 2-10 the bottom diameter of the force filled via, which is the same as that in Example 2-1 above, was set to 60 m.
• Example 2-11 the depth of the four parts by etching of the force capping layer 36a and filled vias 60, 160, 260 similar to those of Example 2-10 was adjusted to 0.5 / zm. (Example 2-12)
• Example 2-12 the depth of the recesses by etching of the force capping layer 36a and filled vias 60, 160, 260, which are the same as those of Examples 2-10, was adjusted to 1 m.
• Example 2-13 the depth of the concave portion obtained by etching the force capping layer 36a and the filled vias 60, 160, and 260, which is the same as that of Example 2-10, was adjusted to 2 m.
• Example 2-15 the depth of the recessed portion by etching of the force capping layer 36a and filled vias 60, 160, and 260, which is the same as that of Example 2-10, was adjusted to 5 m.
• Example 2-1 the structure was the same as that of Example 2-1 described above with reference to FIG. 8 except that the concave portion was not provided in the force lid plating layer 36a and filled vias 60, 160, and 260.
• the bottom diameter of the force field via having the same structure as that of Example 2-1 described above with reference to FIG. 8 is set to 60 m, and the lidded layer 36a and filled vias 60, 160, The 260 has a structure without a recess.
• Example 3 A multilayer printed wiring board according to Example 3 will be described with reference to the cross-sectional view of FIG. In Example 1 described above with reference to FIG. 8, force using filled vias In Example 3, via holes 60 and 160 filled with grease are used. In Example 1, the through hole was provided with a cover layer, and a filled via was provided on the cover layer. On the other hand In Example 3, the through hole 36 does not have a cover layer, and the via hole 60 is connected to the land of the through hole!
• Example 3-1 the depth of the concave portion by etching of the conductor circuit 34 and the conductor circuit 58 was adjusted to 3 ⁇ m as in Example 1-1.
• Example 3 as in Example 1, the connection interface is lower than the upper surfaces of the conductor circuits 34 and 58 at the connection portion between the via hole 60 and the conductor circuit 34 and between the no hole 160 and the conductor circuit 58.
• the connection interface that is most prone to cracking is located below the top surface of the conductor circuits 34 and 58 where the stress during thermal contraction and impact is maximized. It becomes difficult to increase the resistance to thermal stress and the resistance to impact.
• the connection reliability between the via hole 60 and the conductor circuit 34 and between the via hole 160 and the conductor circuit 58 is improved.
• Example 3-2 is the same as Example 3-1 above, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 0.5 ⁇ m.
• Example 3-3 was the same as Example 3-1 above, but the depth of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 was adjusted to 1 ⁇ m.
• Example 3-2 is the same as Example 3-1 above, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 2 m.
• Example 3-5 is the same as Example 3-1 above, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 4 / zm.
• Example 3-6 is the same as Example 3-1 above, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 5 ⁇ m.
• Example 3-7 is the same as Example 3-1, except that conductor circuit 34, conductor circuit 58 and The recess depth by etching of the conductor circuit 158 was adjusted to 6 ⁇ m.
• Example 3-8 the bottom diameter of the force filled via, which is the same as that of Example 3-1, was 60 m.
• Example 3-9 was the same as Example 3-8 above, but the depth of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 was adjusted to 0.5 ⁇ m.
• Example 3-10 is the same as Example 3-8, except that the depth of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 was adjusted to 1 ⁇ m.
• Example 3-11 was the same as Example 3-8 above, but the depth of the recesses formed by etching conductor circuit 34, conductor circuit 58, and conductor circuit 158 was adjusted to 2 ⁇ m.
• Example 3-12 was the same as Example 3-8 above, but the depth of the recesses by etching of conductor circuit 34, conductor circuit 58 and conductor circuit 158 was adjusted to 4 ⁇ m.
• Example 3-13 was the same as Example 3-8 above, but the depth of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 was adjusted to 5 ⁇ m.
• Example 3-14 is the same as Example 3-8 above, but the depths of the recesses formed by etching the conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 were adjusted to 6 ⁇ m.
• Example 3-1 a structure in which the concave portions were not provided in the force conductor circuit 34, the conductor circuit 58, and the conductor circuit 158 having the same structure as that of Example 3-1 described above with reference to FIG.
• the bottom diameter of the force field via having the same structure as Example 3-1 described above with reference to FIG. 8 is set to 60 m, and conductor circuit 34, conductor circuit 58, and conductor circuit 1
• the structure is such that no recess is provided in 58.
• Example 4 is a multilayer multilayer printed wiring board formed by laminating a plurality of substrates.
• FIG. 26 is a cross-sectional view of the multilayer printed wiring board of Example 4.
• the multilayer printed wiring board 10 is formed by stacking substrates 30.
• Each substrate 30 is provided with a conductor circuit 42 on one surface and a conductor circuit 44 on the other surface, and the conductor circuit 42 and the conductor circuit are connected via a via hole 46.
• the via hole 46 is connected to the conductor circuit 42 via a recess 32 h provided on the inner surface side of the conductor circuit 42.
• a solder bump 78U is connected to the via hole 46 of the substrate 30 on the upper surface side through a recess 46h.
• the solder bump 78D is connected to the via hole 46 of the substrate 30 on the lower surface layer side via the recess 46h.
• the upper surface layer and the lower surface layer are provided with a solder resist layer 70 in which openings 71 for projecting the solder bumps 78U and 78D are formed.
• electronic components 90 and 90B are connected to the solder bump 78U and the solder bump 78D on the upper surface side of the multilayer printed wiring board 10.
• connection interface between the via hole 46 and the lower conductor layer 42 is a recess on the back surface of the lower conductor layer. Since it is shifted by 32 hours, the upper surface position force of the conductor circuit 42 where the stress is concentrated can also shift the connection interface downward, and as a result, breakage at the connection interface can be prevented.
• the multilayer printed wiring board manufactured according to the present application can increase resistance to thermal stress and resistance to impact.
• a double-sided circuit board constituting a multilayer circuit board is manufactured.
• This circuit board uses as a starting material a double-sided copper-clad laminate 30A obtained by laminating epoxy resin with glass cloth into a B stage and laminating copper foil 32 and heat-pressing the laminate. Used (Fig. 22 (A)).
• the insulating substrate has a thickness of 75 ⁇ m, and the copper foil has a thickness of 16 ⁇ m. If necessary, the insulating base material may be etched to reduce the thickness of the copper foil 32 (for example, 14 ⁇ m) (Fig. 22 (B)
• the via 16 for forming the via hole is formed by using a high peak short pulse oscillation type carbon dioxide laser processing machine manufactured by Hitachi Via Co., Ltd., on a glass cloth epoxy resin base material having a base material thickness of 75 m.
• the copper foil is directly irradiated with a laser beam, and at a speed of 100 holes and Z seconds, 10
• Additive A (Reaction accelerator) 10. 0 ml / 1
• Additive A promotes the formation of an electrolytic copper plating film in the via hole (opening), while additive B adheres mainly to the copper foil portion and suppresses the formation of the plating film.
• additive B is attached, so that formation of a plating film is suppressed as in the copper foil portion.
• the electrolytic copper plating 14 was filled in the opening 16 to form a flattened via hole 46 (FIG. 23 (A)).
• the electrolytic copper plating swells at the upper part of the opening 16
• the swelled part may be removed by a physical method such as sander belt polishing or puff polishing and flattened.
• a photosensitive dry film etching resist 38 was formed on the copper foil 32 and the copper plating 14 of the insulating base material 30 that had undergone step (3) (FIG. 23 (B)).
• the resist 38 was formed with a thickness of 15 to 20 IX m, and after exposure and development, a copper plating 14 and a non-resist formation portion on the copper foil 32 were formed.
• Etching is performed on the non-formed portion of the resist 38 with an etching solution having a copper chloride strength, and the copper plating film 14 and the copper foil 32 corresponding to the non-formed portion are removed. Thereafter, the resist is stripped off with an alkaline solution to form a conductor circuit 44 including the conductor circuit 42 and the via hole 46 (FIG. 23C). As a result, there is a no-hole 46 for connecting the front and back sides, and a circuit board in which the no-hole 46 and the copper foil portion forming the conductor circuit are flattened can be obtained. Thereafter, a blackening process may be performed to form a black layer 44B on the conductor circuits 42 and 44 (FIG. 23D).
• circuit board 30 obtained through the steps (1) to (6) is taken as one unit (FIG. 24 (A)), and an adhesive layer 48 such as a pre-preda is sandwiched on this board. Pressing conditions Temperature 80 to 250 ° C, pressure 1 to: Heat pressing was performed with L0kgfZcm2, and the multilayered substrate 10 was formed by laminating (FIG. 24 (B)).
• a solder resist layer was formed on the surface of the circuit board located at the uppermost layer and the lowermost layer of the multilayer substrate 10.
• a solder resist layer formed into a film was formed to a thickness of 20 to 30 ⁇ m on the substrate by applying a film-formed solder resist layer or coating with a varnish whose viscosity was adjusted in advance.
• the nickel plating layer 73 having a thickness of 5 ⁇ m was formed in the opening 71 by dipping for a minute (FIG. 25 (A)).
• the substrate was made into an electroless gold plating solution comprising 2 gZl of potassium gold cyanide, 75 gZl of sodium chloride ammonium, 50 gZl of sodium citrate, and 1 OgZl of sodium hypophosphite. It is immersed for 23 seconds under the condition of ° C to form a gold plating layer 74 having a thickness of 0.03 m on the nickel plating layer 73, and a coated metal layer composed of the nickel plating layer 73 and the gold plating layer 74 is formed. (Fig. 25 (B)).
• solder paste made of SnZPb solder having a melting point T2 of about 183 ° C is printed on the solder pad exposed from the opening 71 of the solder resist layer 70 covering the uppermost multilayer circuit board.
• solder bumps (or solder layers) 78U and 78 (D) were formed (Fig. 26).
• Example 4-2 was the same as Example 4-1 described above, but the depth of the recess formed by etching the conductor layer was adjusted to 0.5 ⁇ m.
• Example 4-3 is the same as Example 4-1 above, but the depth of the recess by etching of the conductor layer was adjusted to 1 ⁇ m.
• Example 44 the depth of the concave portion by etching the force conductor layer, which is the same as that of Example 4-1, was adjusted to 2 m.
• Example 4-5 was the same as Example 4-1 above, but the depth of the recess by etching of the conductor layer was adjusted to 4 m.
• Example 46 the depth of the recess formed by etching the force conductor layer, which is the same as that of Example 4-1, was adjusted to 5 m.
• Example 4-7 was the same as Example 4-1 above, but the depth of the recess by etching of the conductor layer was adjusted to 6 m.
• Example 4-1 As Comparative Example 4-1, the structure was the same as that of Example 4-1 described above with reference to FIG. 26, but the conductor layer 32 and the via hole 46 were not provided with recesses.
• the multilayer substrate 10 is irradiated with a carbon dioxide laser so as to pass through the copper foil 32 and the insulating base material 30 on the outer layer side and form an opening 16 for forming a via hole reaching the inner layer conductor circuits 44 and 42. Make a hole (Fig. 29 (A)).
• Recesses 44h and 42h having a depth of 3 m are formed in the inner-layer conductor circuits 44 and 42 exposed by the opening 16 with an etching solution (FIG. 29B). This depth is set to a desired value by adjusting the light etching time.
• Electrolytic copper plating is applied to the substrate on which the recesses 44h and 42h are formed, and the electrolytic copper plating 14 is filled in the opening 16 to form a flattened via hole 46 (FIG. 30).
• a photosensitive dry film etching resist was formed on the copper foil 32 and the copper plating 14, and a resist non-formation portion was formed through exposure and development. Then, the non-resist forming portion is etched with an etching solution such as copper chloride to remove the copper plating film 14 and the copper foil 32 corresponding to the non-forming portion. Thereafter, the resist was peeled off with an alkaline solution to form a conductor circuit 44 including a via hole 46 (FIG. 30B). Subsequent steps are the same as those in the fourth embodiment described above with reference to FIGS.
• a multilayer printed wiring board according to Embodiment 5 will be described with reference to the cross-sectional view of FIG.
• the multilayer printed wiring board 10 of Example 5 is formed by laminating a substrate 30 as in Example 4.
• the fifth embodiment has a stacked via structure in which a via hole is arranged immediately above the via hole.
• the via hole 46 is connected to the conductor circuit 42 via a recess 32 h provided on the inner surface side of the conductor circuit 42. This prevents breakage at the connection interface between the via hole 46 and the conductor circuit 42.
• Example 5-2 is the same as Example 5-1 above, but the depth of the recess by etching the conductor layer was adjusted to 0.5 ⁇ m. (Example 5-3)
• Example 5-3 was the same as Example 5-1 above, but the depth of the recess by etching of the conductor layer was adjusted to 1 ⁇ m.
• Example 5-4 is the same as Example 5-1 above, but the depth of the recess by etching of the conductor layer was adjusted to 2 m.
• Example 5-5 was the same as Example 5-1 above, but the depth of the recess by etching the conductor layer was adjusted to 4 m.
• Example 5-6 was the same as Example 5-1 above, but the depth of the recess by etching of the conductor layer was adjusted to 5 m.
• Example 5-7 is the same as Example 5-1 above, but the depth of the recess by etching of the conductor layer was adjusted to 6 m.
• Comparative Example 5-1 has the same structure as that of Example 5-1 described above with reference to FIG. 31, except that the conductor layer 32 and the via hole 46 are not provided with a recess.
• an IC chip was mounted on the multilayer printed wiring boards of each of the examples and comparative examples, and a sealing resin was filled between the IC chip and the multilayer printed wiring board to obtain an IC mounting substrate. Then, the electrical resistance of a specific circuit via the IC chip (the electrical resistance between a pair of electrodes exposed on the surface opposite to the IC chip mounting surface of the IC mounting substrate and connected to the IC chip) is measured. The value was taken as the initial value. Thereafter, a heat cycle test was performed on these IC-mounted substrates with 55 cycles X 5 minutes and Comparative Example 5 degrees X 5 minutes as one cycle, and this was repeated 2500 times.
• the comparison between the first and second embodiments using filled vias and the third embodiment using via holes shows that the filled vias have lower connection reliability against thermal stress than the via holes. It was possible to improve the connection reliability of filled vias by using the structure provided.
• the comparison between Example 1-3, Example 1-8, and Example 1-9 shows that the reliability decreases as the number of overlaid vias increases. As in Example 1-1, 3 m or more It was found that the desired reliability can be obtained by providing a recess having a depth of.
• the board 10 of Example 1-1 to Example 5-7 and Comparative Example 1-1-1 to Comparative Example 5-1 are mounted on the daughter board 60, and each is housed in a case 98. Secure with screws.
• this fixed casing 98 is allowed to fall naturally from the height of lm with the vertical (head wall TP on the top and bottom wall BT on the bottom) side down. After the drop test, the electrical connection was made for each of the examples.
• Example 1 If the drop test is cleared 10 times, the drop resistance can be increased compared to the conventional product (Comparative Example 1-1). This is true for all of Examples 1-1 to 5-7. I was able to clear. Meanwhile, 30 times Clearing the drop test indicates a high drop resistance. Except for Example 1-2, Example 2-2, Example 3-2, Example 4 2, and Example 5-2, Examples 1 1 to Examples 5-7 were able to clear 30 times.
• FIG. 6 Process diagram showing a method for producing the multilayer printed wiring board of Example 1.
• FIG. 7 Process diagram showing the method for producing the multilayer printed wiring board of Example 1.
• FIG. 8 is a cross-sectional view of a multilayer printed wiring board according to Example 1.
• FIG. 9 is a cross-sectional view showing a state where an IC chip is mounted on the multilayer printed wiring board according to Embodiment 1.
• FIG. 10 is an enlarged view of a portion surrounded by a circle C in FIG.
• FIG. 11 Process drawing showing the method for producing the multilayer printed wiring board of Example 1.
• FIG. 12 is an enlarged view of finoredovia in FIG. 11 (C).
• FIG. 13 is a process diagram showing a method for producing the multilayer printed wiring board of Example 1.
• FIG. 14 is an enlarged view of the filled via in FIG. 13 (C).
• FIG. 15 is a process drawing showing the method for producing the multilayer printed wiring board in Example 1.
• FIG. 16 is an enlarged view of the filled via in FIG. 15 (C).
• FIG. 17 is a schematic diagram showing an arrangement example of filled vias.
• FIG. 18 is a graph showing stress values with respect to the etching amount of filled vias in FIG.
• FIG. 19A is a schematic diagram showing an example of the arrangement of filled vias
• FIG. 19B is a graph showing a stress value with respect to the etching amount of filled vias in FIG. 19A.
• FIG. 20 is a cross-sectional view of a multilayer printed wiring board according to Example 2.
• FIG. 21 is a cross-sectional view of a multilayer printed wiring board according to Example 3.
• FIG. 22 Process drawing showing the method for producing the multilayer printed wiring board of Example 4.
• FIG. 23 is a process drawing showing the method for producing the multilayer printed wiring board according to Example 4.
• FIG. 24 is a process drawing showing the method for producing the multilayer printed wiring board according to Example 4.
• FIG. 25 is a process drawing showing the method for producing the multilayer printed wiring board according to Example 4.
• FIG. 26 is a cross-sectional view of a multilayer printed wiring board according to Example 4.
• FIG. 27 is a cross-sectional view showing a state where electronic components are mounted on the multilayer printed wiring board according to Embodiment 4.
• FIG. 28 is a process diagram showing a method of manufacturing a multilayer printed wiring board according to a modification of Example 4.
• FIG. 29 is a process diagram showing a method of manufacturing a multilayer printed wiring board according to a modification of Example 4.
• FIG. 30 is a process diagram showing a method for producing a multilayer printed wiring board according to a modification of Example 4.
• FIG. 31 is a cross-sectional view of the multilayer printed wiring board according to Example 5.
• FIG. 32 is an explanatory diagram showing the contents of a drop test.
• FIG. 33 is a chart showing results of drop test and reliability test of Example 1 and Comparative Example 1.
• FIG. 34 is a chart showing results of drop test and reliability test of Example 2 and Comparative Example 2.
• FIG. 35 is a chart showing the results of drop tests and reliability tests of Example 3 and Comparative Example 3.
• FIG. 36 is a chart showing the results of drop test and reliability test of Example 4 and Comparative Example 4.
• FIG. 37 is a chart showing the results of drop test and reliability test of Example 5 and Comparative Example 5. Explanation of symbols

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• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

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Cited By (8)

Families Citing this family (5)

Citations (5)

• 2006
  • 2006-03-22 JP JP2007509308A patent/JP4973494B2/ja active Active
  • 2006-03-22 WO PCT/JP2006/305721 patent/WO2006101134A1/ja active Application Filing
  • 2006-03-23 TW TW095110045A patent/TW200704327A/zh unknown

Patent Citations (5)

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