WO2006085436A1 - Substrat avec composante intégrée et condensateur avec substrat intégré - Google Patents

Substrat avec composante intégrée et condensateur avec substrat intégré Download PDF

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Publication number
WO2006085436A1
WO2006085436A1 PCT/JP2006/300970 JP2006300970W WO2006085436A1 WO 2006085436 A1 WO2006085436 A1 WO 2006085436A1 JP 2006300970 W JP2006300970 W JP 2006300970W WO 2006085436 A1 WO2006085436 A1 WO 2006085436A1
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WO
WIPO (PCT)
Prior art keywords
component
substrate
dielectric
conductor pattern
dielectric sheet
Prior art date
Application number
PCT/JP2006/300970
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English (en)
Japanese (ja)
Inventor
Yoshihiro Tomita
Tadashi Nakamura
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Publication of WO2006085436A1 publication Critical patent/WO2006085436A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/26—Folded capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/162—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed capacitors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/05—Flexible printed circuits [FPCs]
    • H05K2201/055—Folded back on itself
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present invention relates to a component built-in substrate and a substrate built-in capacitor, and more particularly to a substrate structure in which electronic components are built in a base material capable of high-density wiring.
  • Patent Document 1 having a configuration power as shown in FIG.
  • a dielectric made of a ceramic dielectric material is formed on a part of a predetermined ceramic sheet 201a.
  • the layer 202 is formed, and electrode conductors 203 and 204 are formed on the upper and lower surfaces of the dielectric layer 202.
  • the dielectric layer 202 and the electrode conductors 203 and 204 sandwiching the dielectric layer 202 constitute a capacitor 205 built in the multilayer wiring board 200.
  • the dielectric layer 202 is sintered by filling the opening formed in the ceramic sheet 201a with a dielectric paste that is a ceramic dielectric material, and then drying by heating.
  • Patent Document 1 Japanese Patent Laid-Open No. 9-92983
  • Patent Document 2 JP 2002-290051 A
  • the capacitor-embedded substrate disclosed in Patent Document 1 is composed of a single-layer dielectric sheet, the required capacity is larger than that of a multilayer ceramic capacitor. In particular, it is difficult to apply as a decoupling capacitor. Also In order to increase the capacitance of the capacitor, it is necessary to form a high-permittivity sheet with a large area. As a result, the effective area for routing the wiring decreases, which hinders the formation of high-density wiring. .
  • the high dielectric constant sheet since a ceramic material that requires high-temperature firing is used as the high dielectric constant sheet, when a capacitor is built in the resin substrate, the ceramic dielectric paste is placed in the resin substrate. After formation, it is difficult to fire the entire resin substrate at a high temperature. If a composite sheet in which powder of a high dielectric constant material is mixed with resin is used, it can also be applied to a resin substrate. However, since the dielectric constant is low, it is not possible to form a large-capacity capacitor. Have difficulty.
  • the present invention has been made in view of the strong point, and an object of the present invention is to provide a component-embedded substrate that enables both high-performance component incorporation and high-density wiring.
  • a component-embedded substrate of the present invention includes a substrate formed by laminating a plurality of dielectric layers arranged along the opposing direction of both main surfaces of the substrate along the substrate plane direction, And an internal conductor pattern provided on both surfaces of the dielectric layer.
  • the electronic component is configured using the internal conductor pattern as a constituent element, and the electronic component is embedded in the substrate.
  • the electronic component is a capacitor
  • the capacitor is constituted by the dielectric layer and the internal conductor pattern facing each other across the dielectric layer.
  • the electronic component is an inductor
  • the inductor is
  • the wiring layer is configured as a Miranda wiring.
  • adjacent dielectric layers are connected and formed integrally with each other on either one of the two main surfaces of the substrate, and adjacent to each other.
  • Each connecting part of the dielectric layer is on either side of the main surface of the substrate!
  • the plurality of dielectric layers constitute a single dielectric sheet that is bent, and the connection parts are alternately arranged in parallel, so that one of the main boards of the component-embedded substrate is provided. And other main surfaces.
  • the inner conductor pattern is provided on each of both surfaces of the dielectric sheet, and the inner conductor pattern provided on each of both surfaces of the dielectric sheet includes: It is provided over a plurality of dielectric layer forming regions arranged in parallel, and is disposed opposite to the dielectric sheet.
  • the dielectric layers are preferably fixed to each other by an insulating adhesive member provided between the layers.
  • the internal conductor pattern is preferably exposed from the insulating adhesive member at the connection portion.
  • the internal conductor pattern exposed at the connection portion on one main surface side of the substrate is used as a first electrode terminal, and the capacitor is exposed at the connection portion on the other main surface side.
  • the internal conductor pattern is preferably used as the second electrode terminal.
  • an insulating film is provided on both main surfaces of the substrate, and an opening reaching the internal conductor pattern is provided at a position facing the connection portion of the insulating film, and is exposed to the opening. It is preferable that both electrode terminals of the capacitor are constituted by the internal conductor pattern.
  • a semiconductor chip is mounted on the insulating film, and a connection terminal of the semiconductor chip is connected to an electrode terminal of the capacitor exposed in the opening.
  • the capacitor is formed in a partial region of the substrate.
  • the internal wiring of the substrate built-in substrate is formed from the region of the internal conductor pattern other than the capacitor.
  • a part of the internal conductor pattern constituting the internal wiring extends to the connection part and is exposed on the main surface of the substrate, and the part of the exposed internal conductor pattern is the internal part. It is preferable to configure a lead electrode for wiring.
  • the dielectric sheet is preferably made of a material having a high dielectric constant.
  • the dielectric sheet includes a first dielectric sheet made of a thin film having a sufficient required dielectric constant, and a mechanical strength of the first dielectric sheet that does not have the required dielectric constant.
  • a second dielectric sheet that is higher than the body sheet, the inner conductor pattern is provided on both sides of the first dielectric sheet, and the first and second dielectric sheets are integrated into a stack. It is preferable to be displayed.
  • the component-embedded substrate of the present invention includes a substrate formed by laminating a plurality of dielectric layers arranged along the opposing direction of both main surfaces of the substrate along the substrate plane direction, and the adjacent dielectric
  • the body layers are formed on one of the two main surfaces of the substrate, the ends of the layers are connected and integrally connected to each other, and the connecting portions of the adjacent dielectric layers are arranged at least on both main surfaces of the substrate.
  • the plurality of dielectric layers constitute a single dielectric sheet bent and arranged on the other side, and the dielectric layers are insulating adhesive members provided between the layers. They are fixed to each other, and the connecting portions are alternately arranged in parallel to constitute one main surface and the other main surface of the component-embedded substrate. A part is disposed between the adjacent dielectric layers, and the part is covered with the insulating adhesive member.
  • connection part for connecting the dielectric layers located at both ends of the component has a flat portion having a width substantially the same as the width of the component.
  • the component is housed in a region surrounded by both dielectric layers connected by the flat portion.
  • the component is arranged, and a conductor pattern is formed on the main surface of another dielectric layer, and the conductor pattern constitutes an internal wiring of the component-embedded substrate. .
  • the component is preferably a semiconductor chip, a chip capacitor, a chip resistor, a chip inductor force, a force that is at least one selected electronic component, or a heat spreader.
  • the dielectric sheet is preferably a composite material containing a ferroelectric filler and a thermosetting resin.
  • a plurality of dielectric layers arranged along the opposing direction of both main surfaces of the substrate are stacked along the substrate plane direction, and the dielectric layers are insulative.
  • a substrate is provided that is fixed to each other by an adhesive member.
  • Adjacent dielectric Layers are connected and formed on one of the two main surfaces of the substrate in such a manner that the ends of the layers are connected to each other, and the connecting portions of the adjacent dielectric layers are connected to the main surfaces of the two substrates.
  • the plurality of dielectric layers constitute a single dielectric sheet bent and arranged.
  • the connecting portions are alternately arranged in parallel to constitute one main surface of the substrate and another main surface.
  • An internal conductor pattern is provided on both surfaces of the dielectric sheet.
  • a capacitor is formed by the dielectric sheet and the internal conductor pattern facing each other across the dielectric sheet.
  • the inner conductor pattern exposed at the connecting portion on one main surface side of the substrate is used as a first electrode terminal, and the inner conductor pattern exposed at the connecting portion on the other main surface side is used as a second electrode terminal.
  • the present invention constitutes a built-in electronic component such as a capacitor using the internal conductor pattern formed on both sides with the dielectric layer in between as a constituent element, the surface area of the component in the electronic component such as a capacitor (Electrode surface area, etc.) can be increased, and electronic parts with excellent characteristics (such as large-capacity capacitors) can be compactly formed.
  • Such an effect of the present invention is remarkably obtained when the dielectric layer is formed by alternately and continuously folding the dielectric sheet with a predetermined width.
  • FIG. 1 is a diagram showing a configuration of a wiring board 1 related to the present invention.
  • FIG. 2 (A), FIG. 2 (B), and FIG. 2 (C) are diagrams showing the structure of a dielectric sheet on which a conductor pattern is formed.
  • FIG. 3 is a cross-sectional view of a wiring board related to the present invention.
  • FIG. 4 is a cross-sectional view showing a configuration of a component built-in substrate incorporating a capacitor according to Embodiment 1 of the present invention.
  • FIG. 5 is an enlarged cross-sectional view showing the configuration of the capacitor of the present invention.
  • FIG. 6 is a cross-sectional view showing a configuration of a component-embedded substrate on which a capacitor and internal wiring of the present invention are formed.
  • FIG. 7 is a cross-sectional view showing a method for taking out the electrode of the capacitor of the present invention.
  • FIG. 8 is a cross-sectional view showing another method of taking out the electrode of the capacitor of the present invention.
  • FIG. 9 is a cross-sectional view showing a configuration of a component built-in board on which the semiconductor chip of the present invention is mounted.
  • FIG. 10 (A) to FIG. 10 (D) are process diagrams showing respective stages of the dielectric sheet forming method of the present invention.
  • [11A] A diagram showing a method of folding a dielectric sheet according to the present invention.
  • FIG. 11B is a diagram showing a method of folding a dielectric sheet according to the present invention.
  • FIG. 11C A diagram illustrating a method of folding a dielectric sheet according to the present invention.
  • FIG. 12 is a cross-sectional view showing a configuration of a component-embedded substrate incorporating an electronic component according to Embodiment 2 of the present invention.
  • FIG. 13 is a cross-sectional view showing a configuration of a component-embedded substrate incorporating an electronic component according to Embodiment 2 of the present invention.
  • FIG. 14- (A) to FIG. 14- (C) are diagrams showing the structure of a dielectric sheet on which a conductor pattern of the present invention is formed.
  • FIG. 15 is a cross-sectional view showing a configuration of a component-embedded substrate incorporating the electronic component of the present invention.
  • FIG. 16 is a cross-sectional view showing the configuration of a multilayer wiring board incorporating a conventional capacitor.
  • FIG. 17 is a cross-sectional view showing a configuration of a multilayer wiring board incorporating a conventional electronic component.
  • External conductive pattern 30 Internal conductor pattern a End of internal conductor pattern
  • FIG. 1 is a diagram showing a wiring board 100 as a basic configuration of the present invention.
  • a wiring board 100 shown in FIG. 1 has a rectangular flat plate shape.
  • the wiring substrate 100 has a plurality of dielectric layers 11. Each dielectric layer 11 is disposed along a facing direction (thickness direction) t of both main surfaces of the substrate, and then laminated along a direction wl orthogonal to the facing direction t.
  • the orthogonal direction wl refers to one substrate plane direction along an arbitrary side of the wiring substrate 100 having a rectangular shape.
  • Inner conductor patterns 12 and 13 are provided on the surface of the dielectric layer 11.
  • the inner conductor patterns 12 and 13 are provided on both surfaces of the dielectric layer 11.
  • Adjacent dielectric layers 11 are formed by connecting and forming the ends of the layers so as to communicate with each other on either side of both main surfaces 20 and 21 of the substrate.
  • connection site 11 a is provided in the dielectric layer 11 continuously along the full width of the dielectric layer 11 (the full width of the wiring board 100), that is, along the substrate plane direction w2 orthogonal to the orthogonal direction w1 on the substrate plane. It is done.
  • the connecting portion 11a is provided at both ends of each dielectric layer 11.
  • the plurality of connecting portions 11a are alternately arranged on either one of the main surfaces 20 and 21 of the substrate along the orthogonal direction wl.
  • the connecting portion 11a adjacent to the connecting portion 11a on the one substrate main surface 20 side is provided on the other substrate main surface 21, and the connecting portion 11a adjacent to the connecting portion 11a on the other substrate main surface 21 side is It is provided on one substrate main surface 20.
  • the plurality of dielectric layers 100 as a whole are in the form of a single dielectric sheet 10 that is bent by being folded at the connecting portion 11a, and further from the folded dielectric sheet 10.
  • a substrate is constructed.
  • the inner conductor patterns 12 and 13 are arranged in a strip shape along the longitudinal direction of the dielectric layer 11 constituting the dielectric sheet 10 in this way.
  • the layer longitudinal direction is the direction of the connecting ridgeline of the connecting portion 11a, and specifically, the substrate plane direction w2.
  • Each dielectric layer 11 is fixed to each other with an insulating adhesive layer 16 disposed between the layers, and the inner conductor patterns 12 and 13 are covered with the insulating adhesive layer 16.
  • one substrate main surface 20 of the wiring substrate 100 is constituted by a continuous body of a plurality of connecting portions 11a fixed by the insulating adhesive layer 16.
  • the other substrate main surface 21 of the wiring substrate 100 is constituted by a continuous body of a plurality of connecting portions 1 la fixed by an insulating adhesive layer 16.
  • At least one of the plurality of internal conductor patterns 12 and 13 is extended to a connection portion 1 la where the surface of the dielectric layer 11 on which the internal conductor patterns 12 and 13 are formed becomes the connection outside.
  • the extended ends of the inner conductor patterns 12 and 13 are exposed at one of the main surfaces 20 and 21.
  • the internal conductor patterns 12 and 13 formed on both surfaces of the same dielectric layer 11 are connected to each other via via holes 22 formed in the dielectric layer 11.
  • the internal conductor patterns 12 and 13 exposed on the main surfaces 20 and 21 of the wiring board 100 constitute lead electrodes 17 and 18.
  • the upper surfaces of the extraction electrodes 17 and 18 are flat surfaces parallel to the substrate main surfaces 20 and 21 so that electronic components mounted on the wiring substrate 100 can be stably mounted.
  • the lead electrodes 17 and 18 formed on both surfaces of the same dielectric layer 11 They are connected to each other through via holes 22 formed in the electric conductor layer 11.
  • the wiring board 100 has a shape in which the inner conductor pattern 12 formed in a band shape is alternately laminated in the lateral direction with the dielectric layer 11 sandwiched therebetween.
  • the wiring can be routed at a minute pitch that is the same as the thickness of the internal conductive patterns 12 and 13.
  • the thickness of the dielectric layer 11 is 4 m and the thickness of the internal conductive patterns 12 and 13 is 1 m, it is possible to route wiring with a very high density of 4 to 5 m.
  • the wiring board 100 the internal conductive patterns 12 and 13 are covered with the insulating adhesive layer 16, so to speak, the wiring board 100 is arranged in the interior of the wiring board 100. High-density wiring is possible while maintaining a narrow pitch that is not obstructed by external connection terminals formed on the main surface of the wire substrate 100.
  • the wiring board 1 shown in FIG. 1 can be formed by alternately folding dielectric sheets by the methods shown in FIGS. 2- (A) to 2- (C) and FIG.
  • FIGS. 2- (A) to 2- (C) respectively show a plan view, a sectional view at XY, and a bottom view of the dielectric sheet 10 before being folded.
  • the peak side line PP ′ that becomes a mountain when viewed from one surface of the dielectric sheet 10 becomes a valley.
  • the valley side line Q—Q ' is virtually set.
  • These mountain side lines P ⁇ ⁇ ′ and valley side lines Q—Q ′ are set along the direction w 3 along one side of the dielectric sheet 10.
  • the peak line P—P ′ and the valley line Q— are set alternately, parallel to each other, and at regular intervals.
  • the direction w3 is a direction that is the same direction as the substrate plane direction w2 in the wiring substrate 100.
  • the inner conductor pattern 12 is formed in a strip shape on one surface of the dielectric sheet 10.
  • the arbitrary internal conductor pattern 12 is formed so as to extend to a position exceeding the peak line P—P ′, and constitutes a first lead electrode 17.
  • the inner conductor pattern 13 is formed in a strip shape on the other surface of the dielectric sheet 10. The inner conductor pattern 12 and the inner conductor pattern 13 face each other with the dielectric sheet 10 in between. Be placed.
  • the inner conductor pattern 13 opposite to the inner conductor pattern 12 having the first lead electrode 17 is formed to extend to a position exceeding the trough side line Q-.
  • a pattern of electrodes 19 is formed.
  • mountain side lines P— or valley side lines Q— Q ′ are arranged on both sides of the inner conductor patterns 12, 13, and the medium force one of these lines P— P ⁇ and Q— Q ′ is Then, the inner conductor patterns 12 and 13 are extended to the selected line to form lead electrodes 17 and 19.
  • the selection of the line P - ⁇ ', Q—Q' is performed as follows. As shown in FIGS. 2 (A) to 2 (C), the dielectric sheet 10 is alternately folded along the lines P— and Q—Q ′.
  • the extension end is located inside the sheet of the dielectric sheet 10 in the bent state, and the sheet When it is located outside, force S is generated.
  • the lines P— ⁇ and Q—Q ′ positioned outside the sheet of the dielectric sheet 10 whose pattern extending ends are bent are selected.
  • via holes 22 are formed in the dielectric sheet 10 in advance.
  • the via hole 22 is formed at a position where the inner conductor pattern 12 where the first lead electrode 17 is formed and the inner conductor pattern 13 where the second lead electrode 19 is formed face each other.
  • the via hole 22 is configured by filling a through-hole formed through the dielectric sheet 10 in the thickness direction with an interlayer connection conductor (metal conductor).
  • the via hole 22 is arranged at a position as close as possible to the extraction electrodes 17 and 19.
  • the first extraction electrode 17 and the second extraction electrode 19 are connected to each other by contacting the via hole 22 (interlayer connection conductor).
  • the dielectric sheet 10 is alternately and continuously folded along the peak side line P— and the valley side line Q—Q ′. At that time, when viewed from one surface of the dielectric sheet 10,
  • the structure of the wiring substrate 100 in which the dielectric layer 11 is laminated along the substrate plane direction is specific.
  • the layer ends of the dielectric layers 11 are connected by connecting portions 11a formed by alternately folding the dielectric sheets 10.
  • a plurality of connecting portions 11a are provided, and each connecting portion 11a is alternately arranged on one of the both ends of each dielectric layer 11.
  • each dielectric layer 11 Insulating adhesive layers (insulating adhesive members) 16 are filled in between, thereby fixing the dielectric layers 11 to each other. As a result, a plurality of dielectric layers 11 having partial forces superimposed on each other are formed.
  • the extraction electrodes 17 and 19 are exposed on the main surfaces 20 and 21 of the wiring board 100, located outside the connection portion 11a.
  • the extraction electrode 17 is connected to the inner conductor pattern 12 by the same material formed integrally, and the extraction electrode 19 is formed of the same material formed integrally. Connected to the inner conductor pattern 13. Further, the inner conductor pattern 12 and the inner conductor pattern 13 are connected to each other through the via hole 22. Thereby, the first extraction electrode 17 and the second extraction electrode 19 are electrically connected to each other.
  • external connection electrodes (not shown) are respectively formed on the first lead electrode 17 and the second lead electrode 19, they are mounted on both main surfaces 20, 21 of the wiring board 110.
  • the circuit components can be connected by signal lines.
  • the case where one via hole 22 is formed in the dielectric layer 11 has been described.
  • the inner conductor pattern 12 and the inner conductor pattern 13 are formed in parallel with the dielectric layer 11 in between. Therefore, the via hole can be formed at any point in between.
  • the wiring board 100 realizes high-density wiring having narrow pitch wiring that cannot be achieved by the conventional wiring board, but actually mounts a plurality of LSIs on the wiring board.
  • LSIs In addition to wiring that connects LSIs, it is necessary to mount capacitors and electronic components.
  • high-density wiring there is a demand for wiring boards that can incorporate high-performance components.
  • the inventor of the present application has the wiring substrate 100 composed of the dielectric layers 11 having the partial force superimposed on each other, but the dielectric layers 11 are essentially continuous electric charges folded alternately. Since it is composed of the body sheet 10, it was noted that the dielectric sheet 10 itself could be the dielectric core of the power capacitor. In other words, apart from the dielectric layer 11 constituting the high-density wiring, the capacitor can be configured by forming the inner conductor pattern on both sides with the dielectric sheet 10 folded continuously alternately. It will be possible. Dielectric sheet 10 Since it can be folded at high density, it is possible to obtain a wiring board containing a large-capacity capacitor in addition to high-density wiring.
  • FIG. 4 is a cross-sectional view showing a basic configuration of the component-embedded substrate 2 according to the first embodiment of the present invention.
  • the basic configuration in FIG. 4 is the same as that in FIG. 1, and the same or similar components are denoted by the same reference numerals.
  • the component built-in substrate 2 can be regarded as a substrate built-in capacitor, but in the following description of each embodiment, they are collectively referred to as a component built-in substrate.
  • the component-embedded substrate 2 includes the dielectric layer sheet 10 that is alternately and continuously folded with a predetermined width, and the internal conductor pattern formed on both surfaces of the dielectric layer sheet 10. 30 and 3 1 are provided.
  • the configuration of the folded dielectric sheet 10 is basically the same as that of the wiring board 100 of FIG. 1 and constitutes the base material of the component-embedded board 2.
  • a capacitor is configured by the dielectric layer sheet 10 and the internal conductor patterns 30 and 31 sandwiching the dielectric sheet 10.
  • the component-embedded substrate 2 shown in FIG. 4 has a high-density formation region of the internal wiring pattern shown in FIG. However, in FIG. 4, the high density formation region is not shown.
  • the dielectric sheet 10 a capacitor is formed in a part of the region, and a high density formation region of the internal wiring pattern is formed in the other region.
  • the folded dielectric sheet 10 has a plurality of connecting parts 1 la formed by alternately folding the dielectric sheets 10, and these connecting parts 1 la Are arranged in parallel, one substrate main surface 20 of the component-embedded substrate 2 and another substrate main surface 21 are formed.
  • the dielectric sheet 10 is united by an insulating adhesive member 16 disposed between the dielectric layers 11 in a folded state.
  • the inner conductor patterns 30, 31 are the main surfaces 20, 21 It is exposed to the outside at (connection part 11a).
  • the internal conductor patterns 30 and 31 exposed to the outside constitute a first electrode terminal and a second electrode terminal of the capacitor, respectively.
  • Examples of the dielectric sheet 10 include a ferroelectric filler such as TiBaO and a thermosetting resin.
  • Capacitors with higher capacitance can be obtained by using a material that has a higher dielectric constant and can be made thinner than the force that can be used for a sheet that also becomes a composite material.
  • a capacitor of lOOnF or more is required for the purpose of decoupling the LSI power supply.
  • a dielectric sheet as thin as 4 m can be applied.
  • a large capacity can be obtained in a capacitor built-in substrate of 3. 5nFZcm 2.
  • the conventional capacitor-embedded substrate using this sheet cannot obtain a capacity sufficient to achieve the purpose of decoupling and the like.
  • the sheet thickness is 4 m
  • the folding width of the sheet is lmm
  • the folding interval pitch between peaks and peaks
  • 500 layers are folded per cm.
  • a capacitor capacity of 175 nF / cm 2 can be obtained as the entire capacitor built-in substrate.
  • a capacitor having an extremely large capacity of about 50 times that of the conventional component-embedded substrate can be incorporated in the substrate, and LSI decoupling, which has been difficult in the past, is difficult. It is possible to incorporate a capacitor for use in a compact.
  • the dielectric sheet 10 forms the base material of the component-embedded substrate 2, a certain degree of mechanical strength is required, and selection of the material is limited.
  • the dielectric sheet 10 is configured as follows, for example. That is, the first dielectric sheet 10A is composed of a dielectric thin film that does not have the required mechanical strength but has a sufficient dielectric constant required as an electronic component such as a capacitor. Internal conductor patterns 30 and 31 are formed on both surfaces of the first dielectric sheet 10A, respectively.
  • a second dielectric sheet 10B is prepared, and the second dielectric sheet 10B is adhered to one surface of the first dielectric sheet 10A.
  • the second dielectric sheet 10B does not have a dielectric constant required for an electronic component such as a capacitor! / Although the dielectric strength is sufficiently higher than that of the first dielectric sheet 10A.
  • the multilayer dielectric sheet (10A + 10B) configured in this way is folded and integrated to form a capacitor. Then, the first dielectric sheet 10A (dielectric thin film) having a sufficiently high dielectric constant can be obtained after the role as the base material (maintaining mechanical strength) is exhibited by the second dielectric sheet 10B. A large capacity capacitor can be formed by using a dielectric core.
  • FIG. 5 is a cross-sectional view showing, in an enlarged manner, a part of the folded multilayer dielectric sheet (10A + 10B), the configuration of the capacitor thus formed.
  • the first dielectric sheet 10A made of a dielectric thin film having a sufficient required dielectric constant, and the mechanical strength of the first dielectric sheet 10A is lower than that of the first dielectric sheet 10A.
  • a second dielectric sheet 10B made of a dielectric sheet higher than the dielectric sheet 10A is prepared. Then, the inner conductor pattern 30 and the inner conductor pattern 31 are formed on the main surface of the first dielectric sheet 10A. Further, the second dielectric sheet 10B is laminated on one surface of the first dielectric sheet 10A, thereby forming a sheet form as a whole. Then, the multilayer dielectric sheet (10A + 10B) in this state is folded and bonded and integrated with the insulating adhesive layer 16 to constitute a capacitor.
  • the thickness of the first dielectric sheet 10A can be reduced to a fraction of that of the dielectric sheet 10 described in FIG. 1 and the like, the entire dielectric sheet 10 is formed as a dielectric core. Compared with a capacitor, a capacitor having a larger capacity can be formed. Moreover, even in that case, the mechanical strength of the entire capacitor can be maintained by the second dielectric sheet 10B.
  • FIG. 6 shows the component-embedded substrate 2 in which the capacitor and the internal wiring are formed in different regions (A) and (B) of the dielectric sheet 10.
  • the inner conductor patterns 30 and 31 are formed on both surfaces of the dielectric sheet 10 to form a capacitor.
  • the inner conductor patterns are formed on both surfaces of the dielectric sheet 10 (dielectric layer). pattern 12 and 13 are formed to constitute the internal wiring.
  • the dielectric sheet 10 in the region constituting the capacitor has as high a dielectric constant as possible, but the dielectric sheet 10 (dielectric layer) in the region constituting the internal wiring can be formed. Only a low dielectric constant is preferred. Therefore, as long as the dielectric sheet 10 made of the same material is used, it is difficult to satisfy the requirements for the internal wiring and the capacitor at the same time.
  • the dielectric sheet 10 is also configured with the second dielectric sheet 10B force in FIG. 5 described above, and the inner conductor in FIG. 5 described above is formed in a partial region (A) of the sheet 10B. Capacitors are selectively formed in the region (A) by forming the patterns 30 and 31 and the first dielectric sheet 10A. Then, the above requirements can be satisfied at the same time.
  • part of the internal conductor patterns 12 and 13 formed on the main surface of the dielectric sheet (dielectric layer) 10 By extending to the connecting part 11a of the sheet 10, the part of the exposed conductor pattern is exposed on the main surface of the component-embedded board, and the exposed electrodes 17, 19 of the inner conductor patterns 12, 13 are exposed. There is no.
  • FIG. 7 is a diagram showing a configuration for extracting the capacitor electrode when an insulating film is formed on the main surface of the component-embedded substrate 2.
  • insulating films 32 and 32 are formed on both main surfaces of the component-embedded substrate 2.
  • the insulating film 32 is formed with an opening 33 reaching the substrate main surfaces 20 and 21 (the connecting portion 11a of the dielectric layer 11).
  • the opening 33 is selectively provided at a position where the end portions of the internal conductor patterns 30 and 31 are exposed on the surface of the substrate 2.
  • the inner conductor patterns 30 and 31 are exposed at the bottom of the opening 33, and the exposed inner conductor patterns 30 and 31 constitute electrode terminals of the capacitor.
  • an extraction electrode 34 is formed over the surface of the insulating film 32 at the peripheral edge of the peripheral surface force of the opening 33, and the electrode terminal of the capacitor is constituted by the extraction electrode 34.
  • the electrode terminals of the capacitor are taken out from both surfaces of the component built-in substrate 2, but as shown in FIG. Out May be. This will be described below.
  • the inner conductor pattern 30 on one side of the dielectric sheet 10 has an inner conductor pattern end 30a and an inner conductor pattern end 30b.
  • the inner conductor pattern end 30a is physically connected and electrically connected to the inner conductor pattern 30 on the main body side.
  • the inner conductor pattern end 30b is physically separated from the inner conductor pattern 30 on the main body side and electrically insulated.
  • a plurality (two in the figure) of openings 33a and 33b are selectively formed on one substrate main surface 20 side. Extraction electrodes 34a and 34b are provided in the openings 33a and 33b, respectively.
  • the inner conductor pattern end 30a is connected to the extraction electrode 34a through one opening 33a.
  • the inner conductor pattern 30 is connected to the extraction electrode 34a.
  • the inner conductor pattern end 30b is connected to the extraction electrode 34b through the other opening 33b. Further, the inner conductor pattern end 30 b is connected to the inner conductor pattern end 31 b of the inner conductor pattern 31 through the via hole 35. Thus, the inner conductor pattern 31 is connected to the extraction electrode 34b.
  • FIG. 9 is a diagram showing a state in which a semiconductor chip is mounted on the surface of the lead-out electrode forming surface of the component built-in substrate 2 on which the capacitor is formed.
  • the configuration of the component-embedded substrate 2 used here is basically the same as the configuration shown in FIGS.
  • the semiconductor chip 40 is mounted on the insulating film 32 provided on the extraction electrode formation surface of the component-embedded substrate 2.
  • the connection terminal 41 of the semiconductor chip 40 is connected to the extraction electrode 34 on the insulating film 32 via the bump 42.
  • the capacitor formed on the component-embedded substrate 2 can be disposed immediately below the semiconductor chip 40, and therefore can function as a decoupling capacitor.
  • FIGS. 10 and 11 Figures 10- (A) to 10- (D) show the process of forming the dielectric sheet before folding.
  • a dielectric sheet 10 having a certain width is prepared.
  • FIG. 10- (B) on the surface of the dielectric sheet 10, along the width direction w3 of the dielectric sheet 10 (direction perpendicular to the paper surface, see FIG. 2), virtual Folded mountain side line P— P ′ and valley side line Q— are provided.
  • the mountain side line P- and the valley side line Q-Q ' are provided alternately and in parallel with each other with a certain regular interval. Determined.
  • a bending guide groove formed by scraping a part of the surface of the dielectric sheet 10 into a wedge shape along the mountain side line P—P ⁇ and the valley side line Q—Q ′. 50 is formed.
  • the bending guide groove 50 of the mountain side line P—P ′ is provided on one surface of the dielectric sheet 10
  • the bending guide groove 50 of the valley side line Q— is provided on the other surface of the dielectric sheet 10. It is done.
  • conductive thin films 60 and 61 are formed on both surfaces of the dielectric sheet 10.
  • the manufacturing method is slightly different.
  • the second dielectric sheet 10B as the dielectric sheet 10
  • at least a capacitor after the steps shown in FIGS. 10A and 10B before forming the conductive thin films 60 and 61.
  • a base electrode thin film is formed as an inner conductor pattern 30 in FIG. 5 on at least one surface of the second dielectric sheet 10B in the region where the first dielectric sheet 10B is formed, and the first dielectric sheet 10A made of a high dielectric constant thin film is formed on the thin film.
  • the internal conductor pattern 31 of FIG. 5 may be formed thereon.
  • the substrate can be stably manufactured even with the first dielectric sheet 10A made of a thin film having a high dielectric constant and no strength.
  • a part of the lower electrode thin film in FIG. 5 can be exposed from the first dielectric sheet 10A and connected to a part of the internal conductor pattern 31 (conductive thin film 60) to be pulled out. It is also possible to connect and draw out the base electrode thin film and the conductive thin film 61 provided on the back surface thereof through a via hole provided in the second dielectric sheet 10B.
  • a capacitor made of the first dielectric sheet 10A shown in FIG. 5 may be provided on both surfaces of the second dielectric sheet 10B.
  • the dielectric sheet 10A can be made sufficiently thin, so that double capacitance can be obtained with almost the same size.
  • the conductive thin films 60 and 61 formed in the region to be the internal wiring are etched to form the internal conductor patterns 12 and 13 constituting the internal wiring. .
  • the conductive thin films 60 and 61 formed in the region to be the capacitor become the inner conductor patterns 30 and 31 constituting the capacitor electrode as they are.
  • a semi-curing insulating sheet 62 was formed on the dielectric sheet 10, and then along the peak side line P— ⁇ and the valley side line Q—Q ′. Remove semi-cured insulation sheet 62 in the area of constant width.
  • FIGS. 11A to 11C a method for folding the dielectric sheet 10 on which the conductive patterns 12 and 13 and the internal conductor patterns 30 and 31 are formed will be described with reference to FIGS. 11A to 11C.
  • FIGS. 11A to 11C only the dielectric sheet 10 is shown, and the conductive patterns 12, 13, the inner conductor patterns 30, 31, and the semi-curing insulating sheet 62 are omitted. .
  • the end force of the dielectric sheet 10 is also a plate-like jig whose bottom surface is narrow along the peak side line P—P ′ and the valley side line Q—Q ′. Fold it while applying.
  • FIG. 11B pressing is performed from both sides of the folded dielectric sheet 10 until the semi-curing insulating sheets (not shown) come into contact with each other.
  • the semi-curable insulating sheet is heated with the pressed state.
  • heat treatment is performed while pressing, so that the semi-curable insulating sheets adhere to each other and the component-embedded board is completed.
  • the built-in component in the present invention is not limited to this.
  • the force with which a conventional substrate creates a zigzag meander wiring in the plane of the wiring layer like the wiring layer 30 in FIG.
  • the wiring folded alternately it is possible to form a circuit equivalent to the meander wiring by considering the cross-sectional force, and it is possible to create an inductor with a compact projected area.
  • a sheet material having a high magnetic permeability as the dielectric sheet of this portion it is possible to realize a high inductance that cannot be achieved conventionally.
  • Embodiment 2 in which a component-embedded substrate in which various components such as electronic components are built using the configuration of the present invention will be described below with reference to FIGS. 12-14.
  • FIGS. 12 and 13 are diagrams showing the configuration of the component-embedded substrate 3 in which the component 80 is built.
  • the component-embedded substrate 3 includes a plurality of dielectric layers 11 each having a partial force superimposed on each other, formed by alternately and continuously folding dielectric sheets 10 having a certain width.
  • the basic configuration is the same as that of the first embodiment.
  • the plurality of dielectric layers 11 are fixed to each other with an insulating adhesive layer 16 formed between the dielectric layers, and a component 80 is disposed between the dielectric layers 11. 80 is covered with an insulating adhesive layer 16. This will be described below.
  • the flat portion 10a is constituted by the connecting portion 11a, and the flat portion 11 and the guiding portion 11a are formed.
  • a region force component storage region ⁇ surrounded by the electric conductor layers 11 and 11 is formed. This part
  • the part 80 is stored in the storage area ⁇ .
  • the component storage area ⁇ in which the component 80 is stored is sealed with the insulating adhesive layer 16.
  • the component 80 is sealed in the component storage area ⁇ .
  • the flat portion 10a is preferably flush with the main surface of the component-embedded substrate 3 where the flat portion 10a is located (main surface 21 in FIG. 12). It can be maximized.
  • the configuration of the other dielectric layer 11 in which the component 80 is not arranged is the same as that of the first embodiment, and the inner conductor patterns 12 and 13 are formed on the surface of the dielectric layer 11, and the component Configures internal wiring of built-in board 3.
  • the external connection electrode 83 of the component 80 is connected to one ends 81a and 82a of the external lead conductor patterns 81 and 82.
  • the other ends 81b and 82b of the external lead conductor patterns 81 and 82 are connected to the connecting part 11a adjacent to the connecting part 11a constituting the flat portion 10a.
  • the external connection electrode 83 of the component 80 stored in the component storage area ⁇ is extracted to the outside of the component built-in substrate 3 via the external lead conductor patterns 81 and 82.
  • part 80 Semiconductor chips, chip capacitors, chip resistors, chip inductors, etc. can be incorporated.
  • FIG. 13 is a diagram showing a configuration in which the electrode of the component 80 is drawn out from each of the one main surface 20 and the other main surface 21 of the component-embedded substrate 3.
  • One external lead electrode 83A of the component built-in board 3 is drawn to one main surface 20 of the component built-in board 3 through one external lead pattern 81 as in FIG. While pressing, the other external extraction electrode 83B is extracted to the other main surface 21 of the component-embedded substrate 3 through the following configuration.
  • the other external lead pattern 82 does not have the other end 82b shown in FIG.
  • An internal conductor pattern 85 for external connection is provided on the surface of the dielectric sheet 10 facing the one end 82a of the external lead electrode 82 across the sheet.
  • the sheet surface on which the external connection internal conductor pattern 85 is provided is located on the main surface 21 side of the component-embedded substrate 3.
  • the internal conductor pattern for external connection 85 and the one end 82a of the external lead electrode 82 are connected to each other through a via hole 35 provided in the dielectric sheet 10.
  • the other external extraction electrode 83 B of the component 80 is connected to the external connection internal conductor pattern 85 and is extracted to the other main surface 21 of the component built-in substrate 3.
  • the component-embedded substrate 3 shown in FIG. 12 or FIG. 13 is formed by alternately folding dielectric sheets by the method shown in FIG. 14- (A) to FIG. 14- (C) and FIG. be able to.
  • FIGS. 14 (A) to 14 (C) are a plan view, a sectional view taken along line BB ′, and a bottom view, respectively, of the dielectric sheet 10 before folding.
  • Fig. 14 (A) and Fig. 14 (C) when folded on both sides of the dielectric sheet 10, the line P-P 'that becomes the peak side and the line Q-Q' that becomes the valley side
  • the internal conductor patterns 12 and 13 constituting the internal wiring are formed in a strip shape along the width direction of the dielectric sheet 10.
  • internal conductor patterns 81 and 82 are formed on the upper surface of the dielectric sheet 10 for leading out the external connection electrodes 83 of the component 80.
  • One ends 81b and 82b of the inner conductor patterns 81 and 82 extend to a position exceeding the peak line ⁇ - ⁇ ′ and function as lead electrodes.
  • the other ends 81a and 82a of the inner conductor patterns 81 and 82 extend to a position exceeding the valley side line Q—Q ′ and function as connection electrodes to the component 80.
  • the component 80 is mounted at a position indicated by a dotted line on the upper surface of the dielectric sheet 10 as shown in FIG. 14 (A).
  • the dielectric sheet 10 thus formed is alternately and continuously folded along the crest-side line P—P ′ and the trough-side line Q—Q ′, so that the component-embedded substrate 3 shown in FIG. Obtainable.
  • the connecting portion 11a of the dielectric sheet 10 on which the component 80 is mounted is folded at an acute angle.
  • the flat portion 10a is formed by being folded into a U shape without being folded.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

L’invention entend proposer un substrat ayant une composante intégrée, permettant d’obtenir à la fois une intégration de composantes haute performance et un câblage haute densité. L’invention concerne un substrat ayant une composante intégrée comprend un substrat (100) où une pluralité de couches diélectriques (11) disposées le long d’une direction opposée aux deux plans principaux du substrat sont empilées dans une direction plane du substrat ; et des motifs conducteurs internes (12, 13) disposés sur une surface de la couche diélectrique (11). La composante électronique est constituée des motifs conducteurs internes (12, 13), et la composante électronique est intégrée au substrat (100).
PCT/JP2006/300970 2005-02-09 2006-01-23 Substrat avec composante intégrée et condensateur avec substrat intégré WO2006085436A1 (fr)

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Application Number Priority Date Filing Date Title
JP2005033126 2005-02-09
JP2005-033126 2005-02-09

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WO2006085436A1 true WO2006085436A1 (fr) 2006-08-17

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112333914A (zh) * 2015-11-30 2021-02-05 瑞萨电子株式会社 电子器件

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Publication number Priority date Publication date Assignee Title
JPS58157123A (ja) * 1982-03-12 1983-09-19 松下電器産業株式会社 チツプ状フイルムコンデンサ
JPH02156516A (ja) * 1988-12-08 1990-06-15 Nichicon Corp 直列形コンデンサ
JPH05101977A (ja) * 1991-10-08 1993-04-23 Kenwood Corp フイルムコンデンサおよびその製造方法
WO1999053510A1 (fr) * 1998-04-15 1999-10-21 Energy Storage Systems Pty. Ltd. Dispositifs condensateurs
JP2000306730A (ja) * 1999-04-21 2000-11-02 Fuji Electric Co Ltd 平面型磁気素子
JP2003069181A (ja) * 2001-08-28 2003-03-07 Mitsubishi Electric Corp 電子機器装置及びその製造方法
JP2003292733A (ja) * 2002-04-02 2003-10-15 Mitsui Mining & Smelting Co Ltd プリント配線板の内蔵キャパシタ層形成用の誘電体フィラー含有樹脂及びその誘電体フィラー含有樹脂を用いて誘電体層を形成した両面銅張積層板並びにその両面銅張積層板の製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58157123A (ja) * 1982-03-12 1983-09-19 松下電器産業株式会社 チツプ状フイルムコンデンサ
JPH02156516A (ja) * 1988-12-08 1990-06-15 Nichicon Corp 直列形コンデンサ
JPH05101977A (ja) * 1991-10-08 1993-04-23 Kenwood Corp フイルムコンデンサおよびその製造方法
WO1999053510A1 (fr) * 1998-04-15 1999-10-21 Energy Storage Systems Pty. Ltd. Dispositifs condensateurs
JP2000306730A (ja) * 1999-04-21 2000-11-02 Fuji Electric Co Ltd 平面型磁気素子
JP2003069181A (ja) * 2001-08-28 2003-03-07 Mitsubishi Electric Corp 電子機器装置及びその製造方法
JP2003292733A (ja) * 2002-04-02 2003-10-15 Mitsui Mining & Smelting Co Ltd プリント配線板の内蔵キャパシタ層形成用の誘電体フィラー含有樹脂及びその誘電体フィラー含有樹脂を用いて誘電体層を形成した両面銅張積層板並びにその両面銅張積層板の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112333914A (zh) * 2015-11-30 2021-02-05 瑞萨电子株式会社 电子器件
CN112333914B (zh) * 2015-11-30 2023-08-08 瑞萨电子株式会社 电子器件

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