WO2006077650A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- WO2006077650A1 WO2006077650A1 PCT/JP2005/000875 JP2005000875W WO2006077650A1 WO 2006077650 A1 WO2006077650 A1 WO 2006077650A1 JP 2005000875 W JP2005000875 W JP 2005000875W WO 2006077650 A1 WO2006077650 A1 WO 2006077650A1
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- resistance layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 40
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 229910021332 silicide Inorganic materials 0.000 claims description 24
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- 125000006850 spacer group Chemical group 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 15
- 229910052710 silicon Inorganic materials 0.000 claims description 15
- 239000010703 silicon Substances 0.000 claims description 15
- 150000004767 nitrides Chemical class 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 238000009751 slip forming Methods 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 230000015654 memory Effects 0.000 abstract description 45
- 230000002093 peripheral effect Effects 0.000 abstract description 25
- 239000010408 film Substances 0.000 description 174
- 239000010410 layer Substances 0.000 description 165
- 238000005468 ion implantation Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000004380 ashing Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- -1 Metal Oxide Nitride Chemical class 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910017052 cobalt Inorganic materials 0.000 description 2
- 239000010941 cobalt Substances 0.000 description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000009477 glass transition Effects 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229920003209 poly(hydridosilsesquioxane) Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- the present invention relates to a nonvolatile memory and a manufacturing method thereof, and more particularly to a nonvolatile memory having an ONO (Oxide Nitride Oxide) film and a manufacturing method thereof.
- ONO Oxide Nitride Oxide
- nonvolatile memories which are semiconductor devices capable of rewriting data
- technical development for the purpose of miniaturization of the memory cell is being promoted in order to increase the storage capacity.
- a floating gate type flash memory that accumulates electric charges in a floating gate has been widely used.
- memory cells become more miniaturized to achieve higher storage densities, it becomes difficult to design floating gate flash memories.
- a thin film of tunnel oxide film is required.
- the leakage current flowing through the tunnel oxide film increases, and when the charge accumulated in the floating gate disappears due to the introduction of defects in the tunnel oxide film, a failure in reliability occurs. This is because of this.
- MONOS Metal Oxide Nitride Oxide Silicon
- SONOS MONOS (Metal Oxide Nitride Oxide Silicon) type and SONOS
- flash memory power S with ONide (Oxide / Nitride / Oxide) film such as (Silicon Oxide Nitride Oxide Silicon) type.
- This is a flash memory that accumulates charges in a silicon nitride film layer called a trap layer sandwiched between silicon oxide film layers.
- This flash memory stores charges in the silicon nitride film layer, which is an insulating film, so even if there is a defect in the tunnel oxide film, the charge does not disappear as in the floating gate type.
- multi-valued bits can be stored in the trap layer of the same memory cell, which is advantageous for increasing the storage capacity of the nonvolatile memory.
- FIG. 1 (a) to FIG. 1 (d) are sectional views showing a conventional flash memory and a manufacturing method thereof.
- the flash memory includes a memory cell and a peripheral circuit. The left side of the drawing shows a memory cell region, and the right side shows a peripheral circuit region.
- a first silicon oxide film layer 110 that is a tunnel oxide film, a silicon nitride film layer 112 that is a trap layer, and a protective film for implantation are formed on a P-type silicon semiconductor substrate 100.
- a third silicon oxide film layer 114 is formed.
- a photoresist 120 is applied, and a bit line and a source / drain region forming region opening 140 in the memory cell region are formed using a general exposure technique.
- the dimension of the opening 140 is L11.
- FIG. 1 (b) for example, arsenic (As) is ion-implanted into the bit line and the source ′ / drain region, and heat treatment is performed, so that the N type Resistive layer 150 is formed.
- the dimension of the low resistance layer 150 is L12. Further, a portion sandwiched between a pair of source and drain regions 150 becomes a channel region 156.
- the third silicon oxide film layer 114 that is a protective film is removed, and a second silicon oxide film layer 116 is formed.
- the second silicon oxide film 116, the silicon nitride film layer 112, and the first silicon oxide film layer 110 in the peripheral circuit region are removed. Thereafter, a fourth silicon oxide film layer 170 serving as a gate oxide film is formed in the peripheral circuit formation region. Further, a polycrystalline silicon film layer that forms the gate metal 182 of the peripheral circuit, the control gate of the memory cell, and the word line 180 is formed. Thereafter, memory cells and peripheral circuits are formed by a general manufacturing method, and a flash memory having an ONO film is completed.
- Patent Document 1 discloses a flash memory having a ⁇ M ⁇ film, which is provided with a metal silicide layer on a part of a bit line for the purpose of reducing the resistance value of the bit line.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2002-170891
- the dimension L12 is larger than the dimension L11 of the opening 140 of the photoresist 120 by the lateral spread of the ion implantation.
- Dimensions of opening 140 Ll l is limited to about half the wavelength of the exposure apparatus. For example, when a commonly used Kr F exposure apparatus is used, it is difficult to make L11 less than lOOnm. Therefore, it is difficult to make L12 below 1 OOnm.
- a first low resistance layer in which a bit line is formed by ion implantation as in Patent Document 1 and a first low resistance layer in contact with the first low resistance layer are formed on a part of the first low resistance layer.
- a second low resistance layer which is a low resistance metal silicide film.
- the second low resistance layer cannot be continuously formed in the direction of current flow. This is incomplete in reducing the resistance of the bit line.
- the metal silicide film is formed between the sidewall control gates, the metal silicide film cannot be formed on the first low resistance layer unless the bit line width is widened. This contradicts the demand for miniaturization.
- a memory cell cannot be completed unless two polycrystalline silicon film layers are formed.
- the gate in the peripheral circuit region is formed by one layer of polycrystalline silicon film, a structure that requires two layers of polycrystalline silicon film in the memory cell has a problem when the manufacturing process of the peripheral circuit becomes complicated. .
- an object of the present invention is to solve the above-described problems, prevent the resistance of the bit line from being increased, enable the memory cell to be miniaturized, and easily manufacture the peripheral circuit and its manufacturing method. Is to provide.
- the present invention relates to a semiconductor substrate, a NO (oxide film Z nitride film / oxide film) film formed on the semiconductor substrate, a control gate disposed on the ONO film, and the semiconductor substrate.
- a bit line having a first low-resistance layer formed on the first low-resistance layer, and a second low-resistance layer formed in contact with the first low-resistance layer and continuously formed in the direction of current flow
- the second low resistance layer is a semiconductor device having a sheet resistance smaller than that of the first low resistance layer.
- the resistance of the bit line can be reduced by continuously providing the bit line with the second low resistance layer having a low sheet resistance in the direction of current flow.
- a semiconductor device which can be reduced in size and miniaturized can be provided.
- the first low resistance layer is an impurity diffusion layer.
- the present invention it is possible to provide a semiconductor device that can simplify the manufacturing process by using an impurity diffusion layer as the first low-resistance layer.
- the second low resistance layer may have a metal silicide film layer.
- a semiconductor device having a low bit line resistance can be provided.
- the second low-resistance layer may have a silicon layer that is epitaxially grown.
- the present invention it is possible to provide a semiconductor device having a low bit line resistance by using a silicon layer grown by low resistance and epitaxial growth for a bit line.
- the present invention includes a word line connected to the control gate, and the control gate and the word line are integrally formed of one polycrystalline silicon layer. S can.
- a memory cell can be formed by a single layer of a polycrystalline silicon film. Therefore, by using this polycrystalline silicon film as a gate metal of a peripheral circuit, a semiconductor in which the manufacturing process of the peripheral circuit is simplified. An apparatus can be provided.
- the present invention may be configured such that the bit line and the control gate are insulated only by the upper oxide film of the ONO film.
- control gate and the bit line are insulated by the high-quality silicon oxide film layer, it is possible to provide a semiconductor device having good insulation characteristics with a simple configuration.
- the present invention further includes a step of forming a NO (oxide film Z nitride film Z oxide film) film on the semiconductor substrate, and an opening in which the bit line formation region is selectively removed on the ON film.
- a NO oxide film Z nitride film Z oxide film
- Forming a first low resistance layer by selectively implanting impurities into the silicon substrate in the bit line formation region using the insulating film mask layer as a mask.
- Forming a second low resistance layer having a sheet resistance lower than that of the low resistance layer.
- the bit line resistance can be reduced by providing the bit line with the second low resistance layer having a low sheet resistance, and the bit line size can be reduced and the size can be reduced.
- a method for manufacturing a possible semiconductor device can be provided.
- the step of forming the insulating film mask layer includes a step of reducing the opening size of the opening by forming a spacer on a side surface of the opening.
- the insulating film mask layer is a silicon nitride film.
- the etching selectivity with the upper oxide film of the ONO film can be ensured, so that it is possible to provide a semiconductor device manufacturing method capable of simplifying the manufacturing process.
- a step of removing an upper oxide film of the ONO film, a nitride film of the ONO film, and a first layer under the opening And a step of forming a silicon oxide film layer so as to cover the low resistance layer.
- control gate and the bit line are insulated by the high-quality silicon oxide film layer, it is possible to provide a manufacturing method of a semiconductor device having a simple structure and good insulating characteristics.
- the step of forming the first low-resistance layer is performed after selectively removing the upper oxide film and the nitride film below the ONO film in the ONO film in the bit line formation region. And a step of ion-implanting impurities into the semiconductor substrate.
- the step of forming the first low-resistance layer is ion implantation through the first silicon oxide film, so that the lateral spread due to the ion implantation can be reduced, and further miniaturization can be achieved.
- a method for manufacturing a semiconductor device can be provided.
- the step of forming the second low resistance layer includes a step of forming a metal silicide film layer. According to the present invention, by using a low resistance metal silicide film layer for a bit line, it is possible to provide a method for manufacturing a semiconductor device having a low bit line resistance.
- the present invention includes a step of selectively forming a resin on the metal silicide film layer and a step of removing the insulating film mask layer after the metal silicide film layer formation step.
- the step of forming the second low resistance layer includes a step of epitaxially growing a low resistance silicon layer.
- FIG. 1 (a) to FIG. 1 (d) are cross-sectional views showing a conventional flash memory having a NO film and a manufacturing method thereof.
- FIGS. 2 (a) to 2 (d) are cross-sectional views (part 1) showing the flash memory having the N film of the first embodiment according to the present invention and the manufacturing method thereof.
- FIG. 3 (e) to FIG. 3 (d) are cross-sectional views (part 2) showing the flash memory having the ONO film of the first embodiment according to the present invention and the manufacturing method thereof.
- FIG. 4 (a) to FIG. 4 (c) are cross-sectional views (part 3) showing the flash memory having the ONO film of the first embodiment according to the present invention and the manufacturing method thereof.
- FIGS. 5 (a) to 5 (d) are cross-sectional views showing a flash memory having an ONO film according to a second embodiment of the present invention and a method for manufacturing the same.
- the first embodiment will be described with reference.
- the first embodiment is an embodiment in which a metal silicide film layer is used as the second low resistance layer.
- These drawings are cross-sectional views of the first embodiment. The left side of the figure shows the memory cell region and the right side shows the peripheral circuit region.
- a first silicon oxide film layer 210 that is a tunnel oxide film and a silicon nitride film layer 212 that is a trap layer are formed on a P-type silicon semiconductor substrate 200 by a normal formation method. Sequentially formed.
- the first silicon oxide film layer 210 is deposited by, for example, a thermal oxidation method
- the silicon nitride film layer 212 is deposited by, for example, a CVD method.
- a third silicon oxide film layer 214 is formed as a protective layer for protecting the trap layer during the manufacturing process.
- the third silicon oxide film layer is deposited by at least 1 Onm or more by CVD method using, for example, HTO (High Temperature Oxide) method or TEOS (tetraethylorthosililcate).
- an insulating film mask layer 230 serving as a mask for forming the bit line and the source / drain region is formed.
- the insulating film mask layer 230 is a silicon nitride film formed by, for example, the CVD method, and the thickness thereof is set to a sufficient thickness to prevent ion implantation described later.
- the silicon nitride film By using the silicon nitride film, the insulating film mask layer 230 can be easily removed thereafter, and selectivity with the third silicon oxide film layer 214 can be ensured during the removal.
- a photoresist 220 is applied onto the insulating film mask layer 230, and an opening 240 is formed in the bit line and source / drain regions using a normal exposure method.
- the opening 240 has an opening dimension L21.
- an antireflection film not shown
- the insulating film mask layer 230 is selectively dry etched using the photoresist 220 as a mask to form an opening 242 in the insulating film mask layer 230.
- the opening 242 has an opening dimension L22 that is substantially the same as the opening dimension L21.
- the photoresist 220 is removed by, for example, an ashing method.
- the spacer insulating film is preferably an insulating film having the same film quality as that of the insulating film mask layer 230, for example, a silicon nitride film formed by a CVD method. is there.
- the thickness is determined by the size by which the opening 242 of the insulating film mask layer is reduced.
- the spacer insulating film is etched back to leave the spacer 234 on the side surface of the opening 242 of the insulating film mask layer, thereby forming the opening 244 having the opening dimension L23.
- the method using the spacer 234 is not essential to the present invention, the opening size 244 of the photoresist opening 240 can be formed, and the opening 244 finer than the L21 can be formed, and the bit line can be further miniaturized. Is possible.
- the third silicon oxide film layer 214 and the silicon nitride film layer 212 are selectively etched using the opening 244 as a mask.
- the first low resistance layer 250 is formed in the N-type bit line region and the source / drain region by ion implantation of arsenic (As) and heat treatment.
- the first low resistance layer 250 has a dimension L24. A portion sandwiched between the first low-resistance layers 250 that are the source and drain regions becomes the channel region 256.
- the ion implantation energy can be reduced, and the force S for reducing the lateral spread of ions can be reduced. As a result, a finer bit line can be provided.
- the ion implantation may be performed by a generally known pocket implantation method.
- the first silicon oxide film layer 210 in the opening 244 is etched.
- a metal silicide film layer 252 is formed as a second low resistance film layer on the bit line region and the source / drain region of the opening 244.
- Cobalt silicide can be formed by forming, for example, cobalt (Co) as a metal silicide on the silicon substrate of the opening 244 by, for example, sputtering, and performing heat treatment by, for example, RTA (Rapid Thermal Anneal).
- RTA Rapid Thermal Anneal
- the resin 260 is applied so as to cover the upper surface of the insulating film mask layer 230, the side surface of the opening 244, and the surface of the metal silicide film layer 252 below the opening 244. Apply.
- HSQ hydrogen-silsesquioxane
- the resin 260 is removed by, for example, an ashing method, and the resin buried portion 262 is left in the opening 244.
- the recessed portion 262 is preferably left above the third silicon oxide film layer 214.
- the insulating film mask layer 230 and the spacer 234 are removed by, for example, hot phosphoric acid. Since the side surface facing the opening 244 of the silicon nitride film layer 212 is protected by the resin remaining portion 26 2, the silicon nitride film layer 212 is not easily removed, and the insulating film mask layer 230 and the spacer 234 Can be removed.
- the resin buried portion 262 is removed by, for example, an ashing method
- the third silicon oxide film layer 214 is removed, for example, with a buffered hydrofluoric acid solution.
- a second silicon oxide film layer 216 is formed as a top oxide film layer on the surface of the silicon nitride film layer 212 and the metal silicide film layer 252 below the opening 244 by, for example, the CVD method.
- the formation temperature is preferably a plasma CVD method that is preferably a temperature that prevents oxidation of the metal silicide film layer, for example, 800 ° C. or less.
- the metal silicide film layer 252 and the control gate 280 which are bit lines, can be insulated by using the second silicon oxide film layer having a good film quality that is not exposed to ions at the time of ion implantation. Characteristics can be obtained.
- a fourth silicon oxide film layer 270 is formed as a gate oxide film in the peripheral circuit region.
- a polycrystalline silicon film layer is formed on the surface of the fourth silicon oxide layer 270 in the peripheral circuit region and on the surface of the second silicon oxide film layer in the memory cell region.
- the polycrystalline silicon layer is used as the control gate and word line 280 in the memory cell region, and is used as the gate electrode 282 in the peripheral circuit region.
- the dimension L24 of the first low resistance layer 250 in the bit line region is larger than the dimension L23 of the opening 244 of the spacer by the lateral spread of the ion implantation.
- the dimension L23 of the spacer opening 244 can be made smaller by about the width of the spacer than the dimension L21 of the photoresist opening. From this, it is a case where the usual KrF exposure equipment is used. Therefore, miniaturization is possible to less than lOOnm.
- the opening 244 is formed using the insulating film as a mask, the metal silicide film layer 252 can be formed by using a high-temperature process in which the photoresist exceeds the glass transition temperature. As a result, the resistance of the bit line can be prevented from being increased, and the bit line can be easily miniaturized.
- the memory cell is formed of one polycrystalline silicon film layer, it can be shared with the gate electrode of the peripheral circuit, and the manufacturing process of the peripheral circuit can be easily performed.
- a low resistance silicon layer epitaxially grown is used as the second low resistance layer.
- FIG. 5A to FIG. 5D are cross-sectional views of the second embodiment. The left side of the figure shows the memory cell area and the right side shows the peripheral circuit area.
- FIG. 5 (a) is the same diagram as FIG. 3 (a) of the first embodiment, and FIG. 2 (a), FIG. 2 (d) and FIG. 3 of the first embodiment. It is manufactured by the same manufacturing process as (a).
- 300 is a silicon semiconductor substrate
- 310 is a first silicon oxide film layer that is a tunnel oxide film
- 312 is a silicon nitride film layer that is a trap layer
- 314 is a third silicon oxide film layer that is a protective film
- 334 is a spacer
- 344 is an opening for forming a bit line region and a source'drain region
- 350 is an N-type bit line and source'drain region formed by ion implantation
- the first low-resistance layer 356 is a channel region.
- the second low-resistance layer doped with, for example, arsenic (As) or phosphorus (P) is formed on the first low-resistance layer below the opening 344 by an epitaxy method.
- Resistive layer 352 is grown.
- the second low resistance layer is not formed on the insulating film mask 330 and the spacer 334, which are insulating films.
- the second low resistance layer 352 is carried up to the upper part of the third silicon oxide film layer 314. Thereafter, the insulating film mask layer 330 and the spacer 334 are removed with, for example, hot phosphoric acid.
- the silicon nitride film layer 312 is removed when the insulating film mask layer 330 and the spacer 334 are removed. There is nothing. Therefore, the insulating film mask layer 330 and the spacer 334 can be easily removed without forming the resin stagnation part 262 as in the first embodiment.
- the third silicon oxide film layer 314 that is a protective film is removed with, for example, a buffered hydrofluoric acid solution, and the upper portion of the second low-resistance layer 352 is covered with the first oxidation film. Etching is performed up to the thickness of the insulating film layer 310. Thereafter, a second silicon oxide film layer 316 is formed as a top oxide film.
- FIG. 5D a flash memory that works in the second embodiment is completed by performing the same manufacturing process as in FIG. 4C of the first embodiment.
- 370 is a fourth silicon oxide film layer which is a gate oxide film in the peripheral circuit region
- 380 is a control gate and word line in the memory cell region
- 382 is a gate electrode in the peripheral circuit region.
- the resistance of the bit line can be reduced by the second low resistance layer 352, the bit line can be miniaturized, and the peripheral circuit can be reduced.
- the power S can be easily manufactured.
- the second embodiment than in the first embodiment use of the resin 260 Re, certain advantages force s that Rukoto Nag can be removed easily insulating mask layer 330 and the spacer 334.
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
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- Toxicology (AREA)
- Health & Medical Sciences (AREA)
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Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2005800469704A CN100552921C (zh) | 2005-01-24 | 2005-01-24 | 半导体装置及其制造方法 |
DE112005003421T DE112005003421T5 (de) | 2005-01-24 | 2005-01-24 | Halbleiterbauelement und Verfahren zu dessen Herstellung |
PCT/JP2005/000875 WO2006077650A1 (ja) | 2005-01-24 | 2005-01-24 | 半導体装置及びその製造方法 |
GB0714070A GB2436271B (en) | 2005-01-24 | 2005-01-24 | Semiconductor device and fabrication method thereof |
JP2006553806A JP4918367B2 (ja) | 2005-01-24 | 2005-01-24 | 半導体装置及びその製造方法 |
US11/338,956 US8901637B2 (en) | 2005-01-24 | 2006-01-24 | Semiconductor memory device having lowered bit line resistance |
US14/540,803 US9496275B2 (en) | 2005-01-24 | 2014-11-13 | Semiconductor memory device having lowered bit line resistance |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2005/000875 WO2006077650A1 (ja) | 2005-01-24 | 2005-01-24 | 半導体装置及びその製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/338,956 Continuation US8901637B2 (en) | 2005-01-24 | 2006-01-24 | Semiconductor memory device having lowered bit line resistance |
Publications (1)
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WO2006077650A1 true WO2006077650A1 (ja) | 2006-07-27 |
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PCT/JP2005/000875 WO2006077650A1 (ja) | 2005-01-24 | 2005-01-24 | 半導体装置及びその製造方法 |
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Country | Link |
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US (2) | US8901637B2 (ja) |
JP (1) | JP4918367B2 (ja) |
CN (1) | CN100552921C (ja) |
DE (1) | DE112005003421T5 (ja) |
GB (1) | GB2436271B (ja) |
WO (1) | WO2006077650A1 (ja) |
Families Citing this family (3)
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JP6363431B2 (ja) * | 2014-08-27 | 2018-07-25 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US9991329B2 (en) | 2016-07-13 | 2018-06-05 | Texas Instruments Incorporated | Method and structure for dual sheet resistance trimmable thin film resistors at same level |
CN107958908B (zh) * | 2017-11-21 | 2020-04-10 | 上海华力微电子有限公司 | Sonos器件的形成方法 |
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JPH10189966A (ja) * | 1996-12-26 | 1998-07-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2000031436A (ja) * | 1998-07-09 | 2000-01-28 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
JP2001118944A (ja) * | 1999-10-05 | 2001-04-27 | Samsung Electronics Co Ltd | 自己整合されたトレンチを有するフラッシュメモリ及びその製造方法 |
JP2003258134A (ja) * | 2002-03-06 | 2003-09-12 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2003338566A (ja) * | 2002-05-21 | 2003-11-28 | Fujitsu Ltd | 不揮発性半導体記憶装置及びその製造方法 |
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US5284784A (en) * | 1991-10-02 | 1994-02-08 | National Semiconductor Corporation | Buried bit-line source-side injection flash memory cell |
JPH11220112A (ja) * | 1998-01-30 | 1999-08-10 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP3219051B2 (ja) * | 1998-05-08 | 2001-10-15 | 日本電気株式会社 | 半導体装置の製造方法 |
US6177340B1 (en) * | 1999-02-18 | 2001-01-23 | Taiwan Semiconductor Manufacturing Company | Method to reduce contact hole aspect ratio for embedded DRAM arrays and logic devices, via the use of a tungsten bit line structure |
JP2002170891A (ja) | 2000-11-21 | 2002-06-14 | Halo Lsi Design & Device Technol Inc | デュアルビット多準位バリスティックmonosメモリの製造、プログラミング、および動作のプロセス |
US6465306B1 (en) * | 2000-11-28 | 2002-10-15 | Advanced Micro Devices, Inc. | Simultaneous formation of charge storage and bitline to wordline isolation |
US6897514B2 (en) * | 2001-03-28 | 2005-05-24 | Matrix Semiconductor, Inc. | Two mask floating gate EEPROM and method of making |
TW480677B (en) * | 2001-04-04 | 2002-03-21 | Macronix Int Co Ltd | Method of fabricating a nitride read only memory cell |
JP4147765B2 (ja) * | 2001-06-01 | 2008-09-10 | ソニー株式会社 | 不揮発性半導体メモリ装置およびその電荷注入方法 |
TW503509B (en) * | 2001-10-29 | 2002-09-21 | Macronix Int Co Ltd | Manufacture method of substrate/oxide nitride/oxide/silicon device |
US6828199B2 (en) * | 2001-12-20 | 2004-12-07 | Advanced Micro Devices, Ltd. | Monos device having buried metal silicide bit line |
JP4030839B2 (ja) * | 2002-08-30 | 2008-01-09 | スパンション エルエルシー | メモリ集積回路装置の製造方法 |
US7256112B2 (en) * | 2005-01-20 | 2007-08-14 | Chartered Semiconductor Manufacturing, Ltd | Laser activation of implanted contact plug for memory bitline fabrication |
-
2005
- 2005-01-24 CN CNB2005800469704A patent/CN100552921C/zh not_active Expired - Fee Related
- 2005-01-24 DE DE112005003421T patent/DE112005003421T5/de not_active Ceased
- 2005-01-24 WO PCT/JP2005/000875 patent/WO2006077650A1/ja not_active Application Discontinuation
- 2005-01-24 JP JP2006553806A patent/JP4918367B2/ja not_active Expired - Fee Related
- 2005-01-24 GB GB0714070A patent/GB2436271B/en not_active Expired - Fee Related
-
2006
- 2006-01-24 US US11/338,956 patent/US8901637B2/en not_active Expired - Fee Related
-
2014
- 2014-11-13 US US14/540,803 patent/US9496275B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH10189966A (ja) * | 1996-12-26 | 1998-07-21 | Toshiba Corp | 半導体装置及びその製造方法 |
JP2000031436A (ja) * | 1998-07-09 | 2000-01-28 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
JP2001118944A (ja) * | 1999-10-05 | 2001-04-27 | Samsung Electronics Co Ltd | 自己整合されたトレンチを有するフラッシュメモリ及びその製造方法 |
JP2003258134A (ja) * | 2002-03-06 | 2003-09-12 | Seiko Epson Corp | 半導体装置の製造方法 |
JP2003338566A (ja) * | 2002-05-21 | 2003-11-28 | Fujitsu Ltd | 不揮発性半導体記憶装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
GB0714070D0 (en) | 2007-08-29 |
JP4918367B2 (ja) | 2012-04-18 |
GB2436271A (en) | 2007-09-19 |
US20150072497A1 (en) | 2015-03-12 |
US8901637B2 (en) | 2014-12-02 |
CN101103456A (zh) | 2008-01-09 |
CN100552921C (zh) | 2009-10-21 |
US9496275B2 (en) | 2016-11-15 |
GB2436271B (en) | 2010-06-16 |
US20060244037A1 (en) | 2006-11-02 |
DE112005003421T5 (de) | 2008-01-17 |
JPWO2006077650A1 (ja) | 2008-08-07 |
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