WO2006070685A1 - トンネル酸化膜の窒化処理方法、不揮発性メモリ素子の製造方法および不揮発性メモリ素子、ならびに制御プログラムおよびコンピュータ読取可能な記憶媒体 - Google Patents
トンネル酸化膜の窒化処理方法、不揮発性メモリ素子の製造方法および不揮発性メモリ素子、ならびに制御プログラムおよびコンピュータ読取可能な記憶媒体 Download PDFInfo
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
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- H10D64/01—Manufacture or treatment
- H10D64/031—Manufacture or treatment of data-storage electrodes
- H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
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- H—ELECTRICITY
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- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6302—Non-deposition formation processes
- H10P14/6319—Formation by plasma treatments, e.g. plasma oxidation of the substrate
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6518—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer
- H10P14/6524—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen
- H10P14/6526—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by introduction of substances into an already-existing insulating layer the substance being nitrogen introduced into an oxide material, e.g. changing SiO to SiON
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
- H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
- H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
- H10P14/6532—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour by exposure to a plasma
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
- H10P14/662—Laminate layers, e.g. stacks of alternating high-k metal oxides
Definitions
- the present invention relates to a method for nitriding a tunnel oxide film in a nonvolatile memory element, a method for manufacturing a nonvolatile memory element using the same, a nonvolatile memory element, and a control for executing the nitriding method
- the present invention relates to a program and a computer-readable storage medium.
- nitriding treatment has been performed on a tunnel oxide film for the purpose of improving memory characteristics.
- a heat treatment is conventionally known (for example, Patent Documents 1 and 2 below).
- the nitriding process proceeds in a thermally balanced state, and therefore the position and concentration of the formed nitriding region, that is, the nitrogen profile is substantially specified. Specifically, the position of the nitriding region is specified at the interface with the substrate, and the peak density of N has an upper limit of approximately 10 21 atoms / cm 3 .
- Patent Document 1 JP-A-5-198573
- Patent Document 2 Japanese Patent Laid-Open No. 2003-188291
- Still another object of the present invention is to provide a control program and a computer-readable storage medium for executing the nitriding method.
- a tunnel oxide film nitriding method comprising: forming a nitride region on a surface portion of the tunnel oxide film.
- a tunnel oxide film is formed on a silicon substrate, and a plasma treatment using a processing gas containing nitrogen gas is used to nitride the surface portion of the tunnel oxide film.
- a processing gas containing nitrogen gas is used to nitride the surface portion of the tunnel oxide film.
- a method for manufacturing a non-volatile memory device comprising forming a sidewall oxide film on the sidewalls of the floating gate and the control gate.
- a silicon substrate, a tunnel oxide film formed on the silicon substrate, a floating gate formed on the tunnel oxide film, and the floating gate described above A non-volatile memory device comprising: a dielectric film formed on the substrate; a control gate formed on the dielectric film; and a sidewall oxide film formed on the sidewalls of the floating gate and the control gate.
- the tunnel oxide film can be provided with a nonvolatile memory element having a nitride region formed by plasma treatment using a treatment gas containing a nitrogen gas on a surface portion thereof.
- a substrate that operates on a computer and at the time of execution has a tunnel oxide film formed thereon for forming a nonvolatile memory element, and includes nitrogen gas.
- Control that causes a computer to control the plasma processing apparatus so as to perform a tunnel oxide film nitriding method that includes forming a nitrided region on the surface portion of the tunnel oxide film by plasma processing using a processing gas.
- a program is provided.
- a control program that operates on a computer is stored.
- a computer-readable storage medium
- the control program during execution, prepares a substrate on which a tunnel oxide film is formed in order to form a nonvolatile memory element, and performs plasma processing using a processing gas containing nitrogen gas, thereby forming the tunnel oxide film.
- a computer-readable storage medium is provided that causes a computer to control a plasma processing apparatus such that a method of nitriding a tunnel oxide film having a nitride region formed on a surface portion is performed.
- the plasma processing may be performed using a plasma processing apparatus that generates plasma by introducing a microwave into a processing chamber using a planar antenna having a plurality of slots. it can.
- a gas containing a rare gas can be used, and the rare gas is preferably Ar gas.
- the N dose amount of the nitride region is preferably l X 10 15 atoms / cm 2 or more.
- the plasma treatment is preferably performed at a pressure of 6.7 to 266 Pa.
- the nitriding region is formed using a plasma processing apparatus that generates plasma by introducing microwaves into a processing chamber using a planar antenna having a plurality of slots.
- the nitriding region can be formed by plasma treatment using a processing gas containing nitrogen gas and a rare gas, and the rare gas is preferably Ar gas.
- the N dose amount of the nitride region is l X 10 15 atoms / cm 2 or more.
- the tunnel oxide film is formed by plasma treatment using a treatment gas containing nitrogen gas, the degree of freedom of the nitrogen profile can be increased as compared with the case of nitriding treatment by heat treatment.
- a nitride region having a higher nitrogen concentration can be formed on the surface portion of the tunnel oxide film than in the case of heat treatment. For this reason, trap sites existing on the surface of the tunnel oxide film can be terminated with nitrogen, so that traps generated in the oxide film during memory operation can be reduced, and the film quality of the tunnel oxide film is good. Can be held in.
- the nitriding region functions as an oxidant barrier, which prevents the formation of illegal oxidation (parsbeak) at the tunnel oxide film interface edge of the floating gate, and data retention The characteristics can be improved. Furthermore, a nitride region with a high dielectric constant is formed on the surface of the tunnel oxide film.
- Equivalent film thickness EOT: Equivalent
- Oxide Thickness can be reduced, and the data retention characteristics can be improved without changing the interface characteristics.
- the tunnel oxide film can be thickened, and the leakage current can be suppressed accordingly, so that the data retention characteristic can be improved as a result.
- FIG. 1A is a view for explaining an example of the steps of a tunnel oxide film nitriding method according to the present invention.
- FIG. 1B is a view for explaining an example of the steps of the tunnel oxide film nitriding method according to the present invention.
- FIG. 2 is a cross-sectional view showing an example of a memory cell of a nonvolatile memory element to which nitriding treatment according to the present invention is applied.
- FIG. 3 is a cross-sectional view schematically showing an example of a plasma processing apparatus for carrying out the tunnel oxide film nitriding method according to the present invention.
- FIG. 4 is a diagram showing the structure of a planar antenna member used in the microwave plasma apparatus of FIG.
- FIG. 5 is a flowchart for explaining the sequence of nitriding treatment.
- FIG. 6A is a view showing a nitrogen profile of a thermal oxide film after performing thermal nitriding treatment.
- FIG. 6B is a view showing a nitrogen profile of a thermal oxide film after plasma nitriding treatment.
- FIG. 7 is a graph showing the nitrogen concentration distribution of the tunnel oxide film when plasma nitriding is actually performed.
- FIG. 8A is a schematic diagram for explaining a state in which traps are generated in a tunnel oxide film due to a conventional memory operation.
- FIG. 8B is a schematic diagram for explaining an effect of preventing trap generation in the tunnel oxide film by the tunnel oxide film nitriding method according to one embodiment of the present invention.
- FIG. 9A is a diagram for explaining a state in which a parse beak is generated by nitriding of a conventional tunnel oxide film.
- FIG. 9B shows a bird's-eye by the tunnel oxide film nitriding method according to the embodiment of the present invention. The figure for demonstrating a cake suppression effect.
- FIG. 10 shows the electric field E (MV / cm) applied in the thickness direction of the oxide film when the nitriding treatment according to an embodiment of the present invention is performed by changing the dose and the base oxide film that is not nitrided. diagram showing the relationship between the leak electric g (AZcm 2).
- FIG. 11 is a diagram showing FN plots in the case of performing a nitriding treatment according to an embodiment of the present invention while changing the dose with a base oxide film that is not nitrided.
- FIG. 12 A diagram showing the relationship between the EOT of the tunnel oxide film and the flat band voltage Vfb when the nitridation process according to this embodiment is performed with the base oxide film not nitrided and the dose changed. .
- FIG. 1 is a cross-sectional view for explaining a tunnel oxide film nitriding method according to the present invention. This nitriding treatment is performed as a part of a manufacturing process of a non-volatile memory device such as EPR ⁇ M, EEPR ⁇ M, or flash memory.
- a non-volatile memory device such as EPR ⁇ M, EEPR ⁇ M, or flash memory.
- a tunnel with a thickness of about 10 nm is formed on the main surface of the Si substrate 101 by, for example, a thermal oxidation process of the Si substrate 101.
- An oxide film 102 is formed, and then predetermined ion implantation is performed on the main surface region of the Si substrate 101, followed by nitriding treatment on the tunnel oxide film 102.
- the nitriding process is performed by a plasma process using a gas containing nitrogen gas, whereby a nitride region 103 is formed on the surface portion of the tunnel oxide film 102 as shown in FIG. 1B.
- the nitrogen profile in the tunnel oxide film 102 can be controlled, and the nitride region 103 is tunnel-oxidized. It can be formed on the surface portion of the film 102 with a high nitrogen concentration. Specifically, the nitride region 103 can be formed in a surface portion close to the pole surface from the surface of the tunnel oxide film 102 to a portion of 2 nm or less.
- the sidewalls of the floating gate 104 and the control gate 109 have a structure in which a sidewall oxide film 111 is formed by oxidation treatment.
- a polysilicon film to be a floating gate 104 is formed on the tunnel oxide film 102 that has been subjected to plasma nitriding, and an oxide film, a nitride film, and an oxide film are sequentially formed thereon, and a control gate 109 is further formed thereon.
- a polysilicon film or a laminated film of polysilicon and tungsten silicide is formed. The film formation at this time is performed by, for example, CVD.
- dry etching is performed by plasma using a photoresist layer and a hard mask layer 110 (not shown) as a mask to form the floating gate 104, the dielectric film 108 having an ONO structure, and the control gate 109, and then the floating gate 104.
- the exposed portion of the polysilicon in the control gate 109 is oxidized to form a sidewall oxide film 111.
- This oxidation treatment can be performed by a thermal oxidation process such as a wet method using a steam generator or a dry method using a gas.
- the plasma processing power of the RLSA (Radial Line Slot Antenna) microwave plasma system which will be described later, is particularly preferred because low-temperature processing is possible with high-density plasma at low electron temperature.
- a nonvolatile memory element having a memory cell having the structure shown in FIG. 2 is formed.
- FIG. 3 is a cross-sectional view schematically showing an example of a plasma processing apparatus for performing the tunnel oxide film nitriding method according to the present invention.
- This plasma processing apparatus 100 is a plane in which a plurality of slots are formed in a predetermined pattern. It is configured as an RLSA microwave plasma processing device that radiates a microphone mouth wave guided from a microwave generation source into the chamber by using an antenna (Radial Line Slot Antenna) to form plasma.
- an antenna Radial Line Slot Antenna
- the plasma processing apparatus 100 is an airtight and grounded substantially cylindrical chamber.
- a circular opening 10 is formed at a substantially central portion of the bottom wall la of the chamber 11, and an exhaust chamber 11 that communicates with the opening 10 and protrudes downward is provided on the bottom wall la. ing.
- a susceptor 2 having a ceramic force such as A1N for horizontally supporting a Si wafer W as a substrate to be processed is provided in the chamber 11.
- the susceptor 2 is supported by a support member 3 made of a ceramic such as a cylindrical A1N that extends upward from the center of the bottom of the exhaust chamber 11.
- a guide ring 4 for guiding the Si wafer W is provided on the outer edge of the susceptor 2.
- the susceptor 2 is loaded with a resistance heating type heater 5.
- the heater 5 is supplied with power from a heater power source 6 to heat the susceptor 2, and the heat is applied to a Si wafer that is an object to be processed. Heat W. At this time, for example, temperature control is possible in the range from room temperature to 800 ° C.
- a cylindrical liner 7 made of a dielectric material such as quartz is provided on the inner periphery of the chamber 11.
- wafer support pins (not shown) for supporting the Si wafer W and raising and lowering it are provided so as to protrude and retract with respect to the surface of the susceptor 2.
- An annular gas introduction member 15 is provided on the side wall of the chamber 11, and a gas supply system 16 is connected to the gas introduction member 15.
- the gas introduction member may be arranged in a shower.
- This gas supply system 16 has an Ar gas supply source 17 and an N gas supply source 18.
- Each gas line 20 is provided with a mass flow controller 21 and front and rear opening / closing valves 22.
- An exhaust pipe 23 is connected to the side surface of the exhaust chamber 11, and an exhaust device 24 including a high-speed vacuum pump is connected to the exhaust pipe 23. Then, by operating the exhaust device 24, the gas force in the chamber 11 is uniformly discharged into the space 11 a of the exhaust chamber 11 and is exhausted through the exhaust pipe 23. As a result, the inside of the chamber 11 can be depressurized at a high speed to a predetermined degree of vacuum, for example, 0.133 Pa.
- a loading / unloading port 25 for loading / unloading the Si wafer W to / from a transfer chamber (not shown) adjacent to the plasma processing apparatus 100 and the loading / unloading port 25 are opened and closed.
- a gate valve 26 is provided.
- the upper portion of the chamber 11 is an opening, and a ring-shaped support 27 is provided along the periphery of the opening, and a dielectric such as quartz or Al 2 O 3 is provided on the support 27. Etc.
- a microwave transmitting plate 28 made of ceramics and transmitting microwaves is hermetically provided through a seal member 29. Therefore, the inside of the chamber 11 is kept airtight.
- a disc-shaped planar antenna member 31 is provided above the microwave transmission plate 28 so as to face the susceptor 2.
- the planar antenna member 31 is locked to the upper end of the support portion 27.
- the planar antenna member 31 is made of a conductor, for example, a copper plate or an aluminum plate whose surface is silver or gold plated, and a plurality of microwave radiation holes (slots) 32 are formed through a predetermined pattern. ing.
- the microwave radiation holes 32 have, for example, a long groove shape as shown in FIG. 4, and are typically orthogonal to each other so that adjacent microwave radiation holes 32 intersect each other (“T”).
- the plurality of microphone mouth wave transmission holes 32 are arranged concentrically. That is, the planar antenna member 31 constitutes an RL SA antenna.
- the length and the arrangement interval of the microwave transmission holes 32 are determined according to the wavelength (e) of the microwave, and are arranged so that the interval between the microwave radiation holes 32 becomes 1/2 or e.g. Further, the microwave radiation hole 32 may have another shape such as a circular shape or an arc shape. Further, the arrangement form of the microwave radiation holes 32 is not particularly limited, and may be arranged in a spiral shape or a radial shape in addition to the concentric shape.
- a slow wave material 33 made of a dielectric having a dielectric constant larger than that of a vacuum is provided on the upper surface of the planar antenna member 31 .
- a shield lid 34 made of a metal material such as aluminum or stainless steel is provided on the upper surface of the chamber 11 so as to cover the planar antenna member 31 and the slow wave material 33.
- the upper surface of the chamber 11 and the shield cover 34 are sealed by a seal member 35.
- a cooling water flow path 34 a is formed in the shield lid 34.
- the shield lid 34 is grounded.
- An opening 36 is formed in the center of the upper wall of the shield lid 34.
- a waveguide 37 is connected.
- a microwave generator 39 is connected to the end of the waveguide 37 via a matching circuit 38. Thereby, for example, a microwave having a frequency of 2.45 GHz generated by the microwave generator 39 is propagated to the planar antenna member 31 through the waveguide 37.
- a microwave frequency 8.35 GHz, 1.98 GHz, or the like can be used.
- the waveguide 37 includes a coaxial waveguide 37a having a circular cross section extending upward from the opening 36 of the shield lid 34, and a rectangular waveguide 37b having a rectangular cross section extending in the horizontal direction. Have. A mode converter 40 is provided between them. An inner conductor 41 extends in the center of the coaxial waveguide 37a, and its lower end is connected and fixed to the center of the planar antenna member 31.
- the process controller 50 includes a user interface including a keyboard on which a process manager inputs commands to manage the plasma processing apparatus 100, a display that visualizes and displays the operating status of the plasma processing apparatus 100, and the like. Ace 51 is connected.
- the process controller 50 includes a control program for realizing various processes executed by the plasma processing apparatus 100 under the control of the process controller 50, and each component of the plasma etching apparatus according to the processing conditions.
- a storage unit 52 that stores a program, that is, a recipe for causing the system to execute processing is connected.
- the recipe may be stored in a hard disk or semiconductor memory, or may be set at a predetermined position in the storage unit 52 while being stored in a portable storage medium such as a CDROM or DVD.
- recipes may be transmitted as appropriate from other devices via, for example, a dedicated line.
- an arbitrary recipe is called from the storage unit 52 according to an instruction from the user interface 51 or the like, and is executed by the process controller 50, thereby controlling the process controller 50.
- a desired process is performed in the plasma processing apparatus 100.
- the gate oxide film 26 is opened and a tunnel oxide film is formed from the loading / unloading port 25.
- the wafer W is loaded into the chamber 1 and placed on the susceptor 2 (step 1).
- the tunnel oxide film is either a wet method using a steam generator or a dry method using gas.
- It is formed with a thickness of 3.5 to 15 nm by a thermal oxidation process.
- a typical example is 10 nm.
- step 2 the inside of the chamber 11 is evacuated (step 2), and Ar gas is supplied from the Ar gas supply source 17 of the gas supply system 16 at a predetermined flow rate.
- the gas is introduced into the chamber 11 through the gas introduction member 15 (step 3).
- the pressure inside the chamber 11 is adjusted by the flow rate of the Ar gas so that the plasma is easily ignited (step 4).
- the pressure at this time is preferably in the range of 13.3 to 267 Pa, and the 66.6 Pa and 126 Pa force sequences are shown. Note that the pressure at this time is set higher than the pressure at the time of nitriding described later.
- microwaves are ignited by radiating microwaves into the chamber 11 (step 5).
- the microwave from the microwave generator 39 is guided to the waveguide 37 through the matching circuit 38.
- Microwaves are sequentially supplied to the planar antenna member 31 through the rectangular waveguide 37b, the mode converter 40, and the coaxial waveguide 37a, and from the planar antenna member 31 through the microwave transmitting plate 28 in the chamber 11. Radiated above the wafer W.
- Ar gas is turned into plasma in the chamber 11 by the microwaves radiated to the chamber 11.
- the microwave power at this time is exemplified by 16 OOW, which is preferably 1000 to 3000 W.
- the pressure inside the chamber 11 is adjusted to 6.7 Pa, for example.
- N gas is supplied from the N gas supply source 18 of the gas supply system 16 to a predetermined amount.
- the gas is introduced into the chamber 11 through the gas introduction member 15 at a flow rate, and the N gas is turned into plasma by the microwave radiated into the chamber 1 (step 6).
- the tunnel oxide film is nitrided (step 7).
- the pressure at this time is preferably 1.3 to 266 Pa, for example 126 Pa.
- the treatment temperature is preferably 200 to 600 ° C, 400. C is exemplified.
- Ar gas 250-3000mL / min (sccm)
- N gas 10-300mL / min (sccm) is preferable
- N gas 40 mL / min (sccm) is exemplified.
- Ar / N is in the range of 1 ⁇ 6 to 300 force S, preferably 10 to: 100 force S. In this case
- the processing time is preferably 240 seconds, preferably 30 to 600 seconds.
- microwave radiation is stopped to extinguish the plasma (step 8), and the gas is stopped while evacuating (step 9). End the sequence.
- the microwave plasma as described above is a low electron temperature plasma having a plasma density of approximately loUZcm 3 or more and 0.5 to 1.5 eV, and tunnel oxidation is performed by the low temperature and short time treatment as described above. It can be controlled so that a nitrided region with a high nitrogen concentration is formed on the surface portion of the film, specifically on the surface portion close to the extreme surface of 2 nm or less from the surface, and plasma damage such as ions on the underlying film There are advantages such as small. In addition, since the nitriding process is performed at a low temperature and in a short time by the high density plasma as described above, the nitrogen profile of the nitriding region can be controlled with high accuracy.
- the nitriding proceeds in a thermally balanced state, so that the position of the nitriding region is specified at the interface portion with the substrate of the tunnel oxide film as shown in FIG. 6A.
- the upper limit of the peak density of nitrogen atoms is approximately 10 21 atoms / cm 3 .
- a high nitrogen concentration in this example, 10 22 A nitride region of atoms Zcm 3
- a region having almost no nitrogen can be formed at the interface with the substrate.
- This nitrogen concentration can be controlled appropriately according to the conditions.
- the position of the nitriding region can be appropriately controlled within the range of 2 nm or less from the surface of the tunnel oxide film by adjusting the conditions.
- FIG. 7 is based on SIMS measurement results when nitriding is actually performed by the method of the present invention. Nitrogen concentration distribution is shown. Figure 7 also shows the SIMS intensity distribution of 0 and Si.
- the equipment shown in Fig. 3 was used, the chamber internal pressure: 126Pa, microwave power: 1600W, Ar flow rate: 1000mL / min (sccm), N flow rate: 40mL / min (sccm) so
- the thickness of the tunnel oxide film is 10 nm. As shown in this figure, it can be seen that a peak of nitrogen concentration exists at a position of about 1 nm from the surface of the tunnel oxide film.
- a high-concentration nitrided region can be formed on the surface of the tunnel oxide film, and a region in which nitrogen does not exist can be formed at the interface with the substrate. Generation of traps formed in the oxide film can be prevented.
- the force in which the trap was generated in the tunnel oxide film 102 due to the memory operation as shown in FIG. 8A
- the nitride region 103 is terminated with nitrogen atoms, the generation of such traps can be reduced, and the film quality of the tunnel oxide film can be maintained well.
- the equivalent oxide thickness (EOT) of the oxide film (SiO) with which Vt (shift in transistor switching voltage) can be increased.
- phosphorous (P) doped in polysilicon is, for example, phosphorous oxide (P
- the nitride region 103 on the surface portion of the tunnel oxide film 102 (the interface portion with the floating gate 104) is formed by performing the plasma nitriding treatment as in this embodiment. It becomes an illegal oxidation barrier, and the oxidation region 104a can be significantly reduced. As a result, the data holding function is increased.
- the dielectric constant can be increased by nitriding the tunnel oxide film 102 and forming the nitride region 103 on the surface portion, the dielectric constant increases as the N dose increases even if the physical film thickness is the same.
- the oxide film (SiO 2) capacitance equivalent film thickness (EOT) can be reduced
- Figure 10 is a base of the oxide film not nitrided, the dose of the nitrogen atom 2. 5 X 10 15, 3. 8 X 10 15, 5. the present embodiment by changing the 2 X 10 15 atoms / cm 2 When nitriding is performed, the electric field E (MV / cm applied in the thickness direction of the oxide film)
- FIG. 3 is a diagram showing the relationship between the leak electric ⁇ (A / cm 2).
- the apparatus shown in Fig. 3 is used, under the conditions of an internal pressure, chamber internal pressure: 126 Pa, microwave power: 1600 W, Ar flow rate: lOOOOmL / min (sccm), N flow rate: 40 mL / min (sccm), Processing time 40
- the base thickness of the tunnel oxide film is 5nm.
- the leakage power g increases abruptly when the electric field E force S9 is exceeded, regardless of the dose of nitrogen atoms. It can be seen that the electric field E increases with the same leakage current g. And this tendency increases as the dose of nitrogen atoms increases. From this, it can be seen that by increasing the EOT by forming a nitrided region, the charge retention function increases, and the effect increases with increasing dose of nitrogen atoms.
- FIG. 11 is a diagram showing FN plots in the case where the base oxide film that is not nitrided and the nitriding treatment according to the present embodiment is performed with the dose varied under the same conditions as in FIG.
- the slopes of the straight lines are the same both when nitriding is not performed and when nitriding is performed, and it is understood that the barrier height does not change even when nitriding is performed. In other words, even if nitriding is performed, the essential function of the device does not change.
- FIG. 12 shows the EOT and flat band voltage of the tunnel oxide film when the nitriding process according to the present embodiment is performed with the base oxide film not nitrided and the dose changed under the same conditions as in FIG. It is a figure which shows the relationship with Vfb.
- the flat band voltage Vfb does not change much even when nitriding is performed. That is, as in the present invention, the nitrided region is formed on the surface portion close to the extreme surface from the surface of the tunnel oxide film to 2 nm or less, and almost no nitrogen is introduced into the interface portion, so that the interface characteristics are mostly reduced. It was confirmed that there was no change.
- the EOT can be reduced without changing the essential function and interface characteristics of the device. It can be seen that the data holding function can be raised. If the EOT is the same, the tunnel oxide film can be thickened by nitriding, and the leakage current can be suppressed accordingly, so that the data retention characteristics can be improved as a result. .
- a plasma processing apparatus that uses a planar antenna having a plurality of slots to propagate microwaves into the chamber and forms high-density plasma at a low electron temperature is used as the processing apparatus.
- Other plasma processing apparatuses such as an inductively coupled plasma processing apparatus, a plane reflected wave plasma processing apparatus, and a magnetron plasma processing apparatus may be used.
- the structure and manufacturing process of the nonvolatile memory element are not limited to those described above, and any structure may be used.
- Ar is used as an inert gas
- other inert gases He, Ne, Kr, Xe
- Ar gas is particularly preferable.
- the present invention contributes to improvement of memory characteristics of nonvolatile memory elements such as EPROM, EEPROM®, and flash memory.
Landscapes
- Semiconductor Memories (AREA)
- Formation Of Insulating Films (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
Claims
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200580045366XA CN101095224B (zh) | 2004-12-28 | 2005-12-22 | 隧道氧化膜的氮化处理方法、非易失性存储元件的制造方法和非易失性存储元件,以及控制程序和计算机可读取的存储介质 |
| US11/813,043 US20080093658A1 (en) | 2004-12-28 | 2005-12-22 | Method for Nitriding Tunnel Oxide Film, Method for Manufacturing Non-Volatile Memory Device, Non-Volatile Memory Device, Control Program and Computer-Readable Recording Medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004-380705 | 2004-12-28 | ||
| JP2004380705A JP2006186245A (ja) | 2004-12-28 | 2004-12-28 | トンネル酸化膜の窒化処理方法、不揮発性メモリ素子の製造方法および不揮発性メモリ素子、ならびにコンピュータプログラムおよび記録媒体 |
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| WO2006070685A1 true WO2006070685A1 (ja) | 2006-07-06 |
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| PCT/JP2005/023597 Ceased WO2006070685A1 (ja) | 2004-12-28 | 2005-12-22 | トンネル酸化膜の窒化処理方法、不揮発性メモリ素子の製造方法および不揮発性メモリ素子、ならびに制御プログラムおよびコンピュータ読取可能な記憶媒体 |
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| US (1) | US20080093658A1 (ja) |
| JP (1) | JP2006186245A (ja) |
| KR (1) | KR20070086697A (ja) |
| CN (2) | CN101834133B (ja) |
| TW (1) | TWI390632B (ja) |
| WO (1) | WO2006070685A1 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7825018B2 (en) * | 2006-02-28 | 2010-11-02 | Tokyo Electron Limited | Plasma oxidation method and method for manufacturing semiconductor device |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20090025780A (ko) * | 2007-09-07 | 2009-03-11 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
| JP5232425B2 (ja) * | 2007-09-10 | 2013-07-10 | ルネサスエレクトロニクス株式会社 | 不揮発性半導体記憶装置およびその製造方法 |
| KR100933835B1 (ko) * | 2007-11-12 | 2009-12-24 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
| US20090309150A1 (en) * | 2008-06-13 | 2009-12-17 | Infineon Technologies Ag | Semiconductor Device And Method For Making Semiconductor Device |
| US8501610B2 (en) | 2009-04-28 | 2013-08-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-volatile memories and methods of fabrication thereof |
| JP4977180B2 (ja) | 2009-08-10 | 2012-07-18 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
| CN104733296B (zh) * | 2013-12-24 | 2017-12-12 | 北京兆易创新科技股份有限公司 | 一种快闪存储器隧道绝缘层的制作方法 |
| KR102263315B1 (ko) | 2014-08-06 | 2021-06-15 | 삼성전자주식회사 | 반도체 장치 및 반도체 장치의 제조방법 |
| CN104766827A (zh) * | 2015-03-31 | 2015-07-08 | 上海华力微电子有限公司 | 一种提高nor闪存数据保存能力的方法 |
| CN104992902A (zh) * | 2015-05-27 | 2015-10-21 | 上海华力微电子有限公司 | 一种提高隧道氧化层可靠性的方法 |
| CN105206581B (zh) * | 2015-08-31 | 2018-10-16 | 上海华力微电子有限公司 | 一种sonos器件中ono结构的制造方法 |
| JP7173082B2 (ja) * | 2020-04-17 | 2022-11-16 | 信越半導体株式会社 | 気相成長用のシリコン単結晶基板、気相成長基板及びこれらの製造方法 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004047614A (ja) * | 2002-07-10 | 2004-02-12 | Innotech Corp | トランジスタとそれを用いた半導体メモリ、およびトランジスタの製造方法 |
| JP2004087865A (ja) * | 2002-08-28 | 2004-03-18 | Hitachi Ltd | 半導体装置の製造方法 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4762728A (en) * | 1985-04-09 | 1988-08-09 | Fairchild Semiconductor Corporation | Low temperature plasma nitridation process and applications of nitride films formed thereby |
| US5273587A (en) * | 1992-09-04 | 1993-12-28 | United Solar Systems Corporation | Igniter for microwave energized plasma processing apparatus |
| JP3558565B2 (ja) * | 1999-11-08 | 2004-08-25 | Necエレクトロニクス株式会社 | 不揮発性半導体装置の製造方法 |
| DE10065976A1 (de) * | 2000-02-25 | 2002-02-21 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterbauelements |
| US6413881B1 (en) * | 2000-03-09 | 2002-07-02 | Lsi Logic Corporation | Process for forming thin gate oxide with enhanced reliability by nitridation of upper surface of gate of oxide to form barrier of nitrogen atoms in upper surface region of gate oxide, and resulting product |
| US6559007B1 (en) * | 2000-04-06 | 2003-05-06 | Micron Technology, Inc. | Method for forming flash memory device having a tunnel dielectric comprising nitrided oxide |
| JP4799748B2 (ja) * | 2001-03-28 | 2011-10-26 | 忠弘 大見 | マイクロ波プラズマプロセス装置、プラズマ着火方法、プラズマ形成方法及びプラズマプロセス方法 |
| WO2003015151A1 (fr) * | 2001-08-02 | 2003-02-20 | Tokyo Electron Limited | Procede de traitement d'un materiau de base et materiau d'utlisation de dispositif electronique |
| US6586313B2 (en) * | 2001-11-29 | 2003-07-01 | Stmicroelectronics S.R.L. | Method of avoiding the effects of lack of uniformity in trench isolated integrated circuits |
| JP4252749B2 (ja) * | 2001-12-13 | 2009-04-08 | 忠弘 大見 | 基板処理方法および基板処理装置 |
| JP4001498B2 (ja) * | 2002-03-29 | 2007-10-31 | 東京エレクトロン株式会社 | 絶縁膜の形成方法及び絶縁膜の形成システム |
| US20050155345A1 (en) * | 2002-03-29 | 2005-07-21 | Tokyo Electron Limited | Device and method for purifying exhaust gas from industrial vehicle engine |
| KR100482747B1 (ko) * | 2002-12-18 | 2005-04-14 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 제조 방법 |
| US7183143B2 (en) * | 2003-10-27 | 2007-02-27 | Macronix International Co., Ltd. | Method for forming nitrided tunnel oxide layer |
| US7399674B2 (en) * | 2004-10-22 | 2008-07-15 | Macronix International Co., Ltd. | Method of fabricating NAND-type flash EEPROM without field oxide isolation |
| CN101044626B (zh) * | 2004-10-28 | 2012-01-25 | 东京毅力科创株式会社 | 栅极绝缘膜的形成方法、半导体装置和计算机记录介质 |
-
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- 2005-12-22 US US11/813,043 patent/US20080093658A1/en not_active Abandoned
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004047614A (ja) * | 2002-07-10 | 2004-02-12 | Innotech Corp | トランジスタとそれを用いた半導体メモリ、およびトランジスタの製造方法 |
| JP2004087865A (ja) * | 2002-08-28 | 2004-03-18 | Hitachi Ltd | 半導体装置の製造方法 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7825018B2 (en) * | 2006-02-28 | 2010-11-02 | Tokyo Electron Limited | Plasma oxidation method and method for manufacturing semiconductor device |
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| CN101095224A (zh) | 2007-12-26 |
| TWI390632B (zh) | 2013-03-21 |
| JP2006186245A (ja) | 2006-07-13 |
| CN101834133A (zh) | 2010-09-15 |
| CN101834133B (zh) | 2012-01-25 |
| TW200633065A (en) | 2006-09-16 |
| CN101095224B (zh) | 2010-06-16 |
| KR20070086697A (ko) | 2007-08-27 |
| US20080093658A1 (en) | 2008-04-24 |
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