Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/12—Mountings, e.g. non-detachable insulating substrates
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
  • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
  • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
  • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L23/00—Details of semiconductor or other solid state devices
  • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
  • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/0001—Technical content checked by a classifier
  • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/1901—Structure
  • H01L2924/1904—Component type
  • H01L2924/19041—Component type being a capacitor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3011—Impedance
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/30—Technical effects
  • H01L2924/301—Electrical effects
  • H01L2924/3025—Electromagnetic shielding

Definitions

• the present invention relates to a semiconductor device, and particularly to a semiconductor device using rewiring.
• BGA All Grid Array
• the BGA structure is a solder bump that is not connected to the substrate by a lead frame like the conventional QFP (Quad Flat Package) structure.
• the terminal is connected to the substrate.
• the entire surface of the semiconductor device can be provided with an external connection terminal, and a lead frame around the component is not required, so that the mounting area can be greatly reduced.
• CSP Chip Size Package
• WL-CSP Wafer Level CSP
• Patent Document 1 Japanese Patent Application Laid-Open No. 2003-297961
• the mounting area can be reduced, but the distance between each terminal is close.
• the signal is routed to the bump position by rewiring the electrode force on the surface of the semiconductor chip, and connected to the bump by an electrode part called a post. The existence of this is something that cannot be ignored, and problems such as crosstalk between each electrode terminal and noise wraparound.
• the present invention has been made in view of these problems, and an object thereof is to provide a semiconductor device in which signal interference between a plurality of functional blocks is reduced.
• a semiconductor device includes a semiconductor substrate on which an integrated circuit including a plurality of functional blocks is formed, and a plurality of electrodes provided on the integrated circuit.
• a plurality of external electrodes that are connected to the pads via rewiring and serve as connection terminals to an external circuit.
• the plurality of external electrodes are classified into a plurality of external electrode groups according to the function blocks to be connected, and are arranged in a plurality of regions for each classified external electrode group.
• the rewiring connected to the low-impedance external electrode is laid in the boundary area between the multiple areas.
• a plurality of electrode pads provided on an integrated circuit refers to an electrode pad provided for supplying a signal to a circuit element constituting the integrated circuit, drawing out the signal, or grounding the signal.
• the “external electrode” refers to an electrode that functions as a connection terminal to an external circuit, such as a solder bump, a solder ball, or a post.
• a plurality of functional blocks for which signal interference is not desired are divided into a plurality of regions, and an external electrode connected to each functional block is divided into a plurality of regions.
• signal interference between a plurality of regions separated by rewiring can be reduced by electrically disposing the external electrodes by rewiring with low impedance.
• At least one of the plurality of functional blocks is a small signal that handles a small signal. It may be a circuit.
• another functional block may be a large signal circuit that handles large signals.
• Small signal circuits that handle small signals include, for example, circuits that perform digital signal processing and analog control circuits.Large signal circuits that handle large signals include power transistors, etc. This refers to circuits that handle high voltages, but small signal circuits and large signal circuits may be separated by the relative relationship of signal levels.
• the rewiring connected to the low-impedance external electrode may be a ground line connected to an external ground terminal or a power supply line connected to a power supply voltage terminal.
• the redistribution that is laid in the boundary area of multiple areas and connected to the low impedance external electrode is used as a ground line, the signal escapes to the external ground terminal, so signal interference between multiple areas is prevented. Can be reduced. Further, by using this rewiring as a power supply line, a signal can be released through a bypass capacitor or the like connected to the outside, so that signal interference between a plurality of regions can be reduced.
• this rewiring be formed as thick as the process rules allow.
• rewirings connected to the low-impedance external electrode, and they may be laid adjacent to each other. By separating a plurality of regions by a plurality of rewirings, signal interference can be more preferably reduced.
• Two of the plurality of rewirings connected to the low impedance external electrode are any combination of a ground line and a power line, a ground line and a ground line, or a power line and a power line. Moyo! /
• the rewiring connected to the low-impedance external electrode may be laid next to the ground line, power line, and ground line in order.
• the rewiring connected to the low impedance external electrode may be connected to the low impedance external electrode at both ends thereof.
• the impedance of the rewiring can be lowered and the potential stabilized.
• signal interference between a plurality of regions can be more preferably reduced.
• FIG. 1 is a view of a semiconductor device according to an embodiment of the present invention as viewed from the electrode pad side.
• FIG. 2 is a cross-sectional view taken along line 2-2 in FIG.
• FIG. 3 is a diagram showing an arrangement of semiconductor integrated circuits formed on a semiconductor substrate.
• FIG. 4 is a diagram showing a modification of the semiconductor device according to the embodiment.
• FIG. 5 is a diagram showing another modification of the semiconductor device according to the embodiment.
• FIG. 1 is a diagram of semiconductor device 100 according to an embodiment of the present invention as viewed from the electrode pad side.
• the semiconductor device 100 has a CSP structure.
• an external circuit formed by a plurality of electrode pads 10 and solder bumps provided on a semiconductor substrate 40 to input / output signals to / from an external circuit.
• Electrode 20 and rewiring 30 are shown.
• the same components are denoted by the same reference numerals, and description thereof will be omitted as appropriate.
• the external electrode 20 is arranged in a matrix on the surface of the semiconductor device 100.
• the electrode pad 10 is disposed on the outermost periphery of the semiconductor substrate 40 so as to surround the integrated circuit.
• the external electrode 20 and the electrode pad 10 are connected via a rewiring 30.
• FIG. 2 is a cross-sectional view taken along line 2-2 of FIG.
• This semiconductor device 100 is formed on a semiconductor substrate 40. It has a WL-CSP structure that directly forms external connection electrodes.
• the semiconductor device 100 includes a semiconductor substrate 40, a passivation film 42 for passivation, an electrode pad 10, a rewiring 30, a post 48, an external electrode 20, and a sealing resin 50.
• a semiconductor integrated circuit including circuit elements such as transistors and resistors is formed on the upper surface of the semiconductor substrate 40, and electrode pads 10 for signal input / output are provided.
• the electrode pad 10 is usually formed of a material such as aluminum.
• the protective film 42 is a silicon nitride film or the like, and is formed by opening the upper part of the electrode pad 10.
• the rewiring 30 is made of copper, aluminum, gold, or the like, and routes the signal from the electrode pad 10 to the position of the external electrode 20 that is the final formation position of the external extraction electrode, and connects to the post 48.
• the columnar post 48 is formed of gold, copper, or the like, and electrically connects the external electrode 20 and the rewiring 30.
• an insulating layer may be further formed on the upper layer of the protective film 42 using an oxide film or a resin film such as polyimide, and the rewiring 30 may be formed on the insulating layer.
• FIG. 3 is a diagram showing an arrangement of the semiconductor integrated circuit 300 formed on the semiconductor substrate 40.
• the semiconductor integrated circuit 300 includes a small signal circuit 310 and a large signal circuit 320 as a plurality of functional blocks.
• the signal interference generated between the small signal circuit 310 and the large signal circuit 320 causes malfunction of the circuit and the accuracy of the signal generated by the semiconductor integrated circuit 300.
• the circuit 320 is divided into two regions.
• the small signal circuit 310 includes a band gap reference circuit used for generating a reference voltage and a constant current, a digital analog converter, and the like.
• the large signal circuit 320 includes a power transistor provided in an output stage for driving the load circuit.
• the small signal circuit 310 and the large signal circuit 320 are separately supplied with a power supply voltage and a ground voltage in order to avoid electrical interference.
• each of the small signal circuit 310 and the large signal circuit 320 includes an electrode pad for supplying a power supply voltage and a ground voltage.
• the electrode pads 10a and 10c are electrode pads for supplying a ground potential to the large signal circuit 320
• the electrode pad 10b is an electrode node for supplying a power supply voltage to the large signal circuit 320
• the electrode pad 10d is used to supply a power supply voltage to the small signal circuit 310.
• the electrode pad lOe is an electrode pad for supplying a ground potential to the small signal circuit 310.
• the plurality of external electrodes 20 are divided into a first external electrode group 210 connected to the small signal circuit 310 and a second external electrode group 220 connected to the large signal circuit 320, and arranged in two regions. Has been.
• the external electrode 20 is supplied with the power supply voltage and the ground voltage for each functional block in order to avoid electrical interference between the small signal circuit 310 and the large signal circuit 320.
• the external electrode 20a is a ground terminal GND, and is grounded outside the semiconductor device 100.
• the external electrode 20a is connected to the electrode pad 10a via the rewiring 30a ′, and supplies a ground voltage to the large signal circuit 320 of the semiconductor integrated circuit 300. .
• the external electrode 20b is a power supply voltage terminal Vdd, is connected to an external voltage source, is connected to the electrode pad 10b by rewiring 30b ′, and supplies a power supply voltage to the large signal circuit 320 of the semiconductor integrated circuit 300.
• the external electrode 20c is a ground terminal, and is connected to the electrode node 10c through the rewiring 30c ′, and supplies a ground voltage to the large signal circuit 320.
• the semiconductor device 100 includes rewirings 30a to 30c.
• the rewirings 30a to 30c are laid in boundary regions between regions where the first external electrode group 210 and the second external electrode group 220 are respectively disposed.
• the rewirings 30a to 30c are connected to the external electrodes 20a to 20c, respectively.
• the external electrodes 20a and 20c are fixed to the ground potential, and the external electrode 20b is a terminal fixed to the power supply voltage, both of which have low impedance. Therefore, the impedance of the rewirings 30a to 30c and the rewirings 30a to 30c connected to these external electrodes 20a to 20c is set to be low.
• the rewirings 30a to 30c and the rewirings 30a 'to 30c' laid in the boundary region between the first external electrode group 210 and the second external electrode group 220 are designed to be as wide as possible. It is desirable to reduce the rewiring impedance.
• a plurality of external electrodes 20 is classified into the first and second external electrode groups 210 and 220 according to the function block to be connected, and the plurality of external electrodes 20 are divided into a plurality of regions for each of the plurality of external electrode groups. Has been.
• the first external electrode group 210 and the second external electrode group 220 are electrically cut off by rewiring, and noise signals generated from the small signal circuit 310 and the large signal circuit 320 are regenerated with low impedance. It can escape to the outside of the semiconductor device 100 through the wirings 30a to 30c and the external electrode 20, and signal interference between a plurality of functional blocks can be reduced.
• multilayer aluminum wiring on semiconductor integrated circuit 300 is used to separate small signal circuit 310 and large signal circuit 320 using rewiring 30. Compared with the case of separating them, signal interference can be reduced without increasing the area of the semiconductor substrate 40, that is, the chip cost. Further, since the wiring width of the rewiring 30 can be increased as much as allowed between the external electrodes 20, the small signal circuit 310 and the large signal circuit 320 can be more effectively separated.
• the small signal circuit 310 and the large signal circuit 320 are electrically separated using the rewirings 30a to 30c and the rewirings 30a ′ to 30c ′.
• the conventional design can be performed for the layer below the protective film 42.
• FIG. 4 is a view showing a modification of the semiconductor device 100 of FIG.
• the small signal circuit 310 shown in FIG. 3 is further divided into two circuit blocks 310a and 310b by a broken line 330.
• the large signal circuit 320 is also divided into two circuit blocks 320a and 320b by the broken line 340!
• the external electrodes 20 connected to the circuit blocks 310a and 310b are also divided into an external electrode group 210a and an external electrode group 210b.
• the signal circuit 310 is provided with a self-recovery line 30d, 30d ', 30e, 30e' force S. Redistribution 30d 'is used to supply power to small signal circuit 310.
• the rewiring 30e ′ is connected to the external electrode 20e for supplying a ground potential to the small signal circuit 310.
• the rewiring 30d and the rewiring 30e are laid in a boundary region between the external electrode group 210a and the external electrode group 210b, and electrically cut off between the external electrode groups 210a and 210b.
• two or more external electrode groups are also electrically divided by rewiring connected to external electrodes having low impedance. Therefore, signal interference between circuit blocks inside the small signal circuit 310 or the large signal circuit 320 can be reduced.
• the technology in which the small signal circuit 310 and the large signal circuit 320 are further divided into a plurality of circuit blocks and electrically separated by rewiring is used in an integrated circuit provided with a plurality of channels having the same function. Therefore, it can be suitably used in cases where signal interference between channels is prevented.
• FIG. 5 is a view showing another modified example of the semiconductor device 100.
• the external electrodes 20h and 20h ′ are grounding external extraction electrodes
• the external electrodes 20i and 20i ′ are power supply voltage supply electrodes.
• the rewiring 30h is connected to the low impedance external electrodes 20h and 20h ′ at both ends thereof.
• rewiring 30i is connected to external electrodes 20i and 20i at both ends.
• rewiring 30h and 30i is connected to an external circuit via external electrodes 20h and 20h 'and 20i and 20', respectively. That's true.
• the connection resistance is 1Z2 compared to the case where it is connected to an external circuit through one external electrode. Can be lowered.
• the resistance component of the rewiring and the Inductance component increases and impedance of rewiring becomes nonuniform. Impedance of rewiring can be reduced uniformly by connecting external electrodes to both ends.
• noise generated from the small signal circuit 310 and the large signal circuit 320 is transferred to the external circuit via the external electrodes 20h, 20h ′, 20i, and 20i ′. Since it can be escaped, signal interference between the small signal circuit 310 and the large signal circuit 320 can be more suitably reduced.
• the semiconductor integrated circuit 300 is divided into two or four functional blocks and rewiring is laid in the boundary region of the external electrode group connected to each functional block has been described.
• the number of circuit blocks to be divided can be freely set according to the characteristics required for the semiconductor device 100 !.
• the small signal circuit 310 and the large signal circuit 320 are divided at the center of the semiconductor device 100, and accordingly, the first and second external electrode groups 210 and 220 are also semiconductor devices.
• the present invention is not limited to this, and it may be divided at an arbitrary position according to the size of each circuit!
• a region where the small signal circuit 310 and the large signal circuit 320 which are functional blocks are disposed, and a region where the first and second external electrode groups 210 and 220 connected to the respective functional blocks are disposed do not necessarily match.
• a part of the large signal circuit 320 may overlap with a part of a region where the first external electrode group 210 is disposed.
• the number of rewirings laid in the boundary region of the plurality of external electrode groups may be determined in consideration of how much signal interference between functional blocks should be reduced.
• the rewiring laid in the boundary region between the first external electrode group and the second external electrode group may be formed twice. The rewiring impedance can be further reduced and signal interference can be further reduced.
• the first external electrode group 210 and the second external electrode group 220 The rewiring 30 laid in the boundary area has been described as being connected to the external electrode 20 for supplying the power supply voltage and ground voltage of the large signal circuit 320. It can be an external electrode 20 for supplying voltage or a combination thereof.
• the present invention can be applied to any of an analog circuit, a digital circuit, and an analog / digital mixed circuit, and the semiconductor manufacturing process is also applied to! /, Deviation of a bipolar process, a CMOS process, and a BiCMOS process. can do.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Computer Hardware Design (AREA)
• Power Engineering (AREA)
• Semiconductor Integrated Circuits (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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• 2005
  • 2005-11-25 JP JP2006547854A patent/JP5039384B2/ja not_active Expired - Fee Related
  • 2005-11-25 KR KR1020067016831A patent/KR20070088266A/ko not_active Withdrawn
  • 2005-11-25 CN CN2010101293355A patent/CN101814458B/zh not_active Expired - Fee Related
  • 2005-11-25 WO PCT/JP2005/021686 patent/WO2006059547A1/ja not_active Ceased
  • 2005-11-25 US US11/792,261 patent/US20090166856A1/en not_active Abandoned
  • 2005-11-25 CN CN2005800052715A patent/CN1922728B/zh not_active Expired - Fee Related
  • 2005-12-02 TW TW094142400A patent/TW200620574A/zh not_active IP Right Cessation

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