WO2006048932A1 - Dispositif electronique et procede de fabrication de dispositif electronique - Google Patents

Dispositif electronique et procede de fabrication de dispositif electronique Download PDF

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Publication number
WO2006048932A1
WO2006048932A1 PCT/JP2004/016324 JP2004016324W WO2006048932A1 WO 2006048932 A1 WO2006048932 A1 WO 2006048932A1 JP 2004016324 W JP2004016324 W JP 2004016324W WO 2006048932 A1 WO2006048932 A1 WO 2006048932A1
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WO
WIPO (PCT)
Prior art keywords
electronic device
wiring board
electrodes
pair
main surface
Prior art date
Application number
PCT/JP2004/016324
Other languages
English (en)
Japanese (ja)
Inventor
Hiroki Noto
Tomoaki Kudaishi
Yusuke Sato
Satoru Konishi
Masashi Okano
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2004/016324 priority Critical patent/WO2006048932A1/fr
Priority to JP2006542202A priority patent/JPWO2006048932A1/ja
Publication of WO2006048932A1 publication Critical patent/WO2006048932A1/fr

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0262—Arrangements for regulating voltages or for using plural voltages
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    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
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    • H05K1/111—Pads for surface mounting, e.g. lay-out
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    • H05K3/3452—Solder masks
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to an electronic device technology, and more particularly to a technology effective when applied to an RF (Radio Frequency) power module.
  • RF Radio Frequency
  • the RF power module examined by the present inventors is an electronic component for signal amplification of a portable communication device such as a mobile phone, for example, and includes a plurality of semiconductor chips having a transistor for signal amplification, and A plurality of chip components having passive elements are mounted on a module substrate, and these are electrically connected to each other.
  • the chip component is mounted on the module substrate with its electrodes connected via a solder or the like to a pair of electrodes exposed from the opening formed in the insulating layer on the mounting surface of the module substrate.
  • the chip component is described in, for example, Japanese Patent Laid-Open No. 5-326632, and the pair of electrodes of the chip component is an opening formed in an insulating layer formed on the mounting surface of the substrate.
  • a configuration is disclosed in which an insulating layer between adjacent electrodes of the substrate is also removed and the substrate surface is exposed (see Patent Document 1).
  • Patent Document 1 JP-A-5-326632
  • the chip components of the 0402 type which are smaller than those of the current mainstream 1005 type and 0603 type chip components, are used as the chip components constituting the RF power module. Therefore, it is considered to realize higher density mounting.
  • the use of the 0402 type chip component in the chip component installation location in the entire circuit of the RF power module adversely affects the efficiency of the high frequency characteristics.
  • the distance between the electrodes of the chip component is narrow, so the distance between the pair of electrodes on the module substrate to which the electrode of the chip component is connected is also narrow. Therefore, the opening formed in the insulating layer on the module substrate is not formed so as to expose each of the pair of adjacent electrodes, but the pair of adjacent electrodes and the module substrate surface therebetween are exposed.
  • solder flash a phenomenon in which the solder attached to the electrode of the chip component melts and expands when the RF power module is mounted and breaks the sealing resin
  • solder flash a phenomenon in which the solder attached to the electrode of the chip component melts and expands when the RF power module is mounted and breaks the sealing resin
  • This solder flash problem is particularly likely to occur when the solder bumps on the back side of the module board are made of lead-free solder and the melting point of the solder bumps is higher than the melting point of the solder attached to the chip component electrode.
  • An object of the present invention is to provide a technique capable of reducing the size of an electronic device.
  • Another object of the present invention is to provide a technique capable of suppressing or preventing a short circuit failure between a pair of electrodes of an electronic component constituting an electronic device.
  • the present invention uses electronic components having different dimensions depending on the place where the electronic component is incorporated in the high-frequency power amplifier circuit.
  • the present invention is such that an insulating layer remains on the wiring board between the pair of electrodes of the electronic component in the high-frequency power amplifier circuit.
  • FIG. 1 is an explanatory diagram of an example of a mobile phone system having an electronic device according to an embodiment of the present invention.
  • FIG. 2 is a circuit block diagram of an example of an electronic device in the mobile phone system of FIG.
  • FIG. 3 is an explanatory diagram of an example of mounting an electronic device in the mobile phone system of FIG. 1.
  • FIG. 4 is a plan view of an example of a main surface of a wiring board of an electronic device.
  • FIG. 5 is a plan view of an example of the back surface of the wiring board of FIG.
  • FIG. 6 is a cross-sectional view taken along line XI—XI in FIG.
  • FIG. 7 is a cross-sectional view of an essential part of an example of a semiconductor chip when a semiconductor amplifying element constituting an amplifier circuit part of an electronic device is formed by an LDMOSFET.
  • FIG. 8 is a fragmentary cross-sectional view of an example of a semiconductor chip when a semiconductor amplifying element constituting an amplifier circuit portion of an electronic device is formed of a heterojunction bipolar transistor.
  • FIG. 9 is an enlarged plan view of a component mounting surface of the wiring board of FIG. 4 and a chip component mounting region. [10] FIG. 9 is an enlarged plan view of the wiring board showing a state where the chip components are mounted in FIG.
  • FIG. 11 is a sectional view taken along line X 2 -X 2 in FIG.
  • FIG. 12 is a cross-sectional view of an example of the X2-X2 line in FIG. 10 of the chip part having a capacitor.
  • FIG. 13 is a cross-sectional view of an example of the X2-—X2 line in FIG. 10 of the chip component having a resistor.
  • FIG. 14 is a partially broken cross-sectional view of an example of the X2-X2 line in FIG. 10 of the chip component having an inductor.
  • FIG. 15 is a circuit diagram of an example of a high frequency power amplifier circuit of an electronic device.
  • FIG. 16 is a circuit diagram of an example in which chip components in the circuit diagram of FIG. 15 are indicated by element-level graphic symbols.
  • FIG. 17 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is another embodiment of the present invention, and a mounting region of a chip component.
  • FIG. 18 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
  • FIG. 19 is a cross-sectional view taken along line X3-X3 in FIG.
  • FIG. 20 is an enlarged cross-sectional view of a main part of a wiring board between a pair of electrodes in FIG.
  • FIG. 21 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is another embodiment of the present invention, and a mounting region of a chip component.
  • FIG. 22 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
  • FIG. 23 is a cross-sectional view taken along line X4-X4 in FIG.
  • FIG. 24 is an enlarged cross-sectional view of a main part of the wiring board between a pair of electrodes in FIG. 23.
  • FIG. 25 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is still another embodiment of the present invention, and a chip component mounting region.
  • FIG. 26 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
  • FIG. 27 is a sectional view taken along line X5-X5 in FIG.
  • FIG. 28 is a cross-sectional view taken along line X6—X6 of FIG.
  • FIG. 29 An enlarged plan view of a component mounting surface of a wiring board of an electronic device according to another embodiment of the present invention, which is a mounting region of a chip component.
  • FIG. 30 is an enlarged plan view showing a state where chip components are mounted on the wiring board of FIG.
  • FIG. 31 is a cross-sectional view taken along line X7—X7 of FIG.
  • FIG. 32 is a cross-sectional view taken along line X8—X8 of FIG.
  • FIG. 33 is a flowchart of a manufacturing process of the electronic device according to the embodiment of the invention.
  • FIG. 34 is an essential part enlarged cross-sectional view of the multilayer ceramic substrate during the manufacturing process of the electronic device according to one embodiment of the present invention.
  • FIG. 35 is a fragmentary cross-sectional view of a printing mask used in the manufacturing process of the electronic device according to one embodiment of the present invention.
  • FIG. 36 is a cross-sectional view of a principal part in a state where the multilayer ceramic substrate of FIG. 34 and the printing mask of FIG. 35 are overlaid.
  • FIG. 37 is a cross-sectional view of main parts of a multilayer ceramic substrate and a printing mask during a printing process.
  • FIG. 38 is a cross-sectional view of a principal part of a multilayer ceramic substrate.
  • FIG. 39 is an enlarged cross-sectional view of an example of an insulating layer portion between a pair of electrodes on the main surface of a multilayer ceramic substrate.
  • FIG. 40 is an enlarged sectional view of another example of the insulating layer portion between a pair of electrodes on the main surface of the multilayer ceramic substrate.
  • FIG. 41 is a fragmentary cross-sectional view of the multilayer ceramic substrate after a chip component mounting step.
  • FIG. 42 is a fragmentary cross-sectional view of the mother board during the mounting process of the electronic device.
  • FIG. 43 is a fragmentary cross-sectional view of the mother board after the mounting process of the electronic device.
  • GSM Global System for Mobile Communication
  • GSM Global System for Mobile Communication
  • GSM Global System for Mobile Communication
  • GSM Global System for Mobile Communication
  • GSM has three frequency bands of radio waves to be used: 900 MHz band is GSM900 or simply GSM, 1800 MHz band is GSM1 800 or DCS (Digital Cellular System) 1800 or PCN, 1900 MHz band is GS Ml 900 or DCS 1900 or PCS (Personal Communication Services).
  • GSM1900 is mainly used in North America. In North America, the GSM850 in the 850MHz band may also be used.
  • the GMSK modulation method is a method used for communication of an audio signal. In this method, the phase is shifted according to the data.
  • the EDGE modulation method is a method used for data communication, in which an amplitude shift is added to the phase shift of GMSK modulation.
  • Fig. 1 shows an example of DPS, a digital mobile phone system that transmits information using a GSM network, for example.
  • This digital cellular phone system DPS is constructed by modules, circuits and elements mounted on the motherboard MB.
  • Symbol PM is an RF (Radio Frequency) power module (hereinafter simply referred to as a power module) that is the electronic device of the first embodiment
  • symbol ANT is an antenna for transmitting and receiving signal radio waves
  • symbol FEM is a front end module.
  • the code BBC converts the audio signal into a baseband signal, converts the received signal into an audio signal, generates the modulation system switching signal and the band switching signal, and the code FMC downcodes the received signal.
  • Modulation / demodulation circuits FLT1 and FLT2 that demodulate and demodulate to generate a baseband signal and modulate the transmission signal are filters that remove noise and interference from the received signal power.
  • Filter FLT1 is for GSM and filter FLT2 is for DCS.
  • the baseband circuit BBC is composed of a plurality of semiconductor integrated circuits such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory.
  • the front end module FEM has low-pass filters LPFl and LPF2, switch circuits SWl and SW2, capacitors CI and C2, and a duplexer WDC.
  • Low-pass filters LPFl and LPF2 are circuits that attenuate harmonics
  • switch circuits SWl and SW2 are switch circuits for switching transmission and reception signals
  • capacitors CI and C2 are elements that cut the DC component from the received signal
  • duplexer WDC is It is a circuit that demultiplexes GSM900 band signals and DCS1 800 band signals, and these circuits and elements are mounted on a single circuit board as a module.
  • the switching signals C NT1 and CNT2 of the switch circuits SWl and SW2 are supplied from the baseband circuit BBC.
  • FIG. 2 shows an example of a circuit block diagram of the power module PM.
  • the noise module PM can use four frequency bands, e.g. GSM850, GSM900, DCS1800 and DCS1900 (four-band method), and GMS K (Gaussian filtered Minimum Shift Keying) and EDGE (Enhanced Data) in each frequency band.
  • GSM Environment It is configured to be able to use two communication systems with modulation system! /
  • This power module PM includes an amplifier circuit unit 2A for GSM850 and GSM900, an amplifier circuit unit 2B for DCS1800 and DCS1900, and a peripheral circuit that controls and corrects the amplification operation of these amplifier circuit units 2A and 2B. And 3.
  • Each amplifier circuit section 2A, 2B has three amplifier circuit sections 2A1-2A3, 2B1-2B3 connected in series, and four impedance matching circuits 2 AM1-2AM4, 2BM1-2BM4.
  • the input terminals Tal and Tbl of the power module PM are electrically connected to the inputs of the first stage amplification circuit sections 2A1 and 2B1 via the impedance matching circuits 2AM1 and 2BM1 of the input stage, and are connected to the first stage.
  • the output of the second amplification circuit section 2A1, 2B1 is electrically connected to the input of the second stage amplification circuit section 2A2, 2B2 via the interstage impedance matching circuit 2AM2, 2BM2, and the second stage amplification circuit
  • the outputs of the parts 2A2 and 2B2 are electrically connected to the inputs of the final stage amplifier circuit parts 2A3 and 2B3 via the interstage impedance matching circuits 2A M3 and 2BM3.
  • the outputs of the final stage amplifier circuits 2A3 and 2B3 are electrically connected to the output terminals Ta2 and Tb2 via the impedance matching circuits 2AM4 and 2BM4 of the output stage.
  • the peripheral circuit 3 includes a control circuit 3A, a bias circuit 3B for applying a bias voltage to the amplifier circuit units 2A1-2A3, 2B1-2B3, and the like.
  • the control circuit 3A is a circuit that generates a desired voltage to be applied to the amplification circuit units 2A and 2B, and includes a power supply control circuit 3A1 and a bias voltage generation circuit 3A2.
  • the power supply control circuit 3A1 is a circuit that generates a first power supply voltage to be applied to the drain terminals of the power MOS FETs for output of each of the amplification circuit sections 2A1-2A3, 2B1-2B3.
  • the bias voltage generation circuit 3 A2 is a circuit that generates a first control voltage for controlling the bias circuit 3B.
  • the bias voltage generation circuit 3A2 Based on the first power supply voltage generated by the power supply control circuit 3A1, the first control voltage is generated! /
  • the baseband circuit BBC is a circuit that generates the output level designation signal.
  • This output level designation signal is a signal that designates the output level of the amplifier circuits 2A and 2B, and is generated based on the distance between the mobile phone and the base station, that is, the output level according to the strength of the radio wave. And become like! /
  • FIG. 3 shows an implementation example of the power module PM of the digital cellular phone system DPS shown in FIG.
  • the mother board MB is, for example, a printed wiring board having a multilayer wiring structure, and a power module PM and a plurality of chip components 5 are mounted on the main surface thereof.
  • the power module PM is connected via a bump electrode (external terminal, protruding electrode) 6 connected to each of a plurality of electrodes (external connection electrodes) on the back surface (module mounting surface) of the module board (wiring board) MC B. It is mounted on the main surface of one board MB.
  • the power module PM has a so-called BGA (Ball Grid Array) package configuration in which a plurality of protruding bump electrodes 6 are arranged in an array on the module mounting surface. Further, the chip component 5 is mounted on the main surface of the mother board MB via the bonding material 7.
  • the material of the bump electrode 6 and the bonding material 7 includes, for example, a tin-silver-based lead-free (lead-free) solder (such as a tin “!
  • tin-copper-based lead-free solder such as tin-nickel (Ni) alloy (melting point: about 227 degrees)
  • tin-zinc-based lead-free solder such as tin-zinc (Zn) alloy ( Melting point: about 198 degrees)
  • tin-bismuth-based lead-free solder Melting point: about 148 degrees
  • tin-bismuth silver alloy or lead-free solder of tin antimony (Sb) alloy is used.
  • the power module PM and the chip component 5 are electrically connected to each other through the wiring of the mother board MB to form the digital mobile phone system DPS.
  • the main surface (mounting part mounting surface) of the module board MC B is covered with, for example, a silicone rubber (silicone resin) or an epoxy resin, and the like, and is mounted on the main surface of the module board MCB. Electronic components such as semiconductor chips and chip components described later are sealed.
  • the bump electrode 6 of the power module PM may be made of gold (Au) in addition to lead-free solder.
  • the power module PM package configuration may be a so-called LGA (Land Grid Array) package configuration in which a plurality of flat electrode pads are arranged in an array on the module mounting surface.
  • FIG. 4 is a plan view of an example of the main surface (part mounting surface) of the module board MCB of the power module PM
  • FIG. 5 is the back surface (module mounting surface) of the module board MCB of FIG.
  • FIG. 6 shows an example of a cross-sectional view taken along line XI-XI in FIG.
  • X represents the first direction
  • Y represents the second direction orthogonal to the first direction X.
  • the module substrate MCB has a multilayer wiring structure in which insulating layers 11 and wirings 12 are alternately laminated and integrated.
  • Wiring 12 and via 12V are formed in the inner layer of module board MCB.
  • the wiring 12 of each layer of the module board MCB is electrically connected through the via 12V!
  • the inner layer wiring 12 and via 12V are made of, for example, an alloy of copper (Cu) and tungsten (W).
  • the component mounting surface (main surface, first surface) of the uppermost insulating layer 11 and the module mounting surface of the lowermost insulating layer 11 Wiring 12 and electrodes (land, terminal, conductor pattern) 12E are formed on the back surface and the second surface.
  • the wiring 12 and the electrode 12E are made of, for example, a alloy of copper (Cu) and tungsten (W), and nickel (Ni) plating and gold (Au) plating are sequentially applied to the surface with lower layer force! / RU Furthermore, the component mounting surface of the uppermost insulating layer 11 and the module mounting surface of the lowermost insulating layer 11 are wetted by solder (lead (Pb) —tin (Sn)) such as overcoat glass (silicon). However, an insulating layer 13 having properties may be formed so as to cover the surface of the wiring 12! A part of the insulating layer 13 is opened, and the force electrode 12E is exposed there.
  • solder lead (Pb) —tin (Sn)
  • the wide electrode 12E1 at the center of the back surface of the module substrate MCB is an electrode for a reference potential (ground potential GND, for example, OV).
  • the electrode 12E2 at the outer peripheral corner of the back surface of the module substrate MCB is an RF signal electrode.
  • the electrode 12E3 on the outer periphery of the back surface of the module board MCB is an electrode for supplying a bias voltage.
  • the electrode 12E4 on the outer periphery of the back surface of the module board MCB is an electrode for control signals.
  • one semiconductor chip (electronic component) 15 is mounted on the component mounting surface of the module board MCB, and for example, three types of chip components (electronic component and passive component) of different sizes 16 (16a-16c) is implemented.
  • the semiconductor chip 15 is well mounted in a substantially rectangular recess 17 called a cavity at the center of the main surface of the module substrate MCB with its main surface (device forming surface) facing upward. .
  • the semiconductor chip 15 is formed with three stages of amplification circuit sections 2A1-2A3 for GSM850 and GSM900 and three stages of amplification circuit sections 2B1, 2B3 for DCS1800 and DCS1900.
  • a plurality of bonding pads (external terminals: hereinafter simply referred to as pads! /) Are formed along the outer periphery.
  • the node P is a lead electrode for a circuit formed on the semiconductor chip 15.
  • each electrode 12E is formed integrally with the wiring 12 on the main surface of the module substrate MCB.
  • Each of the electrodes 12E and the semiconductor layer 15 are connected to each other through a bonding wire (hereinafter simply referred to as a wire) BW connected in contact therewith. Yes.
  • the wire BW is made of, for example, gold (Au).
  • the back surface of the semiconductor chip 15 is connected to the electrode 12E on the bottom surface of the recess 17 of the module substrate MCB, and is further electrically connected to the electrode 12E1 on the back surface of the module substrate MCB through vias 12V.
  • FIG. 7 shows a semiconductor in which the semiconductor amplifying elements constituting the amplifying circuit portions 2A1-2A3, 2B1-2B3 are formed by LDMOSFETs (Laterally Diffused Meta-Oxide-Semiconductor Field Effect Transistors). An example of a cross-sectional view of the main part of the chip 15 is shown.
  • LDMOSFETs Laser Diffused Meta-Oxide-Semiconductor Field Effect Transistors
  • An epitaxial layer 202 made of p-type single crystal silicon is formed on the main surface of the semiconductor substrate 201 that also has p + type single crystal silicon force, and an L DMOSFET is formed on a part of the main surface of the epitaxial layer 202.
  • a P-type well 203 is formed, which functions as a punch-through streak that suppresses the extension of the depletion layer from the drain to the source.
  • an LDMOSFET gate electrode 205 is formed through a gate insulating film 204 made of silicon oxide or the like.
  • the gate electrode 205 is made of, for example, a laminated film of an n-type polycrystalline silicon film and a metal silicide film, and a sidewall spacer 206 having a force such as silicon oxide is formed on the side wall of the gate electrode 205.
  • the source and drain of the LDMOSFET are formed.
  • the drain is an n-type offset drain region 207 that is in contact with the channel formation region, an n-type offset drain region 208 that is in contact with the n-type offset drain region 207 and is separated from the channel formation region force, and an n-type offset.
  • the n + type drain region 209 formed in contact with the drain region 208 and further away from the channel formation region also acts as a force.
  • n-type offset drain region 207 closest to gate electrode 205 has the lowest impurity concentration and is the farthest away from gate electrode 205.
  • the interstitial n + type drain region 209 has the highest impurity concentration.
  • the source of the LDMOSFET is formed in contact with the n-type source region 210 in contact with the channel formation region, and in contact with the n- type source region 210, and is separated from the channel formation region, and has an impurity concentration higher than that in the n-type source region 210.
  • a p-type halo region 212 is formed below the n-type source region 210.
  • a p-type punching layer 214 in contact with the n + type source region 211 is formed at the end of the n + type source region 211 (the end opposite to the side in contact with the n ⁇ type source region 210).
  • the p-type punching layer 214 is a conductive layer for electrically connecting the source of the LDMOSFET and the semiconductor substrate 201, for example, a p-type polycrystalline silicon embedded in the groove 213 formed in the epitaxial layer 202. Formed by a film.
  • LDMOSFET p-type punch layer 214 (p + type semiconductor region 215), source (n + type source region 211), and drain (n + type drain region 209) are respectively formed on top of silicon nitride film 221 and oxide.
  • a plug 224 in a contact hole 223 formed in the silicon film 222 is connected.
  • a source electrode 225 is connected to the p-type punching layer 214 (p + type semiconductor region 215) and the source (n + type source region 211) via a plug 224, and a plug 224 is connected to the drain (n + type drain region 209).
  • a drain electrode 226 is connected via
  • a wiring 229 is connected to each of the drain electrode 226 and the source electrode 225 via a through hole 228 formed in the silicon oxide film 227 that covers the drain electrode 226 and the source electrode 225.
  • a surface protective film 230 made of a multilayer film of an oxide silicon film and a silicon nitride film is formed.
  • a source back electrode 231 is formed on the back surface of the semiconductor substrate 201.
  • FIG. 8 shows a configuration of the semiconductor chips 15a-15c in the case where the semiconductor amplifying elements constituting the amplifying circuit sections 2A1-2A3, 2B1-2B3 are formed by heterojunction bipolar transistors (HBTs). An example of a fragmentary sectional view is shown.
  • HBTs heterojunction bipolar transistors
  • a subcollector layer 252 made of an n + type GaAs layer is formed on a semi-insulating GaAs substrate (semiconductor substrate) 251, and an HBT 253 is formed on the subcollector layer 252.
  • Each HBT 253 has a collector electrode 254 made of gold or the like formed on the sub-collector layer 252 and a collector mesa 255 formed so as to be separated from the collector electrode 254 by a predetermined distance.
  • the collector mesa 255 is formed of, for example, an n-type GaAs layer, and the collector mesa 255 and the collector electrode 254 are electrically connected via the subcollector layer 252.
  • a base mesa 256 made of, for example, a p-type GaAs layer is formed.
  • a base electrode 257 made of gold or the like is formed in the peripheral area on the base mesa 256! .
  • An emitter layer 258 is formed on a substantially central portion of the base mesa 256, and an emitter electrode 259 is formed on the emitter layer 258.
  • the emitter layer 258 is formed of, for example, an n-type InGaP layer, a GaAs layer, and an InGaAs layer, and the emitter electrode 259 is formed of, for example, a tungsten silicide force.
  • a heterogeneous semiconductor junction heterojunction
  • a collector wiring 263 is connected to the collector electrode 254 via a contact hole 262 formed in the insulating film 261.
  • An emitter wiring 266 is connected to the emitter electrode 259 through through holes 265 formed in the insulating films 264 and 261. The illustration of the structure above the emitter wiring 266 is omitted here.
  • the chip components 16a to 16c shown in FIG. 4 are mounted on the component mounting surface of the module substrate MCB in a state where the electrodes are connected to the electrodes 12E of the component mounting surface of the module substrate MC B.
  • the chip component 16 is formed with passive elements such as capacitors CG1-CG6, CA1-CA3, ferrite beads FB1, inductor LG1, resistors Rl, R3, R5, and the like.
  • the chip component (first passive component) 16a having the smallest size among the chip components 16 is a 0402 type chip component.
  • the power module PM is downsized.
  • a chip component 16a in which resistors Rl, R3, R5, a capacitor CG1, and the like are formed is illustrated.
  • a chip component (second passive component) 16b larger than the chip component 16a is a 0603 type chip component.
  • a chip component 16b in which capacitors CG2-CG6, CA1-CA3, ferrite beads FBI, and the like are formed is illustrated.
  • a chip component (second passive component) 16c larger than the chip component 16b is a 1005 type chip component.
  • a chip component 16c in which an inductor LG1 is formed is illustrated.
  • FIG. 9 is an enlarged plan view of the mounting area of the chip component 16 (16a and 16c) on the mounting surface of the module substrate MCB
  • FIG. 10 shows the chip component 16 (16a-16c) in FIG. Fig. 11 is a cross-sectional view taken along the line X2-X2 in Fig. 10, showing the state where is mounted.
  • Chip parts 16a-16c have different dimensions and electrical specifications, The configuration of the chip component 16 and the configuration of the mounting area of the chip component 16 of the module board MCB are the same.
  • Openings 20 and 20 are formed in the insulating layer 13 on the component mounting surface of the module board MCB, and each of the pair of electrodes 12E and 12E is exposed. ing. The outer peripheral portion of each of the pair of electrodes 12E and 12E is separated from the end portion of the insulating layer 13 (that is, the end portion of the opening 20). Each of the pair of electrodes 16E, 16E of the chip component 16 (16a-16c) is connected to each of the pair of electrodes 12E where the forces of the openings 20, 20 of the module board MCB are also exposed by the adhesive 21. .
  • the adhesive 21 also has, for example, a lead (Pb) -tin (Sn) soldering force.
  • the melting point of Pb—Sn is different depending on the ratio of Pb and Sn. For example, when the ratio of Pb—Sn is 37Z63 (eutectic solder), it is about 183 degrees, for example.
  • the insulating layer 13 is left on the insulating layer 11 between the adjacent electrodes 12E of the module board MCB.
  • the length of the smallest 0402 type chip component 16a among the chip components 16 (the total length in the longitudinal direction of the chip component 16) D1 is, for example, 0.4 ⁇ 0.02 mm
  • the length of the electrode 16E in the longitudinal direction) D2 is, for example, 0.0-07-0.12 mm
  • the length between the electrodes (the length between the adjacent electrodes 16E in the longitudinal direction of the chip part 16) D3 is, for example, 0. 15mm or more
  • width (length in the short direction of chip component 16) D4 is 0.2 ⁇ 0.02mm
  • height D5 is chip capacitor, for example 0.2 ⁇ 0.02mm
  • chip resistance In some cases, for example, 0.12 ⁇ 0.02 mm.
  • each of the pair of electrodes 12E in the mounting region of the chip component 16a is, for example, 0.15 mm
  • the width of each of the pair of electrodes 12E is, for example, 0.25 mm
  • the distance from the outer periphery of the electrode 12E to the end of the opening 20 is, for example, 0.0375 mm, adjacent to the pair of electrodes 12E.
  • the distance D9 is, for example, 0.175 mm or more, for example, 0.205 mm, and the width of the insulating layer 13 left between the pair of electrodes 12E (the length in the direction in which the pair of electrodes 12E are arranged) D10 is, for example, 0 13mm.
  • the length D1 of the 0603-type chip part 16b having an intermediate size is, for example, 0.6 ⁇ 0.03 mm
  • the electrode length D2 is, for example, 0.1-0.2 mm
  • the inter-electrode length D3 is For example, 0.2 mm or more
  • width D4 is, for example, 0.3 ⁇ 0.03 mm
  • height D5 is, for example, a chip capacitor. 3 ⁇ 0.03mm, in case of chip resistor, for example 0.25 ⁇ 0.03mm.
  • the length D6 of each of the pair of electrodes 12E in the mounting region of the chip component 16b is, for example, 0.3 mm
  • the width D7 of each of the pair of electrodes 12E is, for example, 0.35 mm, which is opened from the outer periphery of the electrode 12E.
  • the distance D8 to the end of the portion 20 is 0.05 mm, for example, and the adjacent distance D9 of the pair of electrodes 12E is 0.3 mm, for example, and the width D10 of the insulating layer 13 left between the adjacent of the pair of electrodes 12E is For example, 0.2 mm.
  • the length D1 of the largest 1005 type chip part 16c is, for example, 1.0 ⁇ 0.05 mm
  • the electrode length D2 is, for example, 0.15-0.3 mm
  • the interelectrode length D3 is, for example, 0. 4 mm or more
  • width D 4 is, for example, 0.5 ⁇ 0.05 mm
  • height D5 is for chip capacitors, for example 0.5 ⁇ 0.05 mm, for chip resistors, for example, 0.35 ⁇ 0 05mm.
  • the length D6 of each of the pair of electrodes 12E in the mounting region of the chip part 16c is, for example, 0.4 mm
  • the width D7 of each of the pair of electrodes 12E is, for example, 0.55 mm.
  • the distance D8 to the end of the insulating layer 13 is, for example, 0.6 mm
  • the adjacent distance D9 of the pair of electrodes 12E is, for example, 0.05 mm
  • the width D10 of the insulating layer 13 left between the adjacent of the pair of electrodes 12E is, for example, 0 Te at 05mm.
  • the 0402 type chip component 16 is used to promote downsizing of the power module PM, in the mounting region of the 0402 type chip component 16a, an opening 20 is provided for each pair of electrodes 12E. It is possible to reduce the alignment margin between the opening 20 and the electrode 12E by forming a large opening 20 that covers both of the pair of electrodes 12E without forming a gap. Can be narrowed, which is preferable. In addition, in the case of the 0402 type chip component 16a, the distance between adjacent pairs of electrodes 16E is narrower than that of the 0603 type and 1005 type, so that the opening 20 is formed rather than forming the opening 20 for each pair of electrodes 12E.
  • solder flash chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease.
  • solder flash chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease.
  • solder flash chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease.
  • solder flash chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease.
  • solder flash problem occurs especially when the bump electrode 6 on the back side of the module board MCB is made of lead-free solder with a higher melting point than the adhesive 21 attached to the electrode 16E of the chip component 16a-16c. easy. This means that the solder reflow temperature when mounting on the mother board must be high (about 260 degrees), and when mounting on the mother board, it is necessary to mount the chip components in the power module PM. This is because the solder (Pb—Sn) remelts.
  • the insulation between the pair of electrodes 12E is applied when a desired metal is deposited on the pair of electrodes 12E of the module board MCB by a method such as a staking method.
  • a desired metal is likely to remain on the exposed surface of the layer 11
  • the problem of short circuit failure between the pair of electrodes 16E due to the solder flash and the metal residue described above is likely to occur.
  • the insulating layer 13 is left behind between the adjacent electrodes 12E of the module substrate MCB in the mounting area of the 0402 type chip component 16a.
  • the adjacent distance D9 between the pair of electrodes 12E is, for example, 0.175 mm or more.
  • the width of the insulating layer 13 left between the adjacent electrodes 12E (dimension in the direction in which the pair of electrodes 12E are arranged) D10, for example, 0.1 mm or more is necessary for processing.
  • the upper limit of the dimension D10 is not particularly limited if the length in the longitudinal direction of the chip part 16a (the direction in which the pair of electrodes 12E are arranged) is the upper limit, but it is, for example, about 0.4 mm.
  • the insulating layer 13 having the property of not being wetted by the solder is provided between the adjacent electrodes 12E of the module substrate MCB.
  • the remaining insulating layer 13 acts to stop the flow of the melted solder, thereby suppressing or preventing a short circuit failure between the pair of electrodes 16E of the chip component 16a caused by the solder flash. it can.
  • the insulating layer 13 is left between the pair of electrodes 12E. Therefore, the desired metal does not directly contact the insulating layer 11 and remains on the insulating layer 13.
  • the pair of electrodes of the chip component 16a resulting from the metal residue as described above can be suppressed or prevented.
  • the insulating layer 13 may overlap a part of the outer periphery of the pair of electrodes 12E.
  • the good dimension (overlap amount) is preferably about 0.2 mm, for example.
  • the length D6 of the pair of electrodes 12E in this case (the electrode 12E in this case refers to a region exposed from the insulating layer 13) is, for example, about 0.1 mm.
  • the same reasoning force as described above is obtained, and also in the mounting area of the module substrate MCB of the 0603 type and 1005 type chip components 16b and 16c, the insulating layer 13 is provided between the pair of electrodes 12E. Is left.
  • the chip parts 16b and 16c even in the chip parts 16b and 16c, the chip parts due to the short circuit failure between the pair of electrodes 16E of the chip parts 16b and 16c due to the solder flash and the metal residue due to the same action as the chip part 16a. Short circuit failure between the pair of electrodes 16E of 16b and 16c can be suppressed or prevented.
  • part of the insulating layer 13 may overlap with part of the outer periphery of the pair of electrodes 12E.
  • FIG. 12 shows an example of a cross-sectional view taken along line X2-X2 of FIG. 10 of a chip component (chip capacitor) 16 (16a-16c) having a capacitor.
  • a chip component 16 having a capacitor is formed between a pair of electrodes 16E, a plurality of internal electrodes 16IE electrically connected to and opposed to each other, and a facing surface of the plurality of internal electrodes 16IE. And a dielectric 16D.
  • the pair of electrodes 16E has a configuration in which, for example, a plating layer made of nickel, for example, and a plating layer also made of tin force, for example, are formed on the surface of the base electrode also having silver strength.
  • the internal electrode 16IE is made of, for example, palladium (Pd), copper, or nickel.
  • the dielectric 16D is made of, for example, titanium oxide, calcium zirconate or barium titanate.
  • the rated voltage of the 0402 type chip part 16a is, for example, about 16V
  • the capacitance value range is, for example, 2-6pF
  • the rated voltage of the 0603 type chip part 16b is, for example, 25V
  • capacity For example, the value range is 0.5-100 pF, 1005 type
  • the rated voltage of the chip component 16c is, for example, 50V
  • the capacitance value range is, for example, 0.5-lOOOOpF.
  • FIG. 13 shows a chip component having resistance (chip resistance) 16 (16a-16c) X2 in FIG.
  • the chip component 16 having resistance includes a substrate 16B, a pair of electrodes 16E formed at both ends in the longitudinal direction, an internal electrode 16IE electrically connected to each of the pair of electrodes 16E, and each internal electrode 16IE. And a protective film 16P that protects the resistor 16R and the internal electrode 16IE.
  • the substrate 16B is made of alumina, for example.
  • the configuration of the electrode 16E is almost the same as that described in FIG.
  • the internal electrode 16IE is made of a special metal film.
  • the resistor 16R also has a ruthenium oxide (RuO) material strength.
  • the protective film 16P is made of resin, for example.
  • the rated power of the 0402 type chip part 16a is, for example, about 0.03W
  • the rated power of the 0603 type chip part 16b is, for example, 0.05W
  • 1005 type chip part 16c is, for example, 0.063W.
  • FIG. 14 shows an example of a partially broken cross-sectional view of the chip component 16 (16a-16c) having an inductor, taken along line X2-X2 in FIG.
  • the chip component 16 having an inductor is wound around the outer periphery of the element body 16A, electrically connected to the element body 16A, a pair of electrodes 16E formed at both ends in the longitudinal direction, and the pair of electrodes 16E. And a coil conductor 16L and an outer resin 16D covering the coil conductor 16L.
  • the 0402 type chip component 16a By the way, considering only the miniaturization of the power module PM, it is preferable to use the 0402 type chip component 16a.
  • the use of the 0402 type chip component 16a in the installation location of the chip component 16 in the entire circuit of the power module PM adversely affects the efficiency of the high frequency characteristics. There are places where it is inappropriate to use the 0402 type chip part 16a, and it is not possible to make it all 0402 type. Also, simply using the 0402 type chip part 16a may cause problems. I found it. Therefore, in the first embodiment, the chip parts 16 having different types (dimensions) are used in accordance with the assembling locations of the chip parts 16 of the circuit of the power module PM.
  • FIG. 15 shows an example of a circuit diagram of the high frequency power amplifier circuit of the power module PM.
  • FIG. 16 shows an example of a circuit diagram in which the chip component 16 in the circuit diagram of FIG. Show.
  • the solid line indicates the RF signal wiring
  • the broken line indicates the power supply wiring
  • the two-dot chain line indicates the control signal wiring.
  • the power supply wiring includes a high-potential-side power supply wiring, a low-potential-side power supply wiring (a wiring for supplying a reference potential or a ground potential), and a bias wiring.
  • control signal wiring such as band Z mode switching switch signal wiring.
  • Reference numerals Ta3-Ta7, Tb3-Tb7 denote terminals of the power module PM.
  • the terminal Tal—Ta7 indicates an amplification system terminal for GSM850 and GSM900, and the terminal Tbl—Tb7 indicates an amplification system terminal for DCS1800 and DCS1900.
  • the symbols Pal 1 Pa 7, Pbl—Pb 7, Pel—Pc 3 indicate the pads P of the semiconductor chip 15.
  • FIG. 15 a matte hatching is added to the 0402 type chip part 16a for easy understanding of the drawing.
  • the element symbols of the 0402 type chip part 16a are shown as being surrounded by a square in order to make the drawing easy to see.
  • the 0402 type chip component 16a is mainly used in places where the applied voltage (or flowing current) is smaller than the voltage (or flowing current) applied to the 0603 or 1005 type chip components 16b and 16c. Yes.
  • capacitors CGI, Rl, R3, R5, etc. are formed on the 0402 type chip component 16a is illustrated.
  • Ferrite beads FBI, FB2, capacitors CA1-CA3, CB2, CB3, capacitors CG2-CG5, CP2-CP5, capacitor CG6, etc. are formed on 0603 type chip parts 16b, and inductors LG1, LP1, etc. are 1005 type
  • inductors LG1, LP1, etc. are 1005 type
  • the case where it is formed on the chip part 16c is illustrated.
  • Capacitor CG1 is a capacitor for the matching circuit of the RF input section that performs impedance matching between the weak RF signal input section and the first stage amplifier circuit section 2A1 transistor. It is electrically connected between the RF signal wiring that electrically connects the terminal Tal and the pad Pal that is electrically connected to the input of the first stage amplifier circuit section 2A1, and the ground potential. If this matching is not achieved, the input signal is reflected and the efficiency is lowered.
  • the current that flows in this capacitor CG1 is, for example, 20-30mA, and the applied voltage is For example, ov (which is hardly applied).
  • the resistor R1 is a bias resistor that determines the amount of fluctuation of the RF output, and is electrically connected between the nod Pel and the ground potential.
  • the current flowing through the resistor R1 is, for example, 0.3 mA, and the applied voltage is, for example, 1.55V.
  • Resistor R3 is a bias resistor that determines the point at which RF output begins to be output, and is electrically connected between node Pc2 and the ground potential.
  • the current flowing through the resistor R3 is, for example, 0.27 mA, and the applied voltage is, for example, 1.39V.
  • Resistor R5 is a chip component 16 that forms a detection circuit together with capacitor CG6, and has the function of canceling the reflected wave of the RF signal picked up by capacitor CG6 and picking up only the necessary traveling wave, pad Pc3 And the capacitor CG6 are electrically connected between the wiring and the ground potential.
  • the current flowing through the resistor R5 is, for example, 20-30 mA, and the applied voltage is, for example, OV (almost not applied).
  • the current flowing through the capacitor CG6 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
  • Ferrite beads FBI, FB2, and capacitor CA1 are the first-stage power supply circuit, which plays a role of preventing oscillation as an RF filter, and the power supply (direct current (DC )) Has a role to prevent malfunction.
  • the current flowing through the ferrite beads FBI, FB2 and capacitor CA1 is, for example, 0.11A, and the applied voltage is, for example, 3.5V.
  • Capacitors CA2 and CB2 are the second-stage power supply circuit, and their roles are the same as those of the first-stage power supply circuit.
  • RF filters are formed by the capacitors CA2 and CB2 and the line (wiring 12) on the module board MCB.
  • the current flowing through the capacitor CA2 is, for example, 0.3A, and the applied voltage is, for example, 3.5V.
  • Capacitors CA3 and CB3 and inductors LG1 and LP1 are the third-stage power supply circuit, and function as an RF filter to prevent oscillation.
  • the current flowing through the capacitors CA3 and CB3 and the inductors LG1 and LP1 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
  • Capacitors CG2—CG5, CP2—CP5 are capacitors for matching circuits in the RF output section that perform impedance matching between the output section and the transistors in the third-stage amplifier circuit sections 2A3, 2B3. Since the RF signal output is large and the impedance difference is large, many parts are used.
  • the current flowing through the capacitors CG2-CG5, CP2-CP5 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
  • FIG. 17 is an enlarged plan view of the mounting area of the module substrate MCB of the power module PM according to the second embodiment and is mounted on the chip component 16 (16a)
  • FIG. 18 is a chip on the module substrate MCB of FIG. Fig. 19 is a cross-sectional view taken along line X3-X3 in Fig. 18, and
  • Fig. 20 is an enlarged view of the main part of the module board MCB between the pair of electrodes 12E in Fig. 19. Each cross-sectional view is shown.
  • the insulating layer 13 since the insulating layer 13 must be left between the pair of electrodes 12E, reduction of the distance between the pair of electrodes 12E is hindered. This is particularly a problem when chip components 16 smaller than 0402 type are mounted. Therefore, in the second embodiment, the insulating layer 13 is not left between the pair of electrodes 12E in the mounting region of the 0402 type chip component 16a or the smaller chip component 16 and the pair of electrodes 12E A large opening 20 was formed so as to include the space between the pair of electrodes 12E. In this case, since it is not necessary to leave the insulating layer 13 between the pair of electrodes 12E, it is possible to narrow the space between the pair of electrodes 12E.
  • the opening portion of the mounting area of the 0402 type chip component 16a or the chip component 16 smaller than that, and the insulating layer 11 between the pair of electrodes 12E where the force is exposed are viewed in a plane.
  • a plurality of grooves 25 extending in a direction perpendicular to the direction in which the pair of electrodes 12E are arranged and recessed in the thickness direction of the module substrate MC when viewed in cross section.
  • the distance between the pair of electrodes 12E can be increased compared to the case where the groove 25 is not provided, so that the short-circuit failure between the pair of electrodes 12E and 16E due to the solder flash or the metal residue is suppressed or prevented. it can.
  • FIG. 21 is a mounting surface of the module substrate MCB of the power module PM according to the third embodiment, and is an enlarged plan view of the mounting region of the chip component 16 (16a), and FIG. 22 is a chip on the module substrate MCB of FIG. Fig. 2 is an enlarged plan view showing the part 16 (16a) mounted 3 is a cross-sectional view taken along the line X4-X4 in FIG. 22, and FIG. 24 is an enlarged cross-sectional view of the main part of the module board MCB between the pair of electrodes 12E in FIG.
  • the groove formed in the insulating layer 11 between the pair of electrodes 12E exposed from the opening 20 in the mounting region of the 0402 type chip component 16a or the smaller chip component 16 is provided.
  • the insulating layer 13 is embedded at 25 mm.
  • the insulating layer 13 having the property of not being wetted by the solder is left between the pair of electrodes 12E, a short circuit failure between the pair of electrodes 12E and 16E due to the solder flash can be suppressed or prevented.
  • the desired metal is deposited on the surface of the pair of electrodes 12E by a method such as the above, the insulating layer 13 is embedded in the groove 25 between the pair of electrodes 12E. It is possible to prevent direct contact with the insulating layer 11 where the groove 25 is formed. As a result, as described in the first embodiment, it is possible to suppress or prevent a short circuit failure between the pair of electrodes 12E due to the metal residue.
  • FIG. 25 is a mounting surface of the module substrate MCB of the power module PM according to the fourth embodiment, and is an enlarged plan view of the mounting region of the chip component 16 (16a).
  • FIG. 26 is a chip on the module substrate MCB of FIG.
  • FIG. 27 is a cross-sectional view taken along line X5-X5 in FIG. 26, and
  • FIG. 28 is a cross-sectional view taken along line X6-X6 in FIG. 26, respectively, showing a state where the component 16 (16a) is mounted. Note that in FIG. 26, the chip component 16 is shown in a transparent manner for easy viewing of the drawing.
  • the pair of electrodes 12E of the module board MCB is electrically connected to the pair of electrodes 16E of the chip component 16 through the portions exposed from the openings 20a and 20b.
  • the opening 20a that exposes one electrode 12E is, for example, a flat concave shape, and the exposed shape of the electrode 12E exposed from the opening 20a is also a flat concave shape.
  • the opening 20b that exposes the other electrode 12E is, for example, a planar convex shape, and the exposed shape of the electrode 12E exposed from the opening 20b is also a planar convex shape.
  • the pair of electrodes 12E! A part of is covered.
  • the width D20 of the insulating layer 13 can be made larger than the adjacent interval D9. That is, even when the adjacent distance D9 between the pair of electrodes 12E is the same as or smaller than that of the first embodiment, the insulating layer 13 can be easily formed between the pair of electrodes 12E. Therefore, even when the 0402 type or smaller chip component 16 is mounted, a pair of chip components 16 caused by the solder flash and the metal residue is used for the same reason as described in the first embodiment. Short circuit failure between the electrodes 16E can be suppressed or prevented.
  • FIG. 29 is a mounting surface of the module substrate MCB of the power module PM according to the fifth embodiment, and is an enlarged plan view of the mounting area of the chip component 16 (16a).
  • FIG. 30 is a chip on the module substrate MCB of FIG.
  • FIG. 31 is a cross-sectional view taken along line X7—X7 in FIG. 30, and
  • FIG. 32 is a cross-sectional view taken along line X8—X8 in FIG. Note that in FIG. 30, the chip component 16 is shown in a transparent manner for easy viewing of the drawing.
  • the adjacent distance D21 between the pair of electrodes 12E in the mounting area of the chip component 16 smaller than the 0402 type chip component 16a is equal to the longitudinal length D22 of the chip component 16. .
  • the insulating layer 13 is left between the pair of electrodes 12E in a state in which the width D10 described in the first embodiment 1 is secured.
  • a convex portion 12E1 extending toward the adjacent center of the pair of electrodes 12E is formed in the center of each of the opposing sides of the pair of electrodes 12E.
  • the convex portion 12E1 has a function for promoting the adhesion of solder to the electrode 16E of the chip component 16 when the chip component 16 is mounted.
  • the insulating layer 13 can be left between the pair of electrodes 12E without impairing the electrical connectivity between the chip component 16 smaller than the 0402 type and the pair of electrodes 12E. Therefore, even when the chip component 16 smaller than the 0402 type is mounted, for the same reason as described in the first embodiment, between the pair of electrodes 16E of the chip component 16 due to the solder flash and the metal residue. Can prevent or prevent short circuit defects. [0077] (Embodiment 6)
  • a multilayer ceramic substrate is prepared. On this multilayer ceramic substrate, a plurality of module substrate MCB formation regions are arranged.
  • the surface electrode 12E and the insulating layer 13 of the multilayer ceramic substrate are formed as follows.
  • FIG. 34 is an enlarged cross-sectional view of the main part of the multilayer ceramic substrate MCBm during the manufacturing process.
  • a printing mask 30 for forming the insulating layer 13 is prepared.
  • FIG. 35 is a cross-sectional view of the main part of the printing mask 30.
  • the printing mask 30 has, for example, a metal thin plate force, and an opening 30a penetrating the main back surface is formed at a desired location. Subsequently, as shown in FIG.
  • FIG. 36 is a cross-sectional view of the main part in a state where the multilayer ceramic substrate MCBm and the printing mask 30 are overlaid.
  • FIG. 37 is a cross-sectional view of the principal parts of the multilayer ceramic substrate MCBm and the printing mask 30 during the printing process.
  • FIG. 38 is a cross-sectional view of a principal part of the multilayer ceramic substrate MCBm. 39 and 40 show an example of an enlarged sectional view of the insulating layer 13 portion between the pair of electrodes 12E.
  • the side surface of the insulating layer 13 is substantially perpendicular to the main surface of the multilayer ceramic substrate MCBm.
  • the side surface of the insulating layer 13 may be inclined with respect to the main surface of the multilayer ceramic substrate MCB. That is, a taper may be formed on the side surface of the insulating layer 13.
  • the width D10 is a relatively wide width on the lower bottom side, which is 0.1 mm or more as described in the first embodiment.
  • a solder paste material having a Pb—Sn (PbZSn ratio of 37Z63 (eutectic solder)) force is applied to the main surface of the multilayer ceramic substrate MCBm in the same manner as described above.
  • Printing is performed by using a printing mask.
  • the semiconductor chip 15 and the chip After mounting the chip component 16 (16a-16c) as shown in FIG. 41, a pair of electrodes of the chip component 16 is applied by performing a heating (one riff mouth) process as shown in step S4 of FIG. 16E and the pair of electrodes 12E on the main surface of the multilayer ceramic substrate MCBm are connected via the solder paste (adhesive 21).
  • the heating temperature (reflow temperature) at this time is set to a temperature at which the solder paste is melted.
  • the ratio of PbZSn is 37Z63 (eutectic solder), for example, it is about 183 degrees.
  • step S7 of FIG. 33 for example, a silicone resin or a low-elastic epoxy resin so as to collectively cover the formation areas of the plurality of module substrates MCB on the main surface of the multilayer ceramic substrate MCBm.
  • the sealing member 8 having equal force is formed by the same printing method as described above.
  • step S8 of FIG. 33 the sealing member 8 is cured by performing a beta (heating) process.
  • step S9 of FIG. 33 the multilayer ceramic substrate MCCBm is cut into individual modules PM, and a plurality of modules PM are cut out (individualization step).
  • step S8 and step S9 or between step S10 and step S11 bumps made of the lead-free solder solder are applied to each of the plurality of electrodes (external connection electrodes) on the back surface of the module board MCB.
  • Connect electrode 6 When bump electrode 6 is connected between steps S8 and S9 before cutting multilayer ceramic substrate MCBm, bump electrode 6 can be connected to multiple module substrates on multilayer ceramic substrate MCBm. Process simplification and manufacturing time can be shortened.
  • the bump electrode 6 may be a gold (Au) bump instead of the lead-free solder bump. Furthermore, here, the force described for connecting the bump electrode 6 may be shipped without connecting the bump electrode 6 (product of LGA package configuration).
  • the lead-free solder paste is applied to the electrodes on the main surface of the mother board MB as shown in step S22. Is printed by a method using a print mask similar to the above.
  • the steps in Figure 33 As shown in step S23, the power module PM is mounted on the main surface of the mother board MB. That is, as shown in FIG. 42, the bump electrode 6 of the power module PM and the electrode 35 on the main surface of the mother board MB are aligned.
  • FIG. 42 is a cross-sectional view of the main part of the mother board MB during the power module mounting process.
  • FIG. 43 is a cross-sectional view of the main part of the mother board MB after the mounting process of the power module PM.
  • the heating temperature (reflow temperature) at this time is set to a temperature at which the solder paste made of lead-free solder is melted.
  • the solder reflow temperature when mounting on this motherboard MB is the above step S4.
  • the temperature must be higher than the temperature at (eg about 260 degrees).
  • the solder (Pb—Sn) for mounting the chip components in the power module PM is remelted, and the pair of electrodes 16E (or the pair of electrodes 12E) are short-circuited. In some cases (solder flash).
  • the insulating layer 13 is left between the pair of electrodes 12E, and this acts as a barrier against the molten solder.
  • the short circuit failure between the pair of electrodes 16E of the chip component 16 to be performed can be suppressed or prevented.
  • the lead-free solder or gold forming the bump electrode 6 and the solder paste 36 are mixed in the bump electrode 6 in the stage of FIG. As described above, do not connect the bump electrode 6 to the electrode (external connection electrode) on the back of the power module PM! ⁇
  • the electrode on the back of the power module PM and the motherboard MB The electrode 35 is connected to the solder paste 36. After that, as shown in steps S25 and S26 in FIG. 33, an electrical characteristic test is performed to complete the secondary mounting.
  • GSM850, GSM900, GSM1800, and GSM19 The power described when applied to a four-band mobile phone capable of handling radio waves in the four frequency bands of 00.
  • a four-band mobile phone capable of handling radio waves in the four frequency bands of 00.
  • This is not limited to this example.
  • it handles radio waves in the two frequency bands of GSM90 0 and GSM1800.
  • It can also be applied to dual-band mobile phones that can handle radio waves in the three frequency bands of GSM900, GSM1800, and GSM1900.
  • the present invention is not limited to this.
  • the present invention can also be applied to mobile information processing devices such as PDAs (Personal Digital Assistants) having a communication function, and information processing devices such as personal computers having a communication function.
  • PDAs Personal Digital Assistants
  • the electronic device of the present invention is, for example, a mobile electronic device such as a mobile phone, a mobile information processing device such as a PDA having a communication function, a personal computer having a communication function, or the like. It can be used for information processing devices.

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Abstract

Etant donné qu’une partie qui est inadaptée pour l'utilisation d'un composant de puce de type 0402 et qui provoque des effets défavorables sur l’efficacité de caractéristiques de haute fréquence, par exemple, existe parmi des parties d’incorporation de composants de puces dans le circuit entier d’un module de puissance RF lorsque le composant de puce de type 0402 est utilisé, un composant de puce de dimensions différentes est utilisé selon la partie d’incorporation du composant de puce dans le circuit entier du module de puissance RF. Dans le circuit du module de puissance RF, le composant de puce de type 0402 de faibles dimensions est connecté électriquement à une partie étant appliquée avec une tension inférieure à celle appliquée à un composant de puce de type 1005 ou de type 0603 de grandes dimensions.
PCT/JP2004/016324 2004-11-04 2004-11-04 Dispositif electronique et procede de fabrication de dispositif electronique WO2006048932A1 (fr)

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JP2011134956A (ja) * 2009-12-25 2011-07-07 Shinko Electric Ind Co Ltd 半導体装置
JP2014239207A (ja) * 2013-05-10 2014-12-18 株式会社村田製作所 コンデンサ素子の実装構造体およびコンデンサ素子の実装方法
CN104822231A (zh) * 2014-01-31 2015-08-05 株式会社村田制作所 电子部件的安装构造体
US20190341191A1 (en) * 2018-01-31 2019-11-07 Tdk Corporation Electronic component

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