WO2006048932A1 - Electronic device and electronic device manufacturing method - Google Patents

Electronic device and electronic device manufacturing method Download PDF

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Publication number
WO2006048932A1
WO2006048932A1 PCT/JP2004/016324 JP2004016324W WO2006048932A1 WO 2006048932 A1 WO2006048932 A1 WO 2006048932A1 JP 2004016324 W JP2004016324 W JP 2004016324W WO 2006048932 A1 WO2006048932 A1 WO 2006048932A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic device
wiring board
electrodes
pair
main surface
Prior art date
Application number
PCT/JP2004/016324
Other languages
French (fr)
Japanese (ja)
Inventor
Hiroki Noto
Tomoaki Kudaishi
Yusuke Sato
Satoru Konishi
Masashi Okano
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to PCT/JP2004/016324 priority Critical patent/WO2006048932A1/en
Priority to JP2006542202A priority patent/JPWO2006048932A1/en
Publication of WO2006048932A1 publication Critical patent/WO2006048932A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
    • H05K1/0262—Arrangements for regulating voltages or for using plural voltages
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
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    • H05K1/111—Pads for surface mounting, e.g. lay-out
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    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to an electronic device technology, and more particularly to a technology effective when applied to an RF (Radio Frequency) power module.
  • RF Radio Frequency
  • the RF power module examined by the present inventors is an electronic component for signal amplification of a portable communication device such as a mobile phone, for example, and includes a plurality of semiconductor chips having a transistor for signal amplification, and A plurality of chip components having passive elements are mounted on a module substrate, and these are electrically connected to each other.
  • the chip component is mounted on the module substrate with its electrodes connected via a solder or the like to a pair of electrodes exposed from the opening formed in the insulating layer on the mounting surface of the module substrate.
  • the chip component is described in, for example, Japanese Patent Laid-Open No. 5-326632, and the pair of electrodes of the chip component is an opening formed in an insulating layer formed on the mounting surface of the substrate.
  • a configuration is disclosed in which an insulating layer between adjacent electrodes of the substrate is also removed and the substrate surface is exposed (see Patent Document 1).
  • Patent Document 1 JP-A-5-326632
  • the chip components of the 0402 type which are smaller than those of the current mainstream 1005 type and 0603 type chip components, are used as the chip components constituting the RF power module. Therefore, it is considered to realize higher density mounting.
  • the use of the 0402 type chip component in the chip component installation location in the entire circuit of the RF power module adversely affects the efficiency of the high frequency characteristics.
  • the distance between the electrodes of the chip component is narrow, so the distance between the pair of electrodes on the module substrate to which the electrode of the chip component is connected is also narrow. Therefore, the opening formed in the insulating layer on the module substrate is not formed so as to expose each of the pair of adjacent electrodes, but the pair of adjacent electrodes and the module substrate surface therebetween are exposed.
  • solder flash a phenomenon in which the solder attached to the electrode of the chip component melts and expands when the RF power module is mounted and breaks the sealing resin
  • solder flash a phenomenon in which the solder attached to the electrode of the chip component melts and expands when the RF power module is mounted and breaks the sealing resin
  • This solder flash problem is particularly likely to occur when the solder bumps on the back side of the module board are made of lead-free solder and the melting point of the solder bumps is higher than the melting point of the solder attached to the chip component electrode.
  • An object of the present invention is to provide a technique capable of reducing the size of an electronic device.
  • Another object of the present invention is to provide a technique capable of suppressing or preventing a short circuit failure between a pair of electrodes of an electronic component constituting an electronic device.
  • the present invention uses electronic components having different dimensions depending on the place where the electronic component is incorporated in the high-frequency power amplifier circuit.
  • the present invention is such that an insulating layer remains on the wiring board between the pair of electrodes of the electronic component in the high-frequency power amplifier circuit.
  • FIG. 1 is an explanatory diagram of an example of a mobile phone system having an electronic device according to an embodiment of the present invention.
  • FIG. 2 is a circuit block diagram of an example of an electronic device in the mobile phone system of FIG.
  • FIG. 3 is an explanatory diagram of an example of mounting an electronic device in the mobile phone system of FIG. 1.
  • FIG. 4 is a plan view of an example of a main surface of a wiring board of an electronic device.
  • FIG. 5 is a plan view of an example of the back surface of the wiring board of FIG.
  • FIG. 6 is a cross-sectional view taken along line XI—XI in FIG.
  • FIG. 7 is a cross-sectional view of an essential part of an example of a semiconductor chip when a semiconductor amplifying element constituting an amplifier circuit part of an electronic device is formed by an LDMOSFET.
  • FIG. 8 is a fragmentary cross-sectional view of an example of a semiconductor chip when a semiconductor amplifying element constituting an amplifier circuit portion of an electronic device is formed of a heterojunction bipolar transistor.
  • FIG. 9 is an enlarged plan view of a component mounting surface of the wiring board of FIG. 4 and a chip component mounting region. [10] FIG. 9 is an enlarged plan view of the wiring board showing a state where the chip components are mounted in FIG.
  • FIG. 11 is a sectional view taken along line X 2 -X 2 in FIG.
  • FIG. 12 is a cross-sectional view of an example of the X2-X2 line in FIG. 10 of the chip part having a capacitor.
  • FIG. 13 is a cross-sectional view of an example of the X2-—X2 line in FIG. 10 of the chip component having a resistor.
  • FIG. 14 is a partially broken cross-sectional view of an example of the X2-X2 line in FIG. 10 of the chip component having an inductor.
  • FIG. 15 is a circuit diagram of an example of a high frequency power amplifier circuit of an electronic device.
  • FIG. 16 is a circuit diagram of an example in which chip components in the circuit diagram of FIG. 15 are indicated by element-level graphic symbols.
  • FIG. 17 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is another embodiment of the present invention, and a mounting region of a chip component.
  • FIG. 18 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
  • FIG. 19 is a cross-sectional view taken along line X3-X3 in FIG.
  • FIG. 20 is an enlarged cross-sectional view of a main part of a wiring board between a pair of electrodes in FIG.
  • FIG. 21 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is another embodiment of the present invention, and a mounting region of a chip component.
  • FIG. 22 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
  • FIG. 23 is a cross-sectional view taken along line X4-X4 in FIG.
  • FIG. 24 is an enlarged cross-sectional view of a main part of the wiring board between a pair of electrodes in FIG. 23.
  • FIG. 25 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is still another embodiment of the present invention, and a chip component mounting region.
  • FIG. 26 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
  • FIG. 27 is a sectional view taken along line X5-X5 in FIG.
  • FIG. 28 is a cross-sectional view taken along line X6—X6 of FIG.
  • FIG. 29 An enlarged plan view of a component mounting surface of a wiring board of an electronic device according to another embodiment of the present invention, which is a mounting region of a chip component.
  • FIG. 30 is an enlarged plan view showing a state where chip components are mounted on the wiring board of FIG.
  • FIG. 31 is a cross-sectional view taken along line X7—X7 of FIG.
  • FIG. 32 is a cross-sectional view taken along line X8—X8 of FIG.
  • FIG. 33 is a flowchart of a manufacturing process of the electronic device according to the embodiment of the invention.
  • FIG. 34 is an essential part enlarged cross-sectional view of the multilayer ceramic substrate during the manufacturing process of the electronic device according to one embodiment of the present invention.
  • FIG. 35 is a fragmentary cross-sectional view of a printing mask used in the manufacturing process of the electronic device according to one embodiment of the present invention.
  • FIG. 36 is a cross-sectional view of a principal part in a state where the multilayer ceramic substrate of FIG. 34 and the printing mask of FIG. 35 are overlaid.
  • FIG. 37 is a cross-sectional view of main parts of a multilayer ceramic substrate and a printing mask during a printing process.
  • FIG. 38 is a cross-sectional view of a principal part of a multilayer ceramic substrate.
  • FIG. 39 is an enlarged cross-sectional view of an example of an insulating layer portion between a pair of electrodes on the main surface of a multilayer ceramic substrate.
  • FIG. 40 is an enlarged sectional view of another example of the insulating layer portion between a pair of electrodes on the main surface of the multilayer ceramic substrate.
  • FIG. 41 is a fragmentary cross-sectional view of the multilayer ceramic substrate after a chip component mounting step.
  • FIG. 42 is a fragmentary cross-sectional view of the mother board during the mounting process of the electronic device.
  • FIG. 43 is a fragmentary cross-sectional view of the mother board after the mounting process of the electronic device.
  • GSM Global System for Mobile Communication
  • GSM Global System for Mobile Communication
  • GSM Global System for Mobile Communication
  • GSM Global System for Mobile Communication
  • GSM has three frequency bands of radio waves to be used: 900 MHz band is GSM900 or simply GSM, 1800 MHz band is GSM1 800 or DCS (Digital Cellular System) 1800 or PCN, 1900 MHz band is GS Ml 900 or DCS 1900 or PCS (Personal Communication Services).
  • GSM1900 is mainly used in North America. In North America, the GSM850 in the 850MHz band may also be used.
  • the GMSK modulation method is a method used for communication of an audio signal. In this method, the phase is shifted according to the data.
  • the EDGE modulation method is a method used for data communication, in which an amplitude shift is added to the phase shift of GMSK modulation.
  • Fig. 1 shows an example of DPS, a digital mobile phone system that transmits information using a GSM network, for example.
  • This digital cellular phone system DPS is constructed by modules, circuits and elements mounted on the motherboard MB.
  • Symbol PM is an RF (Radio Frequency) power module (hereinafter simply referred to as a power module) that is the electronic device of the first embodiment
  • symbol ANT is an antenna for transmitting and receiving signal radio waves
  • symbol FEM is a front end module.
  • the code BBC converts the audio signal into a baseband signal, converts the received signal into an audio signal, generates the modulation system switching signal and the band switching signal, and the code FMC downcodes the received signal.
  • Modulation / demodulation circuits FLT1 and FLT2 that demodulate and demodulate to generate a baseband signal and modulate the transmission signal are filters that remove noise and interference from the received signal power.
  • Filter FLT1 is for GSM and filter FLT2 is for DCS.
  • the baseband circuit BBC is composed of a plurality of semiconductor integrated circuits such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory.
  • the front end module FEM has low-pass filters LPFl and LPF2, switch circuits SWl and SW2, capacitors CI and C2, and a duplexer WDC.
  • Low-pass filters LPFl and LPF2 are circuits that attenuate harmonics
  • switch circuits SWl and SW2 are switch circuits for switching transmission and reception signals
  • capacitors CI and C2 are elements that cut the DC component from the received signal
  • duplexer WDC is It is a circuit that demultiplexes GSM900 band signals and DCS1 800 band signals, and these circuits and elements are mounted on a single circuit board as a module.
  • the switching signals C NT1 and CNT2 of the switch circuits SWl and SW2 are supplied from the baseband circuit BBC.
  • FIG. 2 shows an example of a circuit block diagram of the power module PM.
  • the noise module PM can use four frequency bands, e.g. GSM850, GSM900, DCS1800 and DCS1900 (four-band method), and GMS K (Gaussian filtered Minimum Shift Keying) and EDGE (Enhanced Data) in each frequency band.
  • GSM Environment It is configured to be able to use two communication systems with modulation system! /
  • This power module PM includes an amplifier circuit unit 2A for GSM850 and GSM900, an amplifier circuit unit 2B for DCS1800 and DCS1900, and a peripheral circuit that controls and corrects the amplification operation of these amplifier circuit units 2A and 2B. And 3.
  • Each amplifier circuit section 2A, 2B has three amplifier circuit sections 2A1-2A3, 2B1-2B3 connected in series, and four impedance matching circuits 2 AM1-2AM4, 2BM1-2BM4.
  • the input terminals Tal and Tbl of the power module PM are electrically connected to the inputs of the first stage amplification circuit sections 2A1 and 2B1 via the impedance matching circuits 2AM1 and 2BM1 of the input stage, and are connected to the first stage.
  • the output of the second amplification circuit section 2A1, 2B1 is electrically connected to the input of the second stage amplification circuit section 2A2, 2B2 via the interstage impedance matching circuit 2AM2, 2BM2, and the second stage amplification circuit
  • the outputs of the parts 2A2 and 2B2 are electrically connected to the inputs of the final stage amplifier circuit parts 2A3 and 2B3 via the interstage impedance matching circuits 2A M3 and 2BM3.
  • the outputs of the final stage amplifier circuits 2A3 and 2B3 are electrically connected to the output terminals Ta2 and Tb2 via the impedance matching circuits 2AM4 and 2BM4 of the output stage.
  • the peripheral circuit 3 includes a control circuit 3A, a bias circuit 3B for applying a bias voltage to the amplifier circuit units 2A1-2A3, 2B1-2B3, and the like.
  • the control circuit 3A is a circuit that generates a desired voltage to be applied to the amplification circuit units 2A and 2B, and includes a power supply control circuit 3A1 and a bias voltage generation circuit 3A2.
  • the power supply control circuit 3A1 is a circuit that generates a first power supply voltage to be applied to the drain terminals of the power MOS FETs for output of each of the amplification circuit sections 2A1-2A3, 2B1-2B3.
  • the bias voltage generation circuit 3 A2 is a circuit that generates a first control voltage for controlling the bias circuit 3B.
  • the bias voltage generation circuit 3A2 Based on the first power supply voltage generated by the power supply control circuit 3A1, the first control voltage is generated! /
  • the baseband circuit BBC is a circuit that generates the output level designation signal.
  • This output level designation signal is a signal that designates the output level of the amplifier circuits 2A and 2B, and is generated based on the distance between the mobile phone and the base station, that is, the output level according to the strength of the radio wave. And become like! /
  • FIG. 3 shows an implementation example of the power module PM of the digital cellular phone system DPS shown in FIG.
  • the mother board MB is, for example, a printed wiring board having a multilayer wiring structure, and a power module PM and a plurality of chip components 5 are mounted on the main surface thereof.
  • the power module PM is connected via a bump electrode (external terminal, protruding electrode) 6 connected to each of a plurality of electrodes (external connection electrodes) on the back surface (module mounting surface) of the module board (wiring board) MC B. It is mounted on the main surface of one board MB.
  • the power module PM has a so-called BGA (Ball Grid Array) package configuration in which a plurality of protruding bump electrodes 6 are arranged in an array on the module mounting surface. Further, the chip component 5 is mounted on the main surface of the mother board MB via the bonding material 7.
  • the material of the bump electrode 6 and the bonding material 7 includes, for example, a tin-silver-based lead-free (lead-free) solder (such as a tin “!
  • tin-copper-based lead-free solder such as tin-nickel (Ni) alloy (melting point: about 227 degrees)
  • tin-zinc-based lead-free solder such as tin-zinc (Zn) alloy ( Melting point: about 198 degrees)
  • tin-bismuth-based lead-free solder Melting point: about 148 degrees
  • tin-bismuth silver alloy or lead-free solder of tin antimony (Sb) alloy is used.
  • the power module PM and the chip component 5 are electrically connected to each other through the wiring of the mother board MB to form the digital mobile phone system DPS.
  • the main surface (mounting part mounting surface) of the module board MC B is covered with, for example, a silicone rubber (silicone resin) or an epoxy resin, and the like, and is mounted on the main surface of the module board MCB. Electronic components such as semiconductor chips and chip components described later are sealed.
  • the bump electrode 6 of the power module PM may be made of gold (Au) in addition to lead-free solder.
  • the power module PM package configuration may be a so-called LGA (Land Grid Array) package configuration in which a plurality of flat electrode pads are arranged in an array on the module mounting surface.
  • FIG. 4 is a plan view of an example of the main surface (part mounting surface) of the module board MCB of the power module PM
  • FIG. 5 is the back surface (module mounting surface) of the module board MCB of FIG.
  • FIG. 6 shows an example of a cross-sectional view taken along line XI-XI in FIG.
  • X represents the first direction
  • Y represents the second direction orthogonal to the first direction X.
  • the module substrate MCB has a multilayer wiring structure in which insulating layers 11 and wirings 12 are alternately laminated and integrated.
  • Wiring 12 and via 12V are formed in the inner layer of module board MCB.
  • the wiring 12 of each layer of the module board MCB is electrically connected through the via 12V!
  • the inner layer wiring 12 and via 12V are made of, for example, an alloy of copper (Cu) and tungsten (W).
  • the component mounting surface (main surface, first surface) of the uppermost insulating layer 11 and the module mounting surface of the lowermost insulating layer 11 Wiring 12 and electrodes (land, terminal, conductor pattern) 12E are formed on the back surface and the second surface.
  • the wiring 12 and the electrode 12E are made of, for example, a alloy of copper (Cu) and tungsten (W), and nickel (Ni) plating and gold (Au) plating are sequentially applied to the surface with lower layer force! / RU Furthermore, the component mounting surface of the uppermost insulating layer 11 and the module mounting surface of the lowermost insulating layer 11 are wetted by solder (lead (Pb) —tin (Sn)) such as overcoat glass (silicon). However, an insulating layer 13 having properties may be formed so as to cover the surface of the wiring 12! A part of the insulating layer 13 is opened, and the force electrode 12E is exposed there.
  • solder lead (Pb) —tin (Sn)
  • the wide electrode 12E1 at the center of the back surface of the module substrate MCB is an electrode for a reference potential (ground potential GND, for example, OV).
  • the electrode 12E2 at the outer peripheral corner of the back surface of the module substrate MCB is an RF signal electrode.
  • the electrode 12E3 on the outer periphery of the back surface of the module board MCB is an electrode for supplying a bias voltage.
  • the electrode 12E4 on the outer periphery of the back surface of the module board MCB is an electrode for control signals.
  • one semiconductor chip (electronic component) 15 is mounted on the component mounting surface of the module board MCB, and for example, three types of chip components (electronic component and passive component) of different sizes 16 (16a-16c) is implemented.
  • the semiconductor chip 15 is well mounted in a substantially rectangular recess 17 called a cavity at the center of the main surface of the module substrate MCB with its main surface (device forming surface) facing upward. .
  • the semiconductor chip 15 is formed with three stages of amplification circuit sections 2A1-2A3 for GSM850 and GSM900 and three stages of amplification circuit sections 2B1, 2B3 for DCS1800 and DCS1900.
  • a plurality of bonding pads (external terminals: hereinafter simply referred to as pads! /) Are formed along the outer periphery.
  • the node P is a lead electrode for a circuit formed on the semiconductor chip 15.
  • each electrode 12E is formed integrally with the wiring 12 on the main surface of the module substrate MCB.
  • Each of the electrodes 12E and the semiconductor layer 15 are connected to each other through a bonding wire (hereinafter simply referred to as a wire) BW connected in contact therewith. Yes.
  • the wire BW is made of, for example, gold (Au).
  • the back surface of the semiconductor chip 15 is connected to the electrode 12E on the bottom surface of the recess 17 of the module substrate MCB, and is further electrically connected to the electrode 12E1 on the back surface of the module substrate MCB through vias 12V.
  • FIG. 7 shows a semiconductor in which the semiconductor amplifying elements constituting the amplifying circuit portions 2A1-2A3, 2B1-2B3 are formed by LDMOSFETs (Laterally Diffused Meta-Oxide-Semiconductor Field Effect Transistors). An example of a cross-sectional view of the main part of the chip 15 is shown.
  • LDMOSFETs Laser Diffused Meta-Oxide-Semiconductor Field Effect Transistors
  • An epitaxial layer 202 made of p-type single crystal silicon is formed on the main surface of the semiconductor substrate 201 that also has p + type single crystal silicon force, and an L DMOSFET is formed on a part of the main surface of the epitaxial layer 202.
  • a P-type well 203 is formed, which functions as a punch-through streak that suppresses the extension of the depletion layer from the drain to the source.
  • an LDMOSFET gate electrode 205 is formed through a gate insulating film 204 made of silicon oxide or the like.
  • the gate electrode 205 is made of, for example, a laminated film of an n-type polycrystalline silicon film and a metal silicide film, and a sidewall spacer 206 having a force such as silicon oxide is formed on the side wall of the gate electrode 205.
  • the source and drain of the LDMOSFET are formed.
  • the drain is an n-type offset drain region 207 that is in contact with the channel formation region, an n-type offset drain region 208 that is in contact with the n-type offset drain region 207 and is separated from the channel formation region force, and an n-type offset.
  • the n + type drain region 209 formed in contact with the drain region 208 and further away from the channel formation region also acts as a force.
  • n-type offset drain region 207 closest to gate electrode 205 has the lowest impurity concentration and is the farthest away from gate electrode 205.
  • the interstitial n + type drain region 209 has the highest impurity concentration.
  • the source of the LDMOSFET is formed in contact with the n-type source region 210 in contact with the channel formation region, and in contact with the n- type source region 210, and is separated from the channel formation region, and has an impurity concentration higher than that in the n-type source region 210.
  • a p-type halo region 212 is formed below the n-type source region 210.
  • a p-type punching layer 214 in contact with the n + type source region 211 is formed at the end of the n + type source region 211 (the end opposite to the side in contact with the n ⁇ type source region 210).
  • the p-type punching layer 214 is a conductive layer for electrically connecting the source of the LDMOSFET and the semiconductor substrate 201, for example, a p-type polycrystalline silicon embedded in the groove 213 formed in the epitaxial layer 202. Formed by a film.
  • LDMOSFET p-type punch layer 214 (p + type semiconductor region 215), source (n + type source region 211), and drain (n + type drain region 209) are respectively formed on top of silicon nitride film 221 and oxide.
  • a plug 224 in a contact hole 223 formed in the silicon film 222 is connected.
  • a source electrode 225 is connected to the p-type punching layer 214 (p + type semiconductor region 215) and the source (n + type source region 211) via a plug 224, and a plug 224 is connected to the drain (n + type drain region 209).
  • a drain electrode 226 is connected via
  • a wiring 229 is connected to each of the drain electrode 226 and the source electrode 225 via a through hole 228 formed in the silicon oxide film 227 that covers the drain electrode 226 and the source electrode 225.
  • a surface protective film 230 made of a multilayer film of an oxide silicon film and a silicon nitride film is formed.
  • a source back electrode 231 is formed on the back surface of the semiconductor substrate 201.
  • FIG. 8 shows a configuration of the semiconductor chips 15a-15c in the case where the semiconductor amplifying elements constituting the amplifying circuit sections 2A1-2A3, 2B1-2B3 are formed by heterojunction bipolar transistors (HBTs). An example of a fragmentary sectional view is shown.
  • HBTs heterojunction bipolar transistors
  • a subcollector layer 252 made of an n + type GaAs layer is formed on a semi-insulating GaAs substrate (semiconductor substrate) 251, and an HBT 253 is formed on the subcollector layer 252.
  • Each HBT 253 has a collector electrode 254 made of gold or the like formed on the sub-collector layer 252 and a collector mesa 255 formed so as to be separated from the collector electrode 254 by a predetermined distance.
  • the collector mesa 255 is formed of, for example, an n-type GaAs layer, and the collector mesa 255 and the collector electrode 254 are electrically connected via the subcollector layer 252.
  • a base mesa 256 made of, for example, a p-type GaAs layer is formed.
  • a base electrode 257 made of gold or the like is formed in the peripheral area on the base mesa 256! .
  • An emitter layer 258 is formed on a substantially central portion of the base mesa 256, and an emitter electrode 259 is formed on the emitter layer 258.
  • the emitter layer 258 is formed of, for example, an n-type InGaP layer, a GaAs layer, and an InGaAs layer, and the emitter electrode 259 is formed of, for example, a tungsten silicide force.
  • a heterogeneous semiconductor junction heterojunction
  • a collector wiring 263 is connected to the collector electrode 254 via a contact hole 262 formed in the insulating film 261.
  • An emitter wiring 266 is connected to the emitter electrode 259 through through holes 265 formed in the insulating films 264 and 261. The illustration of the structure above the emitter wiring 266 is omitted here.
  • the chip components 16a to 16c shown in FIG. 4 are mounted on the component mounting surface of the module substrate MCB in a state where the electrodes are connected to the electrodes 12E of the component mounting surface of the module substrate MC B.
  • the chip component 16 is formed with passive elements such as capacitors CG1-CG6, CA1-CA3, ferrite beads FB1, inductor LG1, resistors Rl, R3, R5, and the like.
  • the chip component (first passive component) 16a having the smallest size among the chip components 16 is a 0402 type chip component.
  • the power module PM is downsized.
  • a chip component 16a in which resistors Rl, R3, R5, a capacitor CG1, and the like are formed is illustrated.
  • a chip component (second passive component) 16b larger than the chip component 16a is a 0603 type chip component.
  • a chip component 16b in which capacitors CG2-CG6, CA1-CA3, ferrite beads FBI, and the like are formed is illustrated.
  • a chip component (second passive component) 16c larger than the chip component 16b is a 1005 type chip component.
  • a chip component 16c in which an inductor LG1 is formed is illustrated.
  • FIG. 9 is an enlarged plan view of the mounting area of the chip component 16 (16a and 16c) on the mounting surface of the module substrate MCB
  • FIG. 10 shows the chip component 16 (16a-16c) in FIG. Fig. 11 is a cross-sectional view taken along the line X2-X2 in Fig. 10, showing the state where is mounted.
  • Chip parts 16a-16c have different dimensions and electrical specifications, The configuration of the chip component 16 and the configuration of the mounting area of the chip component 16 of the module board MCB are the same.
  • Openings 20 and 20 are formed in the insulating layer 13 on the component mounting surface of the module board MCB, and each of the pair of electrodes 12E and 12E is exposed. ing. The outer peripheral portion of each of the pair of electrodes 12E and 12E is separated from the end portion of the insulating layer 13 (that is, the end portion of the opening 20). Each of the pair of electrodes 16E, 16E of the chip component 16 (16a-16c) is connected to each of the pair of electrodes 12E where the forces of the openings 20, 20 of the module board MCB are also exposed by the adhesive 21. .
  • the adhesive 21 also has, for example, a lead (Pb) -tin (Sn) soldering force.
  • the melting point of Pb—Sn is different depending on the ratio of Pb and Sn. For example, when the ratio of Pb—Sn is 37Z63 (eutectic solder), it is about 183 degrees, for example.
  • the insulating layer 13 is left on the insulating layer 11 between the adjacent electrodes 12E of the module board MCB.
  • the length of the smallest 0402 type chip component 16a among the chip components 16 (the total length in the longitudinal direction of the chip component 16) D1 is, for example, 0.4 ⁇ 0.02 mm
  • the length of the electrode 16E in the longitudinal direction) D2 is, for example, 0.0-07-0.12 mm
  • the length between the electrodes (the length between the adjacent electrodes 16E in the longitudinal direction of the chip part 16) D3 is, for example, 0. 15mm or more
  • width (length in the short direction of chip component 16) D4 is 0.2 ⁇ 0.02mm
  • height D5 is chip capacitor, for example 0.2 ⁇ 0.02mm
  • chip resistance In some cases, for example, 0.12 ⁇ 0.02 mm.
  • each of the pair of electrodes 12E in the mounting region of the chip component 16a is, for example, 0.15 mm
  • the width of each of the pair of electrodes 12E is, for example, 0.25 mm
  • the distance from the outer periphery of the electrode 12E to the end of the opening 20 is, for example, 0.0375 mm, adjacent to the pair of electrodes 12E.
  • the distance D9 is, for example, 0.175 mm or more, for example, 0.205 mm, and the width of the insulating layer 13 left between the pair of electrodes 12E (the length in the direction in which the pair of electrodes 12E are arranged) D10 is, for example, 0 13mm.
  • the length D1 of the 0603-type chip part 16b having an intermediate size is, for example, 0.6 ⁇ 0.03 mm
  • the electrode length D2 is, for example, 0.1-0.2 mm
  • the inter-electrode length D3 is For example, 0.2 mm or more
  • width D4 is, for example, 0.3 ⁇ 0.03 mm
  • height D5 is, for example, a chip capacitor. 3 ⁇ 0.03mm, in case of chip resistor, for example 0.25 ⁇ 0.03mm.
  • the length D6 of each of the pair of electrodes 12E in the mounting region of the chip component 16b is, for example, 0.3 mm
  • the width D7 of each of the pair of electrodes 12E is, for example, 0.35 mm, which is opened from the outer periphery of the electrode 12E.
  • the distance D8 to the end of the portion 20 is 0.05 mm, for example, and the adjacent distance D9 of the pair of electrodes 12E is 0.3 mm, for example, and the width D10 of the insulating layer 13 left between the adjacent of the pair of electrodes 12E is For example, 0.2 mm.
  • the length D1 of the largest 1005 type chip part 16c is, for example, 1.0 ⁇ 0.05 mm
  • the electrode length D2 is, for example, 0.15-0.3 mm
  • the interelectrode length D3 is, for example, 0. 4 mm or more
  • width D 4 is, for example, 0.5 ⁇ 0.05 mm
  • height D5 is for chip capacitors, for example 0.5 ⁇ 0.05 mm, for chip resistors, for example, 0.35 ⁇ 0 05mm.
  • the length D6 of each of the pair of electrodes 12E in the mounting region of the chip part 16c is, for example, 0.4 mm
  • the width D7 of each of the pair of electrodes 12E is, for example, 0.55 mm.
  • the distance D8 to the end of the insulating layer 13 is, for example, 0.6 mm
  • the adjacent distance D9 of the pair of electrodes 12E is, for example, 0.05 mm
  • the width D10 of the insulating layer 13 left between the adjacent of the pair of electrodes 12E is, for example, 0 Te at 05mm.
  • the 0402 type chip component 16 is used to promote downsizing of the power module PM, in the mounting region of the 0402 type chip component 16a, an opening 20 is provided for each pair of electrodes 12E. It is possible to reduce the alignment margin between the opening 20 and the electrode 12E by forming a large opening 20 that covers both of the pair of electrodes 12E without forming a gap. Can be narrowed, which is preferable. In addition, in the case of the 0402 type chip component 16a, the distance between adjacent pairs of electrodes 16E is narrower than that of the 0603 type and 1005 type, so that the opening 20 is formed rather than forming the opening 20 for each pair of electrodes 12E.
  • solder flash chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease.
  • solder flash chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease.
  • solder flash chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease.
  • solder flash chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease.
  • solder flash problem occurs especially when the bump electrode 6 on the back side of the module board MCB is made of lead-free solder with a higher melting point than the adhesive 21 attached to the electrode 16E of the chip component 16a-16c. easy. This means that the solder reflow temperature when mounting on the mother board must be high (about 260 degrees), and when mounting on the mother board, it is necessary to mount the chip components in the power module PM. This is because the solder (Pb—Sn) remelts.
  • the insulation between the pair of electrodes 12E is applied when a desired metal is deposited on the pair of electrodes 12E of the module board MCB by a method such as a staking method.
  • a desired metal is likely to remain on the exposed surface of the layer 11
  • the problem of short circuit failure between the pair of electrodes 16E due to the solder flash and the metal residue described above is likely to occur.
  • the insulating layer 13 is left behind between the adjacent electrodes 12E of the module substrate MCB in the mounting area of the 0402 type chip component 16a.
  • the adjacent distance D9 between the pair of electrodes 12E is, for example, 0.175 mm or more.
  • the width of the insulating layer 13 left between the adjacent electrodes 12E (dimension in the direction in which the pair of electrodes 12E are arranged) D10, for example, 0.1 mm or more is necessary for processing.
  • the upper limit of the dimension D10 is not particularly limited if the length in the longitudinal direction of the chip part 16a (the direction in which the pair of electrodes 12E are arranged) is the upper limit, but it is, for example, about 0.4 mm.
  • the insulating layer 13 having the property of not being wetted by the solder is provided between the adjacent electrodes 12E of the module substrate MCB.
  • the remaining insulating layer 13 acts to stop the flow of the melted solder, thereby suppressing or preventing a short circuit failure between the pair of electrodes 16E of the chip component 16a caused by the solder flash. it can.
  • the insulating layer 13 is left between the pair of electrodes 12E. Therefore, the desired metal does not directly contact the insulating layer 11 and remains on the insulating layer 13.
  • the pair of electrodes of the chip component 16a resulting from the metal residue as described above can be suppressed or prevented.
  • the insulating layer 13 may overlap a part of the outer periphery of the pair of electrodes 12E.
  • the good dimension (overlap amount) is preferably about 0.2 mm, for example.
  • the length D6 of the pair of electrodes 12E in this case (the electrode 12E in this case refers to a region exposed from the insulating layer 13) is, for example, about 0.1 mm.
  • the same reasoning force as described above is obtained, and also in the mounting area of the module substrate MCB of the 0603 type and 1005 type chip components 16b and 16c, the insulating layer 13 is provided between the pair of electrodes 12E. Is left.
  • the chip parts 16b and 16c even in the chip parts 16b and 16c, the chip parts due to the short circuit failure between the pair of electrodes 16E of the chip parts 16b and 16c due to the solder flash and the metal residue due to the same action as the chip part 16a. Short circuit failure between the pair of electrodes 16E of 16b and 16c can be suppressed or prevented.
  • part of the insulating layer 13 may overlap with part of the outer periphery of the pair of electrodes 12E.
  • FIG. 12 shows an example of a cross-sectional view taken along line X2-X2 of FIG. 10 of a chip component (chip capacitor) 16 (16a-16c) having a capacitor.
  • a chip component 16 having a capacitor is formed between a pair of electrodes 16E, a plurality of internal electrodes 16IE electrically connected to and opposed to each other, and a facing surface of the plurality of internal electrodes 16IE. And a dielectric 16D.
  • the pair of electrodes 16E has a configuration in which, for example, a plating layer made of nickel, for example, and a plating layer also made of tin force, for example, are formed on the surface of the base electrode also having silver strength.
  • the internal electrode 16IE is made of, for example, palladium (Pd), copper, or nickel.
  • the dielectric 16D is made of, for example, titanium oxide, calcium zirconate or barium titanate.
  • the rated voltage of the 0402 type chip part 16a is, for example, about 16V
  • the capacitance value range is, for example, 2-6pF
  • the rated voltage of the 0603 type chip part 16b is, for example, 25V
  • capacity For example, the value range is 0.5-100 pF, 1005 type
  • the rated voltage of the chip component 16c is, for example, 50V
  • the capacitance value range is, for example, 0.5-lOOOOpF.
  • FIG. 13 shows a chip component having resistance (chip resistance) 16 (16a-16c) X2 in FIG.
  • the chip component 16 having resistance includes a substrate 16B, a pair of electrodes 16E formed at both ends in the longitudinal direction, an internal electrode 16IE electrically connected to each of the pair of electrodes 16E, and each internal electrode 16IE. And a protective film 16P that protects the resistor 16R and the internal electrode 16IE.
  • the substrate 16B is made of alumina, for example.
  • the configuration of the electrode 16E is almost the same as that described in FIG.
  • the internal electrode 16IE is made of a special metal film.
  • the resistor 16R also has a ruthenium oxide (RuO) material strength.
  • the protective film 16P is made of resin, for example.
  • the rated power of the 0402 type chip part 16a is, for example, about 0.03W
  • the rated power of the 0603 type chip part 16b is, for example, 0.05W
  • 1005 type chip part 16c is, for example, 0.063W.
  • FIG. 14 shows an example of a partially broken cross-sectional view of the chip component 16 (16a-16c) having an inductor, taken along line X2-X2 in FIG.
  • the chip component 16 having an inductor is wound around the outer periphery of the element body 16A, electrically connected to the element body 16A, a pair of electrodes 16E formed at both ends in the longitudinal direction, and the pair of electrodes 16E. And a coil conductor 16L and an outer resin 16D covering the coil conductor 16L.
  • the 0402 type chip component 16a By the way, considering only the miniaturization of the power module PM, it is preferable to use the 0402 type chip component 16a.
  • the use of the 0402 type chip component 16a in the installation location of the chip component 16 in the entire circuit of the power module PM adversely affects the efficiency of the high frequency characteristics. There are places where it is inappropriate to use the 0402 type chip part 16a, and it is not possible to make it all 0402 type. Also, simply using the 0402 type chip part 16a may cause problems. I found it. Therefore, in the first embodiment, the chip parts 16 having different types (dimensions) are used in accordance with the assembling locations of the chip parts 16 of the circuit of the power module PM.
  • FIG. 15 shows an example of a circuit diagram of the high frequency power amplifier circuit of the power module PM.
  • FIG. 16 shows an example of a circuit diagram in which the chip component 16 in the circuit diagram of FIG. Show.
  • the solid line indicates the RF signal wiring
  • the broken line indicates the power supply wiring
  • the two-dot chain line indicates the control signal wiring.
  • the power supply wiring includes a high-potential-side power supply wiring, a low-potential-side power supply wiring (a wiring for supplying a reference potential or a ground potential), and a bias wiring.
  • control signal wiring such as band Z mode switching switch signal wiring.
  • Reference numerals Ta3-Ta7, Tb3-Tb7 denote terminals of the power module PM.
  • the terminal Tal—Ta7 indicates an amplification system terminal for GSM850 and GSM900, and the terminal Tbl—Tb7 indicates an amplification system terminal for DCS1800 and DCS1900.
  • the symbols Pal 1 Pa 7, Pbl—Pb 7, Pel—Pc 3 indicate the pads P of the semiconductor chip 15.
  • FIG. 15 a matte hatching is added to the 0402 type chip part 16a for easy understanding of the drawing.
  • the element symbols of the 0402 type chip part 16a are shown as being surrounded by a square in order to make the drawing easy to see.
  • the 0402 type chip component 16a is mainly used in places where the applied voltage (or flowing current) is smaller than the voltage (or flowing current) applied to the 0603 or 1005 type chip components 16b and 16c. Yes.
  • capacitors CGI, Rl, R3, R5, etc. are formed on the 0402 type chip component 16a is illustrated.
  • Ferrite beads FBI, FB2, capacitors CA1-CA3, CB2, CB3, capacitors CG2-CG5, CP2-CP5, capacitor CG6, etc. are formed on 0603 type chip parts 16b, and inductors LG1, LP1, etc. are 1005 type
  • inductors LG1, LP1, etc. are 1005 type
  • the case where it is formed on the chip part 16c is illustrated.
  • Capacitor CG1 is a capacitor for the matching circuit of the RF input section that performs impedance matching between the weak RF signal input section and the first stage amplifier circuit section 2A1 transistor. It is electrically connected between the RF signal wiring that electrically connects the terminal Tal and the pad Pal that is electrically connected to the input of the first stage amplifier circuit section 2A1, and the ground potential. If this matching is not achieved, the input signal is reflected and the efficiency is lowered.
  • the current that flows in this capacitor CG1 is, for example, 20-30mA, and the applied voltage is For example, ov (which is hardly applied).
  • the resistor R1 is a bias resistor that determines the amount of fluctuation of the RF output, and is electrically connected between the nod Pel and the ground potential.
  • the current flowing through the resistor R1 is, for example, 0.3 mA, and the applied voltage is, for example, 1.55V.
  • Resistor R3 is a bias resistor that determines the point at which RF output begins to be output, and is electrically connected between node Pc2 and the ground potential.
  • the current flowing through the resistor R3 is, for example, 0.27 mA, and the applied voltage is, for example, 1.39V.
  • Resistor R5 is a chip component 16 that forms a detection circuit together with capacitor CG6, and has the function of canceling the reflected wave of the RF signal picked up by capacitor CG6 and picking up only the necessary traveling wave, pad Pc3 And the capacitor CG6 are electrically connected between the wiring and the ground potential.
  • the current flowing through the resistor R5 is, for example, 20-30 mA, and the applied voltage is, for example, OV (almost not applied).
  • the current flowing through the capacitor CG6 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
  • Ferrite beads FBI, FB2, and capacitor CA1 are the first-stage power supply circuit, which plays a role of preventing oscillation as an RF filter, and the power supply (direct current (DC )) Has a role to prevent malfunction.
  • the current flowing through the ferrite beads FBI, FB2 and capacitor CA1 is, for example, 0.11A, and the applied voltage is, for example, 3.5V.
  • Capacitors CA2 and CB2 are the second-stage power supply circuit, and their roles are the same as those of the first-stage power supply circuit.
  • RF filters are formed by the capacitors CA2 and CB2 and the line (wiring 12) on the module board MCB.
  • the current flowing through the capacitor CA2 is, for example, 0.3A, and the applied voltage is, for example, 3.5V.
  • Capacitors CA3 and CB3 and inductors LG1 and LP1 are the third-stage power supply circuit, and function as an RF filter to prevent oscillation.
  • the current flowing through the capacitors CA3 and CB3 and the inductors LG1 and LP1 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
  • Capacitors CG2—CG5, CP2—CP5 are capacitors for matching circuits in the RF output section that perform impedance matching between the output section and the transistors in the third-stage amplifier circuit sections 2A3, 2B3. Since the RF signal output is large and the impedance difference is large, many parts are used.
  • the current flowing through the capacitors CG2-CG5, CP2-CP5 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
  • FIG. 17 is an enlarged plan view of the mounting area of the module substrate MCB of the power module PM according to the second embodiment and is mounted on the chip component 16 (16a)
  • FIG. 18 is a chip on the module substrate MCB of FIG. Fig. 19 is a cross-sectional view taken along line X3-X3 in Fig. 18, and
  • Fig. 20 is an enlarged view of the main part of the module board MCB between the pair of electrodes 12E in Fig. 19. Each cross-sectional view is shown.
  • the insulating layer 13 since the insulating layer 13 must be left between the pair of electrodes 12E, reduction of the distance between the pair of electrodes 12E is hindered. This is particularly a problem when chip components 16 smaller than 0402 type are mounted. Therefore, in the second embodiment, the insulating layer 13 is not left between the pair of electrodes 12E in the mounting region of the 0402 type chip component 16a or the smaller chip component 16 and the pair of electrodes 12E A large opening 20 was formed so as to include the space between the pair of electrodes 12E. In this case, since it is not necessary to leave the insulating layer 13 between the pair of electrodes 12E, it is possible to narrow the space between the pair of electrodes 12E.
  • the opening portion of the mounting area of the 0402 type chip component 16a or the chip component 16 smaller than that, and the insulating layer 11 between the pair of electrodes 12E where the force is exposed are viewed in a plane.
  • a plurality of grooves 25 extending in a direction perpendicular to the direction in which the pair of electrodes 12E are arranged and recessed in the thickness direction of the module substrate MC when viewed in cross section.
  • the distance between the pair of electrodes 12E can be increased compared to the case where the groove 25 is not provided, so that the short-circuit failure between the pair of electrodes 12E and 16E due to the solder flash or the metal residue is suppressed or prevented. it can.
  • FIG. 21 is a mounting surface of the module substrate MCB of the power module PM according to the third embodiment, and is an enlarged plan view of the mounting region of the chip component 16 (16a), and FIG. 22 is a chip on the module substrate MCB of FIG. Fig. 2 is an enlarged plan view showing the part 16 (16a) mounted 3 is a cross-sectional view taken along the line X4-X4 in FIG. 22, and FIG. 24 is an enlarged cross-sectional view of the main part of the module board MCB between the pair of electrodes 12E in FIG.
  • the groove formed in the insulating layer 11 between the pair of electrodes 12E exposed from the opening 20 in the mounting region of the 0402 type chip component 16a or the smaller chip component 16 is provided.
  • the insulating layer 13 is embedded at 25 mm.
  • the insulating layer 13 having the property of not being wetted by the solder is left between the pair of electrodes 12E, a short circuit failure between the pair of electrodes 12E and 16E due to the solder flash can be suppressed or prevented.
  • the desired metal is deposited on the surface of the pair of electrodes 12E by a method such as the above, the insulating layer 13 is embedded in the groove 25 between the pair of electrodes 12E. It is possible to prevent direct contact with the insulating layer 11 where the groove 25 is formed. As a result, as described in the first embodiment, it is possible to suppress or prevent a short circuit failure between the pair of electrodes 12E due to the metal residue.
  • FIG. 25 is a mounting surface of the module substrate MCB of the power module PM according to the fourth embodiment, and is an enlarged plan view of the mounting region of the chip component 16 (16a).
  • FIG. 26 is a chip on the module substrate MCB of FIG.
  • FIG. 27 is a cross-sectional view taken along line X5-X5 in FIG. 26, and
  • FIG. 28 is a cross-sectional view taken along line X6-X6 in FIG. 26, respectively, showing a state where the component 16 (16a) is mounted. Note that in FIG. 26, the chip component 16 is shown in a transparent manner for easy viewing of the drawing.
  • the pair of electrodes 12E of the module board MCB is electrically connected to the pair of electrodes 16E of the chip component 16 through the portions exposed from the openings 20a and 20b.
  • the opening 20a that exposes one electrode 12E is, for example, a flat concave shape, and the exposed shape of the electrode 12E exposed from the opening 20a is also a flat concave shape.
  • the opening 20b that exposes the other electrode 12E is, for example, a planar convex shape, and the exposed shape of the electrode 12E exposed from the opening 20b is also a planar convex shape.
  • the pair of electrodes 12E! A part of is covered.
  • the width D20 of the insulating layer 13 can be made larger than the adjacent interval D9. That is, even when the adjacent distance D9 between the pair of electrodes 12E is the same as or smaller than that of the first embodiment, the insulating layer 13 can be easily formed between the pair of electrodes 12E. Therefore, even when the 0402 type or smaller chip component 16 is mounted, a pair of chip components 16 caused by the solder flash and the metal residue is used for the same reason as described in the first embodiment. Short circuit failure between the electrodes 16E can be suppressed or prevented.
  • FIG. 29 is a mounting surface of the module substrate MCB of the power module PM according to the fifth embodiment, and is an enlarged plan view of the mounting area of the chip component 16 (16a).
  • FIG. 30 is a chip on the module substrate MCB of FIG.
  • FIG. 31 is a cross-sectional view taken along line X7—X7 in FIG. 30, and
  • FIG. 32 is a cross-sectional view taken along line X8—X8 in FIG. Note that in FIG. 30, the chip component 16 is shown in a transparent manner for easy viewing of the drawing.
  • the adjacent distance D21 between the pair of electrodes 12E in the mounting area of the chip component 16 smaller than the 0402 type chip component 16a is equal to the longitudinal length D22 of the chip component 16. .
  • the insulating layer 13 is left between the pair of electrodes 12E in a state in which the width D10 described in the first embodiment 1 is secured.
  • a convex portion 12E1 extending toward the adjacent center of the pair of electrodes 12E is formed in the center of each of the opposing sides of the pair of electrodes 12E.
  • the convex portion 12E1 has a function for promoting the adhesion of solder to the electrode 16E of the chip component 16 when the chip component 16 is mounted.
  • the insulating layer 13 can be left between the pair of electrodes 12E without impairing the electrical connectivity between the chip component 16 smaller than the 0402 type and the pair of electrodes 12E. Therefore, even when the chip component 16 smaller than the 0402 type is mounted, for the same reason as described in the first embodiment, between the pair of electrodes 16E of the chip component 16 due to the solder flash and the metal residue. Can prevent or prevent short circuit defects. [0077] (Embodiment 6)
  • a multilayer ceramic substrate is prepared. On this multilayer ceramic substrate, a plurality of module substrate MCB formation regions are arranged.
  • the surface electrode 12E and the insulating layer 13 of the multilayer ceramic substrate are formed as follows.
  • FIG. 34 is an enlarged cross-sectional view of the main part of the multilayer ceramic substrate MCBm during the manufacturing process.
  • a printing mask 30 for forming the insulating layer 13 is prepared.
  • FIG. 35 is a cross-sectional view of the main part of the printing mask 30.
  • the printing mask 30 has, for example, a metal thin plate force, and an opening 30a penetrating the main back surface is formed at a desired location. Subsequently, as shown in FIG.
  • FIG. 36 is a cross-sectional view of the main part in a state where the multilayer ceramic substrate MCBm and the printing mask 30 are overlaid.
  • FIG. 37 is a cross-sectional view of the principal parts of the multilayer ceramic substrate MCBm and the printing mask 30 during the printing process.
  • FIG. 38 is a cross-sectional view of a principal part of the multilayer ceramic substrate MCBm. 39 and 40 show an example of an enlarged sectional view of the insulating layer 13 portion between the pair of electrodes 12E.
  • the side surface of the insulating layer 13 is substantially perpendicular to the main surface of the multilayer ceramic substrate MCBm.
  • the side surface of the insulating layer 13 may be inclined with respect to the main surface of the multilayer ceramic substrate MCB. That is, a taper may be formed on the side surface of the insulating layer 13.
  • the width D10 is a relatively wide width on the lower bottom side, which is 0.1 mm or more as described in the first embodiment.
  • a solder paste material having a Pb—Sn (PbZSn ratio of 37Z63 (eutectic solder)) force is applied to the main surface of the multilayer ceramic substrate MCBm in the same manner as described above.
  • Printing is performed by using a printing mask.
  • the semiconductor chip 15 and the chip After mounting the chip component 16 (16a-16c) as shown in FIG. 41, a pair of electrodes of the chip component 16 is applied by performing a heating (one riff mouth) process as shown in step S4 of FIG. 16E and the pair of electrodes 12E on the main surface of the multilayer ceramic substrate MCBm are connected via the solder paste (adhesive 21).
  • the heating temperature (reflow temperature) at this time is set to a temperature at which the solder paste is melted.
  • the ratio of PbZSn is 37Z63 (eutectic solder), for example, it is about 183 degrees.
  • step S7 of FIG. 33 for example, a silicone resin or a low-elastic epoxy resin so as to collectively cover the formation areas of the plurality of module substrates MCB on the main surface of the multilayer ceramic substrate MCBm.
  • the sealing member 8 having equal force is formed by the same printing method as described above.
  • step S8 of FIG. 33 the sealing member 8 is cured by performing a beta (heating) process.
  • step S9 of FIG. 33 the multilayer ceramic substrate MCCBm is cut into individual modules PM, and a plurality of modules PM are cut out (individualization step).
  • step S8 and step S9 or between step S10 and step S11 bumps made of the lead-free solder solder are applied to each of the plurality of electrodes (external connection electrodes) on the back surface of the module board MCB.
  • Connect electrode 6 When bump electrode 6 is connected between steps S8 and S9 before cutting multilayer ceramic substrate MCBm, bump electrode 6 can be connected to multiple module substrates on multilayer ceramic substrate MCBm. Process simplification and manufacturing time can be shortened.
  • the bump electrode 6 may be a gold (Au) bump instead of the lead-free solder bump. Furthermore, here, the force described for connecting the bump electrode 6 may be shipped without connecting the bump electrode 6 (product of LGA package configuration).
  • the lead-free solder paste is applied to the electrodes on the main surface of the mother board MB as shown in step S22. Is printed by a method using a print mask similar to the above.
  • the steps in Figure 33 As shown in step S23, the power module PM is mounted on the main surface of the mother board MB. That is, as shown in FIG. 42, the bump electrode 6 of the power module PM and the electrode 35 on the main surface of the mother board MB are aligned.
  • FIG. 42 is a cross-sectional view of the main part of the mother board MB during the power module mounting process.
  • FIG. 43 is a cross-sectional view of the main part of the mother board MB after the mounting process of the power module PM.
  • the heating temperature (reflow temperature) at this time is set to a temperature at which the solder paste made of lead-free solder is melted.
  • the solder reflow temperature when mounting on this motherboard MB is the above step S4.
  • the temperature must be higher than the temperature at (eg about 260 degrees).
  • the solder (Pb—Sn) for mounting the chip components in the power module PM is remelted, and the pair of electrodes 16E (or the pair of electrodes 12E) are short-circuited. In some cases (solder flash).
  • the insulating layer 13 is left between the pair of electrodes 12E, and this acts as a barrier against the molten solder.
  • the short circuit failure between the pair of electrodes 16E of the chip component 16 to be performed can be suppressed or prevented.
  • the lead-free solder or gold forming the bump electrode 6 and the solder paste 36 are mixed in the bump electrode 6 in the stage of FIG. As described above, do not connect the bump electrode 6 to the electrode (external connection electrode) on the back of the power module PM! ⁇
  • the electrode on the back of the power module PM and the motherboard MB The electrode 35 is connected to the solder paste 36. After that, as shown in steps S25 and S26 in FIG. 33, an electrical characteristic test is performed to complete the secondary mounting.
  • GSM850, GSM900, GSM1800, and GSM19 The power described when applied to a four-band mobile phone capable of handling radio waves in the four frequency bands of 00.
  • a four-band mobile phone capable of handling radio waves in the four frequency bands of 00.
  • This is not limited to this example.
  • it handles radio waves in the two frequency bands of GSM90 0 and GSM1800.
  • It can also be applied to dual-band mobile phones that can handle radio waves in the three frequency bands of GSM900, GSM1800, and GSM1900.
  • the present invention is not limited to this.
  • the present invention can also be applied to mobile information processing devices such as PDAs (Personal Digital Assistants) having a communication function, and information processing devices such as personal computers having a communication function.
  • PDAs Personal Digital Assistants
  • the electronic device of the present invention is, for example, a mobile electronic device such as a mobile phone, a mobile information processing device such as a PDA having a communication function, a personal computer having a communication function, or the like. It can be used for information processing devices.

Abstract

Since a part which is unfit for using a 0402 type chip component and causes adverse effects on the efficiency of high frequency characteristics, for example, exists among chip component incorporating parts in the entire circuit of an RF power module when the 0402 type chip component is used, a chip component of different dimensions is used depending on the incorporating part of the chip component in the entire circuit of the RF power module. In the RF power module circuit, the 0402 type chip component of small dimensions is connected electrically to a part being applied with a voltage lower than that applied to a 1005 type or 0603 type chip component of large dimensions.

Description

明 細 書  Specification
電子装置及び電子装置の製造方法 技術分野  Technical field of electronic device and method of manufacturing electronic device
[0001] 本発明は、電子装置技術に関し、特に、 RF (Radio Frequency)パワーモジュール に適用して有効な技術に関するものである。  [0001] The present invention relates to an electronic device technology, and more particularly to a technology effective when applied to an RF (Radio Frequency) power module.
背景技術  Background art
[0002] 本発明者が検討した RFパワーモジュールは、例えば携帯電話機等のような携帯型 通信機器の信号増幅用の電子部品であり、信号増幅用のトランジスタを有する複数 の半導体チップと、その他に受動素子を有する複数のチップ部品とをモジュール基 板上に実装し、これらを互いに電気的に接続することで形成されている。チップ部品 はその電極がモジュール基板の実装面上の絶縁層に形成された開口部から露出さ れた一対の電極と半田等を介して接続された状態でモジュール基板に実装されてい る。  [0002] The RF power module examined by the present inventors is an electronic component for signal amplification of a portable communication device such as a mobile phone, for example, and includes a plurality of semiconductor chips having a transistor for signal amplification, and A plurality of chip components having passive elements are mounted on a module substrate, and these are electrically connected to each other. The chip component is mounted on the module substrate with its electrodes connected via a solder or the like to a pair of electrodes exposed from the opening formed in the insulating layer on the mounting surface of the module substrate.
[0003] なお、チップ部品については、例えば特開平 5— 326632号公報に記載があり、チ ップ部品の一対の電極は、基板の実装面上に形成された絶縁層に開口された開口 部から露出される一対の電極と接続されており、その基板の一対の電極の隣接間の 絶縁層も除去され、基板面が露出されている構成が開示されている (特許文献 1参照 [0003] Note that the chip component is described in, for example, Japanese Patent Laid-Open No. 5-326632, and the pair of electrodes of the chip component is an opening formed in an insulating layer formed on the mounting surface of the substrate. A configuration is disclosed in which an insulating layer between adjacent electrodes of the substrate is also removed and the substrate surface is exposed (see Patent Document 1).
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特許文献 1：特開平 5 - 326632号公報  Patent Document 1: JP-A-5-326632
発明の開示  Disclosure of the invention
発明が解決しょうとする課題  Problems to be solved by the invention
[0004] ところで、近年は、携帯型通信機器の小型 ·高機能化要求に伴い、携帯型通信機 器用の RFパワーモジュールの小型'高機能ィ匕も急速に進められている。特に GSM ( Global System for Mobile Communication)方式を使用する RFパワーモジュールでは 、現状、例えば 10 X 8mmサイズのもの力 次世代では、例えば 6 X 5mmサイズが主 流となる。また、 CDMA (Code Division Multiple Access)方式を使用する RFパワー モジュールでも、例えば 6 X 6mmから 5 X 5mmに、さらには 4 X 4mmへとサイズの縮 小が要求されてきている。このような RFパワーモジュールの小型化の要求に伴い、こ れを構成する上記チップ部品として現在主流の 1005型や 0603型のチップ部品から それらよりもさらにサイズの小さい 0402型のチップ部品を使用することによって、更な る高密度実装を実現させることが検討されて 、る。 [0004] By the way, in recent years, along with demands for miniaturization and high functionality of portable communication devices, small-size and high-functionality of RF power modules for portable communication devices have been rapidly advanced. Especially for RF power modules that use the GSM (Global System for Mobile Communication) method, the current power, for example, 10 X 8 mm size, for the next generation, for example, 6 X 5 mm size will become the mainstream. Also, RF power modules that use the Code Division Multiple Access (CDMA) method can be reduced in size, for example, from 6 X 6 mm to 5 X 5 mm, and further to 4 X 4 mm. Small has been demanded. In response to the demand for miniaturization of such RF power modules, the chip components of the 0402 type, which are smaller than those of the current mainstream 1005 type and 0603 type chip components, are used as the chip components constituting the RF power module. Therefore, it is considered to realize higher density mounting.
[0005] しかし、本発明者の検討によれば、 RFパワーモジュールの全体回路内のチップ部 品の組み込み箇所の中には、 0402型のチップ部品を用いると高周波特性の効率に 悪影響を及ぼす等、 0402型のチップ部品を使用することが不適格な箇所があり、 04 02型のチップ部品をただ単純に用いると問題が生じることを見出した。また、 0402 型のチップ部品の場合はチップ部品の電極間が狭 、ので、チップ部品の電極が接 続されるモジュール基板上の一対の電極間も狭い。このため、モジュール基板上の 絶縁層に形成される開口部は、隣接する一対の電極の各々を露出させるように形成 されずに、隣接する一対の電極とその間のモジュール基板表面とが露出されるように 繋がって形成されるような構成とされる。しかし、モジュール基板上の一対の電極間 が露出されていると、半田フラッシュ（チップ部品の電極に付けた半田が RFパワーモ ジュールの実装時に溶け膨張し封止榭脂を割って出てくる現象）によりチップ部品の 電極間を短絡させる問題が生じ易い。この半田フラッシュの問題は、モジュール基板 の裏面の半田バンプが鉛フリー半田で形成されており、その半田バンプの融点がチ ップ部品の電極に付けた半田の融点よりも高い場合に特に生じ易い。また、モジユー ル基板側の一対の電極に所望の金属をめつき法等により被着する際に一対の電極 間のモジュール基板の露出面に上記所望の金属が残り易くなる結果、その金属残り によりチップ部品の一対の電極間を短絡させる問題がある。 [0005] However, according to the study of the present inventor, the use of the 0402 type chip component in the chip component installation location in the entire circuit of the RF power module adversely affects the efficiency of the high frequency characteristics. There are places where it is not appropriate to use 0402 type chip parts, and it has been found that simply using 04 02 type chip parts causes problems. Further, in the case of the 0402 type chip component, the distance between the electrodes of the chip component is narrow, so the distance between the pair of electrodes on the module substrate to which the electrode of the chip component is connected is also narrow. Therefore, the opening formed in the insulating layer on the module substrate is not formed so as to expose each of the pair of adjacent electrodes, but the pair of adjacent electrodes and the module substrate surface therebetween are exposed. The structure is such that they are connected together. However, if the gap between the pair of electrodes on the module substrate is exposed, solder flash (a phenomenon in which the solder attached to the electrode of the chip component melts and expands when the RF power module is mounted and breaks the sealing resin) As a result, the problem of short-circuiting the electrodes of the chip component is likely to occur. This solder flash problem is particularly likely to occur when the solder bumps on the back side of the module board are made of lead-free solder and the melting point of the solder bumps is higher than the melting point of the solder attached to the chip component electrode. . In addition, when a desired metal is deposited on a pair of electrodes on the module substrate side by a contact method or the like, the desired metal tends to remain on the exposed surface of the module substrate between the pair of electrodes. There is a problem of short-circuiting between a pair of electrodes of a chip component.
[0006] 本発明の目的は、電子装置を小型にすることのできる技術を提供することにある。 An object of the present invention is to provide a technique capable of reducing the size of an electronic device.
[0007] また、本発明の目的は、電子装置を構成する電子部品の一対の電極間の短絡不 良を抑制または防止することのできる技術を提供することにある。 [0007] Another object of the present invention is to provide a technique capable of suppressing or preventing a short circuit failure between a pair of electrodes of an electronic component constituting an electronic device.
[0008] 本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添 付図面から明らかになるであろう。 [0008] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
課題を解決するための手段  Means for solving the problem
[0009] 本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、 次のとおりである。 [0009] To briefly explain the summary of typical inventions among inventions disclosed in the present application, It is as follows.
[0010] すなわち、本発明は、高周波電力増幅回路における電子部品の組み込み箇所に 応じて寸法の異なる電子部品を使用するものである。  [0010] That is, the present invention uses electronic components having different dimensions depending on the place where the electronic component is incorporated in the high-frequency power amplifier circuit.
[0011] また、本発明は、高周波電力増幅回路における電子部品の一対の電極間における 配線基板上に絶縁層が残るようにするものである。  [0011] Further, the present invention is such that an insulating layer remains on the wiring board between the pair of electrodes of the electronic component in the high-frequency power amplifier circuit.
発明の効果  The invention's effect
[0012] 本願において開示される発明のうち、代表的なものによって得られる効果を簡単に 説明すれば以下のとおりである。  [0012] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0013] すなわち、高周波電力増幅回路の組み込み箇所に応じて寸法の異なる電子部品 を使用することにより、電子装置の小型化を実現することができる。  [0013] That is, the use of electronic components having different dimensions according to the installation location of the high-frequency power amplifier circuit enables the electronic device to be reduced in size.
[0014] また、高周波電力増幅回路における電子部品の一対の電極間における配線基板 上に絶縁層力 S残るようにすることにより、半田フラッシュや一対の電極間に金属残りが 生じるのを抑制または防止できるので、電子装置の電子部品の一対の電極間の短絡 不良を抑制または防止することができる。  [0014] Further, by causing the insulating layer force S to remain on the wiring board between the pair of electrodes of the electronic component in the high frequency power amplifier circuit, it is possible to suppress or prevent the occurrence of a metal residue between the solder flash and the pair of electrodes Therefore, it is possible to suppress or prevent a short circuit failure between the pair of electrodes of the electronic component of the electronic device.
図面の簡単な説明  Brief Description of Drawings
[0015] [図 1]本発明の一実施の形態である電子装置を有する携帯電話システムの一例の説 明図である。  FIG. 1 is an explanatory diagram of an example of a mobile phone system having an electronic device according to an embodiment of the present invention.
[図 2]図 1の携帯電話システム中の電子装置の一例の回路ブロック図である。  2 is a circuit block diagram of an example of an electronic device in the mobile phone system of FIG.
[図 3]図 1の携帯電話システムでの電子装置の実装例の説明図である。  3 is an explanatory diagram of an example of mounting an electronic device in the mobile phone system of FIG. 1.
[図 4]電子装置の配線基板の主面の一例の平面図である。  FIG. 4 is a plan view of an example of a main surface of a wiring board of an electronic device.
[図 5]図 4の配線基板の裏面の一例の平面図である。  FIG. 5 is a plan view of an example of the back surface of the wiring board of FIG.
[図 6]図 4の XI— XI線の断面図である。  6 is a cross-sectional view taken along line XI—XI in FIG.
[図 7]電子装置の増幅回路部を構成する半導体増幅素子を LDMOSFETにより形 成した場合の半導体チップの一例の要部断面図である。  FIG. 7 is a cross-sectional view of an essential part of an example of a semiconductor chip when a semiconductor amplifying element constituting an amplifier circuit part of an electronic device is formed by an LDMOSFET.
[図 8]電子装置の増幅回路部を構成する半導体増幅素子をへテロ接合型バイポーラ トランジスタにより形成した場合の半導体チップの一例の要部断面図である。  FIG. 8 is a fragmentary cross-sectional view of an example of a semiconductor chip when a semiconductor amplifying element constituting an amplifier circuit portion of an electronic device is formed of a heterojunction bipolar transistor.
[図 9]図 4の配線基板の被部品実装面であってチップ部品の実装領域の拡大平面図 である。 圆 10]図 9にチップ部品を実装した状態を示す配線基板の拡大平面図である。 FIG. 9 is an enlarged plan view of a component mounting surface of the wiring board of FIG. 4 and a chip component mounting region. [10] FIG. 9 is an enlarged plan view of the wiring board showing a state where the chip components are mounted in FIG.
[図 11]図 10の X2— X2線の断面図である。 FIG. 11 is a sectional view taken along line X 2 -X 2 in FIG.
[図 12]コンデンサを有するチップ部品の図 10の X2— X2線の一例の断面図である。  FIG. 12 is a cross-sectional view of an example of the X2-X2 line in FIG. 10 of the chip part having a capacitor.
[図 13]抵抗を有するチップ部品の図 10の X2— X2線の一例の断面図である。 FIG. 13 is a cross-sectional view of an example of the X2-—X2 line in FIG. 10 of the chip component having a resistor.
[図 14]インダクタを有するチップ部品の図 10の X2— X2線の一例の部分破断断面図 である。 FIG. 14 is a partially broken cross-sectional view of an example of the X2-X2 line in FIG. 10 of the chip component having an inductor.
[図 15]電子装置の高周波電力増幅回路の一例の回路図である。  FIG. 15 is a circuit diagram of an example of a high frequency power amplifier circuit of an electronic device.
[図 16]図 15の回路図中のチップ部品を素子レベルの図記号で示した一例の回路図 である。  FIG. 16 is a circuit diagram of an example in which chip components in the circuit diagram of FIG. 15 are indicated by element-level graphic symbols.
圆 17]本発明の他の実施の形態である電子装置の配線基板の被部品実装面であつ てチップ部品の実装領域の拡大平面図である。 FIG. 17 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is another embodiment of the present invention, and a mounting region of a chip component.
圆 18]図 17の配線基板にチップ部品を実装した状態を示す拡大平面図である。 18] FIG. 18 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
[図 19]図 18の X3— X3線の断面図である。 FIG. 19 is a cross-sectional view taken along line X3-X3 in FIG.
[図 20]図 19の一対の電極間の配線基板の要部拡大断面図である。  20 is an enlarged cross-sectional view of a main part of a wiring board between a pair of electrodes in FIG.
圆 21]本発明の他の実施の形態である電子装置の配線基板の被部品実装面であつ てチップ部品の実装領域の拡大平面図である。 FIG. 21 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is another embodiment of the present invention, and a mounting region of a chip component.
圆 22]図 21の配線基板にチップ部品を実装した状態を示す拡大平面図である。 22] FIG. 22 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
[図 23]図 22の X4— X4線の断面図である。 FIG. 23 is a cross-sectional view taken along line X4-X4 in FIG.
[図 24]図 23の一対の電極間の配線基板の要部拡大断面図である。  24 is an enlarged cross-sectional view of a main part of the wiring board between a pair of electrodes in FIG. 23.
圆 25]本発明のさらに他の実施の形態である電子装置の配線基板の被部品実装面 であってチップ部品の実装領域の拡大平面図である。 25] FIG. 25 is an enlarged plan view of a component mounting surface of a wiring board of an electronic device which is still another embodiment of the present invention, and a chip component mounting region.
圆 26]図 25の配線基板にチップ部品を実装した状態を示す拡大平面図である。 26] FIG. 26 is an enlarged plan view showing a state in which chip components are mounted on the wiring board of FIG.
[図 27]図 26の X5— X5線の断面図である。 FIG. 27 is a sectional view taken along line X5-X5 in FIG.
[図 28]図 26の X6— X6線の断面図である。 FIG. 28 is a cross-sectional view taken along line X6—X6 of FIG.
圆 29]本発明の他の実施の形態である電子装置の配線基板の被部品実装面であつ てチップ部品の実装領域の拡大平面図である。 29] An enlarged plan view of a component mounting surface of a wiring board of an electronic device according to another embodiment of the present invention, which is a mounting region of a chip component.
圆 30]図 29の配線基板にチップ部品を実装した状態を示す拡大平面図である。 30] FIG. 30 is an enlarged plan view showing a state where chip components are mounted on the wiring board of FIG.
[図 31]図 30の X7— X7線の断面図である。 [図 32]図 30の X8— X8線の断面図である。 FIG. 31 is a cross-sectional view taken along line X7—X7 of FIG. FIG. 32 is a cross-sectional view taken along line X8—X8 of FIG.
[図 33]本発明の一実施の形態である電子装置の製造工程のフロー図である。  FIG. 33 is a flowchart of a manufacturing process of the electronic device according to the embodiment of the invention.
[図 34]本発明の一実施の形態である電子装置の製造工程中の多層セラミック基板の 要部拡大断面図である。  FIG. 34 is an essential part enlarged cross-sectional view of the multilayer ceramic substrate during the manufacturing process of the electronic device according to one embodiment of the present invention.
[図 35]本発明の一実施の形態である電子装置の製造工程で使用する印刷マスクの 要部断面図である。  FIG. 35 is a fragmentary cross-sectional view of a printing mask used in the manufacturing process of the electronic device according to one embodiment of the present invention.
[図 36]図 34の多層セラミック基板と図 35の印刷マスクとを重ね合わせた状態の要部 断面図である。  FIG. 36 is a cross-sectional view of a principal part in a state where the multilayer ceramic substrate of FIG. 34 and the printing mask of FIG. 35 are overlaid.
[図 37]印刷工程時の多層セラミック基板と印刷マスクとの要部断面図である。  FIG. 37 is a cross-sectional view of main parts of a multilayer ceramic substrate and a printing mask during a printing process.
[図 38]多層セラミック基板の要部断面図である。  FIG. 38 is a cross-sectional view of a principal part of a multilayer ceramic substrate.
[図 39]多層セラミック基板の主面の一対の電極間の絶縁層部分の一例の拡大断面 図である。  FIG. 39 is an enlarged cross-sectional view of an example of an insulating layer portion between a pair of electrodes on the main surface of a multilayer ceramic substrate.
[図 40]多層セラミック基板の主面の一対の電極間の絶縁層部分の他の例の拡大断 面図である。  FIG. 40 is an enlarged sectional view of another example of the insulating layer portion between a pair of electrodes on the main surface of the multilayer ceramic substrate.
[図 41]チップ部品の実装工程後の多層セラミック基板の要部断面図である。  FIG. 41 is a fragmentary cross-sectional view of the multilayer ceramic substrate after a chip component mounting step.
[図 42]電子装置の実装工程時のマザ一ボードの要部断面図である。  FIG. 42 is a fragmentary cross-sectional view of the mother board during the mounting process of the electronic device.
[図 43]電子装置の実装工程後のマザ一ボードの要部断面図である。  FIG. 43 is a fragmentary cross-sectional view of the mother board after the mounting process of the electronic device.
発明を実施するための最良の形態  BEST MODE FOR CARRYING OUT THE INVENTION
[0016] 本願発明の実施の形態を詳細に説明する前に、本実施の形態における用語の意 味を説明すると次の通りである。  [0016] Before describing embodiments of the present invention in detail, the meaning of terms in the present embodiment will be described as follows.
[0017] 1. GSM (Global System for Mobile Communication)は、デジタル携帯電話に使用 されている無線通信方式の 1つまたは規格をいう。 GSMには、使用する電波の周波 数帯が 3つあり、 900MHz帯を GSM900または単に GSM、 1800MHz帯を GSM1 800または DCS (Digital Cellular System) 1800若しくは PCN、 1900MHz帯を GS Ml 900または DCS 1900若しくは PCS (Personal Communication Services)という。 なお、 GSM1900は主に北米で使用されている。北米ではその他に 850MHz帯の GSM850を使用する場合もある。  [0017] 1. GSM (Global System for Mobile Communication) is one of the wireless communication systems or standards used in digital mobile phones. GSM has three frequency bands of radio waves to be used: 900 MHz band is GSM900 or simply GSM, 1800 MHz band is GSM1 800 or DCS (Digital Cellular System) 1800 or PCN, 1900 MHz band is GS Ml 900 or DCS 1900 or PCS (Personal Communication Services). GSM1900 is mainly used in North America. In North America, the GSM850 in the 850MHz band may also be used.
[0018] 2. GMSK変調方式は、音声信号の通信に用いる方式で搬送波の位相を送信デ ータに応じて位相シフトする方式である。 [0018] 2. The GMSK modulation method is a method used for communication of an audio signal. In this method, the phase is shifted according to the data.
[0019] 3. EDGE変調方式は、データ通信に用いる方式で GMSK変調の位相シフトにさ らに振幅シフトをカ卩えた方式である。  [0019] 3. The EDGE modulation method is a method used for data communication, in which an amplitude shift is added to the phase shift of GMSK modulation.
[0020] 以下の実施の形態においては便宜上その必要があるときは、複数のセクションまた は実施の形態に分割して説明するが、特に明示した場合を除き、それらはお互いに 無関係なものではなぐ一方は他方の一部または全部の変形例、詳細、補足説明等 の関係にある。また、以下の実施の形態において、要素の数等 (個数、数値、量、範 囲等を含む）に言及する場合、特に明示した場合および原理的に明らかに特定の数 に限定される場合等を除き、その特定の数に限定されるものではなぐ特定の数以上 でも以下でも良い。さらに、以下の実施の形態において、その構成要素（要素ステツ プ等も含む）は、特に明示した場合および原理的に明らかに必須であると考えられる 場合等を除き、必ずしも必須のものではないことは言うまでもない。同様に、以下の実 施の形態において、構成要素等の形状、位置関係等に言及するときは、特に明示し た場合および原理的に明らかにそうでないと考えられる場合等を除き、実質的にその 形状等に近似または類似するもの等を含むものとする。このことは、上記数値および 範囲についても同様である。また、本実施の形態を説明するための全図において同 一機能を有するものは同一の符号を付すようにし、その繰り返しの説明は可能な限り 省略するようにしている。以下、本発明の実施の形態を図面に基づいて詳細に説明 する。  [0020] In the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant unless otherwise specified. One is related to some or all of the other modification, details, supplementary explanation, etc. Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when explicitly stated, and when clearly limited to a specific number in principle, etc. Except for, the number is not limited to the specific number, and may be a specific number or more. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and clearly considered essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., unless otherwise specified or in principle, it is considered that this is not clearly the case. Including those that are approximate or similar to the shape. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0021] (実施の形態 1)  [0021] (Embodiment 1)
図 1は、例えば GSM方式のネットワークを利用して情報を伝送するデジタル携帯電 話システム DPSの一例を示している。このデジタル携帯電話システム DPSは、マザ 一ボード MB上に搭載されたモジュール、回路および素子等によって構築されている 。符号 PMは本実施の形態 1の電子装置である RF (Radio Frequency)パワーモジュ ール (以下、単にパワーモジュールという）、符号 ANTは信号電波の送受信用のアン テナ、符号 FEMはフロントエンド 'モジュール、符号 BBCは音声信号をベースバンド 信号に変換したり、受信信号を音声信号に変換したり、変調方式切換信号やバンド 切換信号を生成したりする前記ベースバンド回路、符号 FMCは受信信号をダウンコ ンバートして復調しベースバンド信号を生成したり送信信号を変調したりする変復調 用回路、 FLT1, FLT2は受信信号力もノイズや妨害波を除去するフィルタである。フ ィルタ FLT1は GSM用、フィルタ FLT2は DCS用である。ベースバンド回路 BBCは、 DSP (Digital Signal Processor)やマイクロプロセッサ、半導体メモリ等の複数の半導 体集積回路で構成されている。フロントエンド 'モジュール FEMは、ロウパスフィルタ LPFl, LPF2、スィッチ回路 SWl, SW2、コンデンサ CI, C2および分波器 WDCを 有している。ロウパスフィルタ LPFl, LPF2は高調波を減衰させる回路、スィッチ回 路 SWl, SW2は送受信信号切り換え用のスィッチ回路、コンデンサ CI, C2は受信 信号から直流成分をカットする素子、分波器 WDCは、 GSM900帯の信号と、 DCS1 800帯の信号とを分波する回路であり、これら回路および素子は 1つの配線基板上 に搭載されてモジュールとされている。なお、スィッチ回路 SWl, SW2の切換信号 C NT1, CNT2は上記ベースバンド回路 BBCから供給される。 Fig. 1 shows an example of DPS, a digital mobile phone system that transmits information using a GSM network, for example. This digital cellular phone system DPS is constructed by modules, circuits and elements mounted on the motherboard MB. Symbol PM is an RF (Radio Frequency) power module (hereinafter simply referred to as a power module) that is the electronic device of the first embodiment, symbol ANT is an antenna for transmitting and receiving signal radio waves, and symbol FEM is a front end module. The code BBC converts the audio signal into a baseband signal, converts the received signal into an audio signal, generates the modulation system switching signal and the band switching signal, and the code FMC downcodes the received signal. Modulation / demodulation circuits FLT1 and FLT2 that demodulate and demodulate to generate a baseband signal and modulate the transmission signal are filters that remove noise and interference from the received signal power. Filter FLT1 is for GSM and filter FLT2 is for DCS. The baseband circuit BBC is composed of a plurality of semiconductor integrated circuits such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory. The front end module FEM has low-pass filters LPFl and LPF2, switch circuits SWl and SW2, capacitors CI and C2, and a duplexer WDC. Low-pass filters LPFl and LPF2 are circuits that attenuate harmonics, switch circuits SWl and SW2 are switch circuits for switching transmission and reception signals, capacitors CI and C2 are elements that cut the DC component from the received signal, and duplexer WDC is It is a circuit that demultiplexes GSM900 band signals and DCS1 800 band signals, and these circuits and elements are mounted on a single circuit board as a module. The switching signals C NT1 and CNT2 of the switch circuits SWl and SW2 are supplied from the baseband circuit BBC.
[0022] 次に、図 2は、上記パワーモジュール PMの回路ブロック図の一例を示している。ノ ヮーモジュール PMは、例えば GSM850、 GSM900、 DCS1800および DCS1900 の 4つの周波数帯を使用可能 (フォーバンド方式)で、それぞれの周波数帯で GMS K (Gaussian filtered Minimum Shift Keying)変 方式と EDGE (Enhanced Data GSM Environment)変調方式との 2つの通信方式を使用可能な構成とされて!/、る。  Next, FIG. 2 shows an example of a circuit block diagram of the power module PM. The noise module PM can use four frequency bands, e.g. GSM850, GSM900, DCS1800 and DCS1900 (four-band method), and GMS K (Gaussian filtered Minimum Shift Keying) and EDGE (Enhanced Data) in each frequency band. GSM Environment) It is configured to be able to use two communication systems with modulation system! /
[0023] このパワーモジュール PMは、 GSM850および GSM900用の増幅回路部 2Aと、 DCS1800および DCS1900用の増幅回路部 2Bと、それら増幅回路部 2A, 2Bの 増幅動作の制御や補正等を行う周辺回路 3とを有している。各増幅回路部 2A, 2B は、それぞれ直列に接続された 3つの増幅回路部 2A1— 2A3, 2B1— 2B3と、 4つ のインピーダンス整合回路 2AM1— 2AM4, 2BM1— 2BM4とを有している。すな わち、パワーモジュール PMの入力端子 Tal, Tblは、入力段のインピーダンス整合 回路 2AM1, 2BM1を介して 1段目の増幅回路部 2A1, 2B1の入力に電気的に接 続され、 1段目の増幅回路部 2A1, 2B1の出力は段間用のインピーダンス整合回路 2AM2, 2BM2を介して 2段目の増幅回路部 2A2, 2B2の入力に電気的に接続さ れ、 2段目の増幅回路部 2A2, 2B2の出力は段間用のインピーダンス整合回路 2A M3, 2BM3を介して最終段の増幅回路部 2A3, 2B3の入力に電気的に接続され、 最終段の増幅回路部 2A3, 2B3の出力は出力段のインピーダンス整合回路 2AM4 , 2BM4を介して出力端子 Ta2, Tb2と電気的に接続されている。 [0023] This power module PM includes an amplifier circuit unit 2A for GSM850 and GSM900, an amplifier circuit unit 2B for DCS1800 and DCS1900, and a peripheral circuit that controls and corrects the amplification operation of these amplifier circuit units 2A and 2B. And 3. Each amplifier circuit section 2A, 2B has three amplifier circuit sections 2A1-2A3, 2B1-2B3 connected in series, and four impedance matching circuits 2 AM1-2AM4, 2BM1-2BM4. In other words, the input terminals Tal and Tbl of the power module PM are electrically connected to the inputs of the first stage amplification circuit sections 2A1 and 2B1 via the impedance matching circuits 2AM1 and 2BM1 of the input stage, and are connected to the first stage. The output of the second amplification circuit section 2A1, 2B1 is electrically connected to the input of the second stage amplification circuit section 2A2, 2B2 via the interstage impedance matching circuit 2AM2, 2BM2, and the second stage amplification circuit The outputs of the parts 2A2 and 2B2 are electrically connected to the inputs of the final stage amplifier circuit parts 2A3 and 2B3 via the interstage impedance matching circuits 2A M3 and 2BM3. The outputs of the final stage amplifier circuits 2A3 and 2B3 are electrically connected to the output terminals Ta2 and Tb2 via the impedance matching circuits 2AM4 and 2BM4 of the output stage.
[0024] 上記周辺回路 3は、制御回路 3Aと、上記増幅回路部 2A1— 2A3, 2B1— 2B3に バイアス電圧を印加するバイアス回路 3B等を有している。制御回路 3Aは、上記増幅 回路部 2A, 2Bに印加する所望の電圧を発生する回路であり、電源制御回路 3A1お よびバイアス電圧生成回路 3A2を有している。電源制御回路 3A1は、上記増幅回路 部 2A1— 2A3, 2B1— 2B3の各々の出力用のパワー MOS 'FETのドレイン端子に 印加される第 1電源電圧を生成する回路である。また、上記バイアス電圧生成回路 3 A2は、上記バイアス回路 3Bを制御するための第 1制御電圧を生成する回路である。 本実施の形態 1では、電源制御回路 3A1が、パワーモジュール PMの外部の上記べ ースバンド回路 BBC力 供給される出力レベル指定信号に基づいて上記第 1電源 電圧を生成すると、バイアス電圧生成回路 3A2が電源制御回路 3A1で生成された 上記第 1電源電圧に基づ 、て上記第 1制御電圧を生成するようになって！/、る。上記 ベースバンド回路 BBCは、上記出力レベル指定信号を生成する回路である。この出 カレベル指定信号は、増幅回路部 2A, 2Bの出力レベルを指定する信号で、携帯電 話と、基地局との間の距離、すなわち、電波の強弱に応じた出力レベルに基づいて 生成されて 、るようになって!/、る。  The peripheral circuit 3 includes a control circuit 3A, a bias circuit 3B for applying a bias voltage to the amplifier circuit units 2A1-2A3, 2B1-2B3, and the like. The control circuit 3A is a circuit that generates a desired voltage to be applied to the amplification circuit units 2A and 2B, and includes a power supply control circuit 3A1 and a bias voltage generation circuit 3A2. The power supply control circuit 3A1 is a circuit that generates a first power supply voltage to be applied to the drain terminals of the power MOS FETs for output of each of the amplification circuit sections 2A1-2A3, 2B1-2B3. The bias voltage generation circuit 3 A2 is a circuit that generates a first control voltage for controlling the bias circuit 3B. In the first embodiment, when the power supply control circuit 3A1 generates the first power supply voltage based on the output level designation signal supplied from the baseband circuit BBC power outside the power module PM, the bias voltage generation circuit 3A2 Based on the first power supply voltage generated by the power supply control circuit 3A1, the first control voltage is generated! / The baseband circuit BBC is a circuit that generates the output level designation signal. This output level designation signal is a signal that designates the output level of the amplifier circuits 2A and 2B, and is generated based on the distance between the mobile phone and the base station, that is, the output level according to the strength of the radio wave. And become like! /
[0025] 次に、図 3は、上記図 1のデジタル携帯電話機システム DPSの上記パワーモジユー ル PMの実装例を示している。マザ一ボード MBは、例えば多層配線構造を有するプ リント配線基板等力 なり、その主面上には、パワーモジュール PMと複数のチップ部 品 5とが実装されている。パワーモジュール PMは、モジュール基板 (配線基板) MC Bの裏面 (モジュール実装面）の複数の電極 (外部接続用電極)の各々に接続された バンプ電極 (外部端子、突起電極) 6を介してマザ一ボード MBの主面上に実装され ている。すなわち、パワーモジュール PMは、モジュール実装面に複数の突起状のバ ンプ電極 6をアレイ状に配置した、いわゆる BGA (Ball Grid Array)パッケージ構成と されている。また、チップ部品 5は、接合材 7を介してマザ一ボード MBの主面上に実 装されている。バンプ電極 6および接合材 7の材料には、例えば錫"!良 (Ag)KCu )合金や錫 銀 ビスマス (Bi) 合金等のような錫 銀系の鉛フリー (無鉛)半田（融 点:約 221度）、錫 ニッケル (Ni)合金等のような錫 銅系の鉛フリー半田（融点： 約 227度）、錫 亜鉛 (Zn)合金等のような錫 亜鉛系の鉛フリー半田（融点:約 198 度）、錫 ビスマス 銀合金等のような錫 ビスマス系の鉛フリー半田（融点:約 148度 )または錫 アンチモン (Sb)合金の鉛フリー半田等が使用されて 、る。パワーモジュ ール PMとチップ部品 5とはマザ一ボード MBの配線を通じて互いに電気的に接続さ れて上記デジタル携帯電話機システム DPSが形成されて ヽる。モジュール基板 MC Bの主面 (被部品実装面）は、例えばシリコーンゴム (シリコーン榭脂）やエポキシ榭脂 等力 なる封止部材 8により覆われ、これによりモジュール基板 MCBの主面に実装さ れた後述の半導体チップやチップ部品等のような電子部品が封止されている。 Next, FIG. 3 shows an implementation example of the power module PM of the digital cellular phone system DPS shown in FIG. The mother board MB is, for example, a printed wiring board having a multilayer wiring structure, and a power module PM and a plurality of chip components 5 are mounted on the main surface thereof. The power module PM is connected via a bump electrode (external terminal, protruding electrode) 6 connected to each of a plurality of electrodes (external connection electrodes) on the back surface (module mounting surface) of the module board (wiring board) MC B. It is mounted on the main surface of one board MB. That is, the power module PM has a so-called BGA (Ball Grid Array) package configuration in which a plurality of protruding bump electrodes 6 are arranged in an array on the module mounting surface. Further, the chip component 5 is mounted on the main surface of the mother board MB via the bonding material 7. The material of the bump electrode 6 and the bonding material 7 includes, for example, a tin-silver-based lead-free (lead-free) solder (such as a tin “! Good (Ag) KCu) alloy or a tin-silver-bismuth (Bi) alloy” Point: about 221 degrees), tin-copper-based lead-free solder such as tin-nickel (Ni) alloy (melting point: about 227 degrees), tin-zinc-based lead-free solder such as tin-zinc (Zn) alloy ( Melting point: about 198 degrees), tin-bismuth-based lead-free solder (melting point: about 148 degrees), such as tin-bismuth silver alloy, or lead-free solder of tin antimony (Sb) alloy is used. The power module PM and the chip component 5 are electrically connected to each other through the wiring of the mother board MB to form the digital mobile phone system DPS. The main surface (mounting part mounting surface) of the module board MC B is covered with, for example, a silicone rubber (silicone resin) or an epoxy resin, and the like, and is mounted on the main surface of the module board MCB. Electronic components such as semiconductor chips and chip components described later are sealed.
[0026] 上記パワーモジュール PMのバンプ電極 6の材料は、鉛フリー半田の他に、金（Au )を用いても良い。また、上記パワーモジュール PMのパッケージ構成は、 BGAパッ ケージ構成の他に、モジュール実装面に複数の平らな電極パッドをアレイ状に配置 した、いわゆる LGA (Land Grid Array)パッケージ構成としても良い。  [0026] The bump electrode 6 of the power module PM may be made of gold (Au) in addition to lead-free solder. In addition to the BGA package configuration, the power module PM package configuration may be a so-called LGA (Land Grid Array) package configuration in which a plurality of flat electrode pads are arranged in an array on the module mounting surface.
[0027] 次に、図 4は上記パワーモジュール PMのモジュール基板 MCBの主面（被部品実 装面）の一例の平面図、図 5は図 4のモジュール基板 MCBの裏面（モジュール実装 面）の一例の平面図、図 6は図 4の XI— XI線の断面図の一例をそれぞれ示している 。なお、図 4および図 6では、モジュール基板 MCBの主面 (被部品実装面）が見える ように図 3で示した封止部材 9を取り除いている。また、図 4および図 5の Xは第 1方向 、 Yは第 1方向 Xに直交する第 2方向を示している。  Next, FIG. 4 is a plan view of an example of the main surface (part mounting surface) of the module board MCB of the power module PM, and FIG. 5 is the back surface (module mounting surface) of the module board MCB of FIG. FIG. 6 shows an example of a cross-sectional view taken along line XI-XI in FIG. In FIGS. 4 and 6, the sealing member 9 shown in FIG. 3 is removed so that the main surface (component mounting surface) of the module substrate MCB can be seen. 4 and 5, X represents the first direction, and Y represents the second direction orthogonal to the first direction X.
[0028] モジュール基板 MCBは、絶縁層 11と配線 12とを交互に積層して一体ィ匕した多層 配線構造を有している。この絶縁層 11は、例えばミリ波域まで誘電損失の少ないァ ルミナ（酸ィ匕アルミニウム、 Al O、比誘電率 = 9一 9. 7)等のようなセラミックにより形  [0028] The module substrate MCB has a multilayer wiring structure in which insulating layers 11 and wirings 12 are alternately laminated and integrated. This insulating layer 11 is made of ceramic such as alumina (acid aluminum, Al 2 O, relative permittivity = 9 to 19.7) having a low dielectric loss up to the millimeter wave region.
2 3  twenty three
成されている。ただし、絶縁層 11の材料は、これに限定されるものではなく種々変更 可能であり、例えばガラスエポキシ榭脂等を用いても良い。モジュール基板 MCBの 内層には、配線 12およびビア 12Vが形成されている。モジュール基板 MCBの各層 の配線 12はビア 12Vを通じて電気的に接続されて!、る。この内層の配線 12および ビア 12Vは、例えば銅 (Cu)とタングステン (W)との合金カゝらなる。また、最上の絶縁 層 11の被部品実装面（主面、第 1面）および最下の絶縁層 11のモジュール実装面（ 裏面、第 2面）には、配線 12および電極 (ランド、端子、導体パターン） 12Eが形成さ れている。この配線 12および電極 12Eは、例えば銅（Cu)とタングステン (W)との合 金からなり、その表面には、ニッケル (Ni)メツキおよび金 (Au)メツキが下層力も順に 施されて!/、る。さらに最上の絶縁層 11の被部品実装面および最下の絶縁層 11のモ ジュール実装面には、例えばオーバーコートガラス (珪素）のような半田（鉛 (Pb)—錫 (Sn) )にぬれな 、性質を持つ絶縁層 13が配線 12の表面を覆うように形成されて!ヽ る。絶縁層 13の一部は、開口されており、そこ力 電極 12Eが露出されている。モジ ユール基板 MCBの裏面の電極 12Eのうち、モジュール基板 MCBの裏面中央の幅 広の電極 12E1は、基準電位 (接地電位 GNDで、例えば OV)用の電極である。また 、モジュール基板 MCBの裏面外周角部の電極 12E2は、 RF信号用の電極である。 また、モジュール基板 MCBの裏面外周の電極 12E3は、バイアス電圧供給用の電 極である。また、モジュール基板 MCBの裏面外周の電極 12E4は、制御信号用の電 極である。 It is made. However, the material of the insulating layer 11 is not limited to this, and can be variously changed. For example, glass epoxy resin may be used. Wiring 12 and via 12V are formed in the inner layer of module board MCB. The wiring 12 of each layer of the module board MCB is electrically connected through the via 12V! The inner layer wiring 12 and via 12V are made of, for example, an alloy of copper (Cu) and tungsten (W). Also, the component mounting surface (main surface, first surface) of the uppermost insulating layer 11 and the module mounting surface of the lowermost insulating layer 11 ( Wiring 12 and electrodes (land, terminal, conductor pattern) 12E are formed on the back surface and the second surface. The wiring 12 and the electrode 12E are made of, for example, a alloy of copper (Cu) and tungsten (W), and nickel (Ni) plating and gold (Au) plating are sequentially applied to the surface with lower layer force! / RU Furthermore, the component mounting surface of the uppermost insulating layer 11 and the module mounting surface of the lowermost insulating layer 11 are wetted by solder (lead (Pb) —tin (Sn)) such as overcoat glass (silicon). However, an insulating layer 13 having properties may be formed so as to cover the surface of the wiring 12! A part of the insulating layer 13 is opened, and the force electrode 12E is exposed there. Of the electrodes 12E on the back surface of the module substrate MCB, the wide electrode 12E1 at the center of the back surface of the module substrate MCB is an electrode for a reference potential (ground potential GND, for example, OV). Further, the electrode 12E2 at the outer peripheral corner of the back surface of the module substrate MCB is an RF signal electrode. The electrode 12E3 on the outer periphery of the back surface of the module board MCB is an electrode for supplying a bias voltage. The electrode 12E4 on the outer periphery of the back surface of the module board MCB is an electrode for control signals.
[0029] モジュール基板 MCBの被部品実装面には、例えば 1つの半導体チップ (電子部品 ) 15が実装されている他、例えば大きさの異なる 3種類のチップ部品（電子部品、受 動部品） 16 (16a— 16c)が実装されている。  [0029] For example, one semiconductor chip (electronic component) 15 is mounted on the component mounting surface of the module board MCB, and for example, three types of chip components (electronic component and passive component) of different sizes 16 (16a-16c) is implemented.
[0030] 半導体チップ 15は、その主面 (デバイス形成面）を上に向けた状態で、モジュール 基板 MCBの主面中央のキヤビティと称する平面略矩形状の窪み 17内に収まり良く 実装されている。半導体チップ 15には、上記 GSM850および GSM900用の 3段の 増幅回路部 2A1— 2A3と、 DCS1800および DCS1900用の 3段の増幅回路部 2B 1一 2B3とが形成されている。この半導体チップ 15の主面の外周近傍には、その外 周に沿って複数のボンディングパッド (外部端子：以下、単にパッドと!/、う） Pが形成さ れている。ノッド Pは、半導体チップ 15に形成された回路の引き出し電極である。ま た、この半導体チップ 15の外周のモジュール基板 MCBの被部品実装面には、複数 の電極 12E力 半導体チップ 15の外周を取り囲むように配置されている。各電極 12 Eは、モジュール基板 MCBの主面の上記配線 12と一体的に形成されている。この 各電極 12Eと、半導体チップ 15のノ¾ /ド Pとは、その各々に接した状態で接続された ボンディングワイヤ（以下、単にワイヤという） BWを通じて互いに電気的に接続されて いる。ワイヤ BWは、例えば金 (Au)により形成されている。また、半導体チップ 15の 裏面は、モジュール基板 MCBの窪み 17の底面の電極 12Eに接続され、さらにビア 1 2Vを通じてモジュール基板 MCBの裏面の電極 12E1と電気的に接続されて!、る。 [0030] The semiconductor chip 15 is well mounted in a substantially rectangular recess 17 called a cavity at the center of the main surface of the module substrate MCB with its main surface (device forming surface) facing upward. . The semiconductor chip 15 is formed with three stages of amplification circuit sections 2A1-2A3 for GSM850 and GSM900 and three stages of amplification circuit sections 2B1, 2B3 for DCS1800 and DCS1900. In the vicinity of the outer periphery of the main surface of the semiconductor chip 15, a plurality of bonding pads (external terminals: hereinafter simply referred to as pads! /) Are formed along the outer periphery. The node P is a lead electrode for a circuit formed on the semiconductor chip 15. Further, on the part mounting surface of the module substrate MCB on the outer periphery of the semiconductor chip 15, it is arranged so as to surround the outer periphery of the plurality of electrodes 12E force semiconductor chip 15. Each electrode 12E is formed integrally with the wiring 12 on the main surface of the module substrate MCB. Each of the electrodes 12E and the semiconductor layer 15 are connected to each other through a bonding wire (hereinafter simply referred to as a wire) BW connected in contact therewith. Yes. The wire BW is made of, for example, gold (Au). Further, the back surface of the semiconductor chip 15 is connected to the electrode 12E on the bottom surface of the recess 17 of the module substrate MCB, and is further electrically connected to the electrode 12E1 on the back surface of the module substrate MCB through vias 12V.
[0031] 図 7は、上記増幅回路部 2A1— 2A3, 2B1— 2B3を構成する半導体増幅素子を L DMOSFET(Laterally Diffused Metaト Oxide- Semiconductor Field Effect Transistor 、横方向拡散 MOSFET)により形成した場合の半導体チップ 15の要部断面図の一 例を示している。 [0031] FIG. 7 shows a semiconductor in which the semiconductor amplifying elements constituting the amplifying circuit portions 2A1-2A3, 2B1-2B3 are formed by LDMOSFETs (Laterally Diffused Meta-Oxide-Semiconductor Field Effect Transistors). An example of a cross-sectional view of the main part of the chip 15 is shown.
[0032] p+型単結晶シリコン力もなる半導体基板 201の主面には、 p—型単結晶シリコンから なるェピタキシャル層 202が形成され、ェピタキシャル層 202の主面の一部には、 L DMOSFETのドレインからソースへの空乏層の延びを抑えるパンチスルーストツバと しての機能する P型ゥエル 203が形成されている。 p型ゥエル 203の表面には、酸ィ匕 シリコンなどからなるゲート絶縁膜 204を介して LDMOSFETのゲート電極 205が形 成されている。ゲート電極 205は、例えば n型の多結晶シリコン膜と金属シリサイド膜 の積層膜などからなり、ゲート電極 205の側壁には、酸ィ匕シリコンなど力もなるサイド ウォールスぺーサ 206が形成されて!ヽる。  [0032] An epitaxial layer 202 made of p-type single crystal silicon is formed on the main surface of the semiconductor substrate 201 that also has p + type single crystal silicon force, and an L DMOSFET is formed on a part of the main surface of the epitaxial layer 202. A P-type well 203 is formed, which functions as a punch-through streak that suppresses the extension of the depletion layer from the drain to the source. On the surface of the p-type well 203, an LDMOSFET gate electrode 205 is formed through a gate insulating film 204 made of silicon oxide or the like. The gate electrode 205 is made of, for example, a laminated film of an n-type polycrystalline silicon film and a metal silicide film, and a sidewall spacer 206 having a force such as silicon oxide is formed on the side wall of the gate electrode 205. The
[0033] ェピタキシャル層 202の内部のチャネル形成領域を挟んで互いに離間する領域に は、 LDMOSFETのソース、ドレインが形成されている。ドレインは、チャネル形成領 域に接する n—型オフセットドレイン領域 207と、 n—型オフセットドレイン領域 207に接 し、チャネル形成領域力も離間して形成された n型オフセットドレイン領域 208と、 n型 オフセットドレイン領域 208に接し、チャネル形成領域からさらに離間して形成された n+型ドレイン領域 209と力もなる。これら n—型オフセットドレイン領域 207、 n型オフセ ットドレイン領域 208および n+型ドレイン領域 209のうち、ゲート電極 205に最も近い n—型オフセットドレイン領域 207は不純物濃度が最も低く、ゲート電極 205から最も離 間した n+型ドレイン領域 209は不純物濃度が最も高い。  In the regions separated from each other across the channel formation region inside the epitaxial layer 202, the source and drain of the LDMOSFET are formed. The drain is an n-type offset drain region 207 that is in contact with the channel formation region, an n-type offset drain region 208 that is in contact with the n-type offset drain region 207 and is separated from the channel formation region force, and an n-type offset. The n + type drain region 209 formed in contact with the drain region 208 and further away from the channel formation region also acts as a force. Of these n-type offset drain region 207, n-type offset drain region 208, and n + type drain region 209, n-type offset drain region 207 closest to gate electrode 205 has the lowest impurity concentration and is the farthest away from gate electrode 205. The interstitial n + type drain region 209 has the highest impurity concentration.
[0034] LDMOSFETのソースは、チャネル形成領域に接する n—型ソース領域 210と、 n— 型ソース領域 210に接し、チャネル形成領域から離間して形成され、 n—型ソース領域 210よりも不純物濃度が高い n+型ソース領域 211と力もなる。 n—型ソース領域 210の 下部には、 p型ハロー領域 212が形成されている。 [0035] n+型ソース領域 211の端部 (n-型ソース領域 210と接する側と反対側の端部）に は、 n+型ソース領域 211と接する p型打抜き層 214が形成されている。 p型打抜き層 214の表面近傍には、 p+型半導体領域 215が形成されている。 p型打抜き層 214は 、LDMOSFETのソースと半導体基板 201とを電気的に接続するための導電層であ り、例えばェピタキシャル層 202に形成した溝 213の内部に埋め込んだ p型多結晶シ リコン膜によって形成される。 [0034] The source of the LDMOSFET is formed in contact with the n-type source region 210 in contact with the channel formation region, and in contact with the n- type source region 210, and is separated from the channel formation region, and has an impurity concentration higher than that in the n-type source region 210. High n + type source region 211 and power. A p-type halo region 212 is formed below the n-type source region 210. A p-type punching layer 214 in contact with the n + type source region 211 is formed at the end of the n + type source region 211 (the end opposite to the side in contact with the n− type source region 210). Near the surface of the p-type punching layer 214, a p + type semiconductor region 215 is formed. The p-type punching layer 214 is a conductive layer for electrically connecting the source of the LDMOSFET and the semiconductor substrate 201, for example, a p-type polycrystalline silicon embedded in the groove 213 formed in the epitaxial layer 202. Formed by a film.
[0036] LDMOSFETの p型打抜き層 214 (p+型半導体領域 215)、ソース（n+型ソース領 域 211)およびドレイン (n+型ドレイン領域 209)のそれぞれの上部には、窒化シリコ ン膜 221と酸化シリコン膜 222とに形成されたコンタクトホール 223内のプラグ 224が 接続されている。 p型打抜き層 214 (p+型半導体領域 215)およびソース (n+型ソース 領域 211)には、プラグ 224を介してソース電極 225が接続され、ドレイン (n+型ドレイ ン領域 209)には、プラグ 224を介してドレイン電極 226が接続されている。  [0036] LDMOSFET p-type punch layer 214 (p + type semiconductor region 215), source (n + type source region 211), and drain (n + type drain region 209) are respectively formed on top of silicon nitride film 221 and oxide. A plug 224 in a contact hole 223 formed in the silicon film 222 is connected. A source electrode 225 is connected to the p-type punching layer 214 (p + type semiconductor region 215) and the source (n + type source region 211) via a plug 224, and a plug 224 is connected to the drain (n + type drain region 209). A drain electrode 226 is connected via
[0037] ドレイン電極 226およびソース電極 225のそれぞれには、ドレイン電極 226およびソ ース電極 225を覆う酸化シリコン膜 227に形成されたスルーホール 228を介して配線 229が接続されている。配線 229の上部には、酸ィ匕シリコン膜と窒化シリコン膜の積 層膜からなる表面保護膜 230が形成されている。また、半導体基板 201の裏面には ソース裏面電極 231が形成されて!、る。  A wiring 229 is connected to each of the drain electrode 226 and the source electrode 225 via a through hole 228 formed in the silicon oxide film 227 that covers the drain electrode 226 and the source electrode 225. On the upper part of the wiring 229, a surface protective film 230 made of a multilayer film of an oxide silicon film and a silicon nitride film is formed. Further, a source back electrode 231 is formed on the back surface of the semiconductor substrate 201.
[0038] 図 8は、上記増幅回路部 2A1— 2A3, 2B1— 2B3を構成する半導体増幅素子を ヘテロ接合型バイポーラトランジスタ（HBT: Hetero junction Bipolar Transistor)に より形成した場合の半導体チップ 15a— 15cの要部断面図の一例を示している。  [0038] FIG. 8 shows a configuration of the semiconductor chips 15a-15c in the case where the semiconductor amplifying elements constituting the amplifying circuit sections 2A1-2A3, 2B1-2B3 are formed by heterojunction bipolar transistors (HBTs). An example of a fragmentary sectional view is shown.
[0039] 半絶縁性の GaAs基板（半導体基板） 251上に n+型 GaAs層よりなるサブコレクタ 層 252が形成され、サブコレクタ層 252上に HBT253が形成されている。  A subcollector layer 252 made of an n + type GaAs layer is formed on a semi-insulating GaAs substrate (semiconductor substrate) 251, and an HBT 253 is formed on the subcollector layer 252.
[0040] 各 HBT253は、サブコレクタ層 252上に形成された金などからなるコレクタ電極 25 4と、このコレクタ電極 254とは所定間隔だけ離間して形成されたコレクタメサ 255を 有している。コレクタメサ 255は、例えば n型 GaAs層より形成され、コレクタメサ 255と コレクタ電極 254はサブコレクタ層 252を介して電気的に接続されている。  Each HBT 253 has a collector electrode 254 made of gold or the like formed on the sub-collector layer 252 and a collector mesa 255 formed so as to be separated from the collector electrode 254 by a predetermined distance. The collector mesa 255 is formed of, for example, an n-type GaAs layer, and the collector mesa 255 and the collector electrode 254 are electrically connected via the subcollector layer 252.
[0041] コレクタメサ 255上には、例えば p型 GaAs層よりなるベースメサ 256が形成されてい る。ベースメサ 256上の周辺領域には金等よりなるベース電極 257が形成されて!、る 。ベースメサ 256の略中央部上にェミッタ層 258が形成され、ェミッタ層 258上にエミ ッタ電極 259が形成されている。ェミッタ層 258は、例えば n型 InGaP層、 GaAs層お よび InGaAs層を積層した層より形成され、ェミッタ電極 259は、例えばタングステン シリサイド力も形成されている。このように、ベースメサ (p型 GaAs層) 256とェミッタ層（ n型 InGaP層） 258との間には異種半導体接合 (ヘテロ接合）が形成されている。 [0041] On the collector mesa 255, a base mesa 256 made of, for example, a p-type GaAs layer is formed. A base electrode 257 made of gold or the like is formed in the peripheral area on the base mesa 256! . An emitter layer 258 is formed on a substantially central portion of the base mesa 256, and an emitter electrode 259 is formed on the emitter layer 258. The emitter layer 258 is formed of, for example, an n-type InGaP layer, a GaAs layer, and an InGaAs layer, and the emitter electrode 259 is formed of, for example, a tungsten silicide force. Thus, a heterogeneous semiconductor junction (heterojunction) is formed between the base mesa (p-type GaAs layer) 256 and the emitter layer (n-type InGaP layer) 258.
[0042] コレクタ電極 254には、絶縁膜 261に形成されたコンタクトホール 262を介してコレ クタ配線 263が接続されている。ェミッタ電極 259には、絶縁膜 264, 261に形成さ れたスルーホール 265を介してェミッタ配線 266が接続されて!、る。ェミッタ配線 266 よりも上層の構造については、ここでは図示およびその説明を省略する。  A collector wiring 263 is connected to the collector electrode 254 via a contact hole 262 formed in the insulating film 261. An emitter wiring 266 is connected to the emitter electrode 259 through through holes 265 formed in the insulating films 264 and 261. The illustration of the structure above the emitter wiring 266 is omitted here.
[0043] 一方、図 4に示した上記チップ部品 16a— 16cは、その電極がモジュール基板 MC Bの被部品実装面の電極 12Eに接続された状態でモジュール基板 MCBの被部品 実装面上に実装されている。チップ部品 16には、例えばコンデンサ CG1— CG6, C A1— CA3、フェライトビーズ FB1、インダクタ LG1および抵抗 Rl, R3, R5等のよう な受動素子が形成されて 、る。  On the other hand, the chip components 16a to 16c shown in FIG. 4 are mounted on the component mounting surface of the module substrate MCB in a state where the electrodes are connected to the electrodes 12E of the component mounting surface of the module substrate MC B. Has been. The chip component 16 is formed with passive elements such as capacitors CG1-CG6, CA1-CA3, ferrite beads FB1, inductor LG1, resistors Rl, R3, R5, and the like.
[0044] チップ部品 16の中でサイズが最も小さいチップ部品（第 1受動部品） 16a (図面を見 易くするためチップ部品 16aに梨地のハッチングを付す）は、 0402型のチップ部品 である。このチップ部品 16aの採用によりパワーモジュール PMの小型化がなされて いる。ここでは、抵抗 Rl, R3, R5およびコンデンサ CG1等が形成されたチップ部品 16aが例示されている。このチップ部品 16aよりも大きなチップ部品（第 2受動部品） 1 6bは、 0603型のチップ部品である。ここでは、コンデンサ CG2— CG6, CA1— CA 3およびフェライトビーズ FBI等が形成されたチップ部品 16bが例示されている。さら に、このチップ部品 16bよりも大きなチップ部品（第 2受動部品） 16cは、 1005型のチ ップ部品である。ここでは、インダクタ LG1が形成されたチップ部品 16cが例示されて いる。  [0044] The chip component (first passive component) 16a having the smallest size among the chip components 16 (the chip component 16a is mattely hatched to make the drawing easy to see) is a 0402 type chip component. By adopting this chip component 16a, the power module PM is downsized. Here, a chip component 16a in which resistors Rl, R3, R5, a capacitor CG1, and the like are formed is illustrated. A chip component (second passive component) 16b larger than the chip component 16a is a 0603 type chip component. Here, a chip component 16b in which capacitors CG2-CG6, CA1-CA3, ferrite beads FBI, and the like are formed is illustrated. Furthermore, a chip component (second passive component) 16c larger than the chip component 16b is a 1005 type chip component. Here, a chip component 16c in which an inductor LG1 is formed is illustrated.
[0045] ここで、図 9はモジュール基板 MCBの被部品実装面であってチップ部品 16 (16a 一 16c)の実装領域の拡大平面図、図 10は図 9にチップ部品 16 ( 16a— 16c)を実装 した状態を示す拡大平面図、図 11は図 10の X2— X2線の断面図をそれぞれ示して いる。なお、チップ部品 16a— 16cは、各々の寸法や電気的規定値は異なるものの、 チップ部品 16の構成やモジュール基板 MCBのチップ部品 16の実装領域の構成は 同じである。 Here, FIG. 9 is an enlarged plan view of the mounting area of the chip component 16 (16a and 16c) on the mounting surface of the module substrate MCB, and FIG. 10 shows the chip component 16 (16a-16c) in FIG. Fig. 11 is a cross-sectional view taken along the line X2-X2 in Fig. 10, showing the state where is mounted. Chip parts 16a-16c have different dimensions and electrical specifications, The configuration of the chip component 16 and the configuration of the mounting area of the chip component 16 of the module board MCB are the same.
[0046] モジュール基板 MCBの被部品実装面上の絶縁層 13には開口部 20, 20が形成さ れており、その開口部 20, 20の各々力 一対の電極 12E, 12Eの各々が露出されて いる。一対の電極 12E, 12Eの各々の外周部は、絶縁層 13の端部（すなわち、開口 部 20の端部）から離れている。チップ部品 16 (16a— 16c)の一対の電極 16E, 16E の各々は、モジュール基板 MCBの開口部 20, 20の各々力も露出された一対の電 極 12Eの各々と接着材 21により接続されている。接着材 21は、例えば鉛 (Pb)—錫（ Sn)の半田力もなる。この Pb— Snの融点は、 Pbと Snとの割合によつて異なる力 一 例として Pb-Snの割合が 37Z63 (共晶半田）の場合、例えば約 183度である。チッ プ部品 16a— 16cの実装領域においてモジュール基板 MCBの一対の電極 12Eの 隣接間の絶縁層 11上には絶縁層 13が残されて 、る。  [0046] Openings 20 and 20 are formed in the insulating layer 13 on the component mounting surface of the module board MCB, and each of the pair of electrodes 12E and 12E is exposed. ing. The outer peripheral portion of each of the pair of electrodes 12E and 12E is separated from the end portion of the insulating layer 13 (that is, the end portion of the opening 20). Each of the pair of electrodes 16E, 16E of the chip component 16 (16a-16c) is connected to each of the pair of electrodes 12E where the forces of the openings 20, 20 of the module board MCB are also exposed by the adhesive 21. . The adhesive 21 also has, for example, a lead (Pb) -tin (Sn) soldering force. The melting point of Pb—Sn is different depending on the ratio of Pb and Sn. For example, when the ratio of Pb—Sn is 37Z63 (eutectic solder), it is about 183 degrees, for example. In the mounting region of the chip parts 16a to 16c, the insulating layer 13 is left on the insulating layer 11 between the adjacent electrodes 12E of the module board MCB.
[0047] チップ部品 16のうち、最も小さい 0402型のチップ部品 16aの長さ（チップ部品 16 の長手方向の全長） D1は、例えば 0. 4±0. 02mm,電極長さ（チップ部品 16の長 手方向の電極 16Eの長さ） D2は、例えば 0. 07-0. 12mm,電極間長さ（チップ部 品 16の長手方向の隣接する電極 16E間の長さ） D3は、例えば 0. 15mm以上、幅（ チップ部品 16の短方向の長さ） D4は、例えば 0. 2±0. 02mm,高さ D5は、チップ コンデンサの場合で、例えば 0. 2±0. 02mm,チップ抵抗の場合で、例えば 0. 12 ±0. 02mmである。また、チップ部品 16aの実装領域の一対の電極 12Eの各々の 長さ（一対の電極 12Eが並ぶ方向の長さ） D6は、例えば 0. 15mm,一対の電極 12 Eの各々の幅（一対の電極 12Eが並ぶ方向に直交する方向の長さ） D7は、例えば 0 . 25mm,電極 12Eの外周から開口部 20の端部までの間隔 D8は、例えば 0. 0375 mm、一対の電極 12Eの隣接間隔 D9は、例えば 0. 175mm以上であり、例えば 0. 205mm,一対の電極 12Eの隣接間に残された絶縁層 13の幅（一対の電極 12Eが 並ぶ方向の長さ） D10は、例えば 0. 13mmである。  [0047] The length of the smallest 0402 type chip component 16a among the chip components 16 (the total length in the longitudinal direction of the chip component 16) D1 is, for example, 0.4 ± 0.02 mm, and the electrode length (of the chip component 16) The length of the electrode 16E in the longitudinal direction) D2 is, for example, 0.0-07-0.12 mm, and the length between the electrodes (the length between the adjacent electrodes 16E in the longitudinal direction of the chip part 16) D3 is, for example, 0. 15mm or more, width (length in the short direction of chip component 16) D4 is 0.2 ± 0.02mm, height D5 is chip capacitor, for example 0.2 ± 0.02mm, chip resistance In some cases, for example, 0.12 ± 0.02 mm. The length of each of the pair of electrodes 12E in the mounting region of the chip component 16a (the length in the direction in which the pair of electrodes 12E are arranged) D6 is, for example, 0.15 mm, and the width of each of the pair of electrodes 12E (the pair of electrodes D7 is, for example, 0.25 mm, and the distance from the outer periphery of the electrode 12E to the end of the opening 20 is, for example, 0.0375 mm, adjacent to the pair of electrodes 12E. The distance D9 is, for example, 0.175 mm or more, for example, 0.205 mm, and the width of the insulating layer 13 left between the pair of electrodes 12E (the length in the direction in which the pair of electrodes 12E are arranged) D10 is, for example, 0 13mm.
[0048] 中間の大きさの 0603型のチップ部品 16bの長さ D1は、例えば 0. 6±0. 03mm, 電極長さ D2は、例えば 0. 1-0. 2mm、電極間長さ D3は、例えば 0. 2mm以上、 幅 D4は、例えば 0. 3±0. 03mm,高さ D5は、チップコンデンサの場合で、例えば 0 . 3±0. 03mm,チップ抵抗の場合で、例えば 0. 25±0. 03mmである。また、チッ プ部品 16bの実装領域の一対の電極 12Eの各々の長さ D6は、例えば 0. 3mm、一 対の電極 12Eの各々の幅 D7は、例えば 0. 35mm,電極 12Eの外周から開口部 20 の端部までの間隔 D8は、例えば 0. 05mm,一対の電極 12Eの隣接間隔 D9は、例 えば 0. 3mm、一対の電極 12Eの隣接間に残された絶縁層 13の幅 D10は、例えば 0. 2mmである。 [0048] The length D1 of the 0603-type chip part 16b having an intermediate size is, for example, 0.6 ± 0.03 mm, the electrode length D2 is, for example, 0.1-0.2 mm, and the inter-electrode length D3 is For example, 0.2 mm or more, width D4 is, for example, 0.3 ± 0.03 mm, and height D5 is, for example, a chip capacitor. 3 ± 0.03mm, in case of chip resistor, for example 0.25 ± 0.03mm. Further, the length D6 of each of the pair of electrodes 12E in the mounting region of the chip component 16b is, for example, 0.3 mm, and the width D7 of each of the pair of electrodes 12E is, for example, 0.35 mm, which is opened from the outer periphery of the electrode 12E. The distance D8 to the end of the portion 20 is 0.05 mm, for example, and the adjacent distance D9 of the pair of electrodes 12E is 0.3 mm, for example, and the width D10 of the insulating layer 13 left between the adjacent of the pair of electrodes 12E is For example, 0.2 mm.
[0049] 最も大きい 1005型のチップ部品 16cの長さ D1は、例えば 1. 0±0. 05mm,電極 長さ D2は、例えば 0. 15-0. 3mm、電極間長さ D3は、例えば 0. 4mm以上、幅 D 4は、例えば 0. 5±0. 05mm,高さ D5は、チップコンデンサの場合で、例えば 0. 5 ±0. 05mm,チップ抵抗の場合で、例えば 0. 35±0. 05mmである。また、チップ 部品 16cの実装領域の一対の電極 12Eの各々の長さ D6は、例えば 0. 4mm、一対 の電極 12Eの各々の幅 D7は、例えば 0. 55mm,電極 12Eの外周から開口部 20の 端部までの間隔 D8は、例えば 0. 6mm、一対の電極 12Eの隣接間隔 D9は、例えば 0. 05mm,一対の電極 12Eの隣接間に残された絶縁層 13の幅 D10は、例えば 0. 05mmで teる。  [0049] The length D1 of the largest 1005 type chip part 16c is, for example, 1.0 ± 0.05 mm, the electrode length D2 is, for example, 0.15-0.3 mm, and the interelectrode length D3 is, for example, 0. 4 mm or more, width D 4 is, for example, 0.5 ± 0.05 mm, height D5 is for chip capacitors, for example 0.5 ± 0.05 mm, for chip resistors, for example, 0.35 ± 0 05mm. Further, the length D6 of each of the pair of electrodes 12E in the mounting region of the chip part 16c is, for example, 0.4 mm, and the width D7 of each of the pair of electrodes 12E is, for example, 0.55 mm. The distance D8 to the end of the insulating layer 13 is, for example, 0.6 mm, the adjacent distance D9 of the pair of electrodes 12E is, for example, 0.05 mm, and the width D10 of the insulating layer 13 left between the adjacent of the pair of electrodes 12E is, for example, 0 Te at 05mm.
[0050] ところで、パワーモジュール PMの小型化を推進させるために 0402型のチップ部品 16を用いたという主旨からすると、 0402型のチップ部品 16aの実装領域では、一対 の電極 12E毎に開口部 20を形成せずに一対の電極 12Eの両方を包括するような大 きな開口部 20を形成する方が開口部 20と電極 12Eとの位置合わせ余裕を小さくで き、一対の電極 12Eの隣接間隔を狭めることができるので好ましい。また、 0402型の チップ部品 16aの場合、一対の電極 16Eの隣接間が 0603型や 1005型に比べて大 幅に狭いので一対の電極 12E毎に開口部 20を形成するよりも、開口部 20の形成の し易さの観点からも一対の電極 12E間に絶縁層 13を残さずに一対の電極 12Eの両 方を包括するような大きな開口部 20を形成する方が好ましい。しかし、チップ部品 16 aの実装領域の一対の電極 12Eの隣接間に絶縁層 13が残されておらずモジュール 基板 MCBの絶縁層 11が露出されていると、半田フラッシュ（チップ部品 16a— 16c の電極 16Eに付けた半田（接着材 21)がパワーモジュール PMをマザ一ボード MB 上に実装する時に溶け膨張し封止榭脂を割って出てくる現象）によりチップ部品 16a の各々の一対の電極 16E間を短絡させる問題が生じ易い。この半田フラッシュの問 題は、モジュール基板 MCBの裏面のバンプ電極 6がチップ部品 16a— 16cの電極 1 6Eに付けた接着材 21よりも融点の高い鉛フリー半田で形成されている場合に特に 生じ易い。これは、マザ一ボードへの実装の際の半田リフロー温度を高温 (約 260度 )にしなければならず、マザ一ボードへの実装の際に、パワーモジュール PM内のチ ップ部品実装用の半田（Pb— Sn)が再溶融する為である。また、一対の電極 12Eの 隣接間の絶縁層 11が露出されて 、るとモジュール基板 MCBの一対の電極 12Eに 所望の金属をめつき法等により被着する際に一対の電極 12E間の絶縁層 11の露出 面に上記所望の金属が残り易くなる結果、その金属残りによりチップ部品 16aの一対 の電極 16E間を短絡させる問題が生じ易い。特に 0402型のチップ部品 16aの場合 、一対の電極 16E間の距離が短いので、上記した半田フラッシュや金属残りに起因 する一対の電極 16E間の短絡不良の問題が生じ易い。 [0050] By the way, since the 0402 type chip component 16 is used to promote downsizing of the power module PM, in the mounting region of the 0402 type chip component 16a, an opening 20 is provided for each pair of electrodes 12E. It is possible to reduce the alignment margin between the opening 20 and the electrode 12E by forming a large opening 20 that covers both of the pair of electrodes 12E without forming a gap. Can be narrowed, which is preferable. In addition, in the case of the 0402 type chip component 16a, the distance between adjacent pairs of electrodes 16E is narrower than that of the 0603 type and 1005 type, so that the opening 20 is formed rather than forming the opening 20 for each pair of electrodes 12E. From the viewpoint of ease of formation, it is preferable to form a large opening 20 that covers both the pair of electrodes 12E without leaving the insulating layer 13 between the pair of electrodes 12E. However, if the insulating layer 13 is not left between the pair of electrodes 12E in the mounting region of the chip component 16a and the insulating layer 11 of the module board MCB is exposed, solder flash (chip components 16a-16c Chip component 16a due to solder (adhesive 21) attached to electrode 16E that melts and expands when power module PM is mounted on mother board MB and breaks sealing grease. The problem of short-circuiting each pair of electrodes 16E is likely to occur. This solder flash problem occurs especially when the bump electrode 6 on the back side of the module board MCB is made of lead-free solder with a higher melting point than the adhesive 21 attached to the electrode 16E of the chip component 16a-16c. easy. This means that the solder reflow temperature when mounting on the mother board must be high (about 260 degrees), and when mounting on the mother board, it is necessary to mount the chip components in the power module PM. This is because the solder (Pb—Sn) remelts. In addition, when the insulating layer 11 between the pair of electrodes 12E is exposed, the insulation between the pair of electrodes 12E is applied when a desired metal is deposited on the pair of electrodes 12E of the module board MCB by a method such as a staking method. As a result that the desired metal is likely to remain on the exposed surface of the layer 11, there is a problem that a short circuit occurs between the pair of electrodes 16E of the chip component 16a due to the metal residue. In particular, in the case of the 0402 type chip component 16a, since the distance between the pair of electrodes 16E is short, the problem of short circuit failure between the pair of electrodes 16E due to the solder flash and the metal residue described above is likely to occur.
[0051] そこで、本実施の形態 1においては、 0402型のチップ部品 16aの実装領域におい てモジュール基板 MCBの一対の電極 12Eの隣接間に敢えて絶縁層 13を残して!/ヽ る。この場合、チップ部品 16aの実装領域におけるモジュール基板 MCBの一対の電 極 12Eの隣接間に絶縁層 13を残すには、一対の電極 12Eの隣接間隔 D9として、例 えば 0. 175mm以上、その一対の電極 12Eの隣接間に残される絶縁層 13の幅（一 対の電極 12Eが並ぶ方向の寸法） D10として、例えば 0. 1mm以上は加工上必要で ある。この程度の寸法が残されていないと、絶縁層 13のパターンを印刷する際に、絶 縁層 13の印刷状態がかすれてしまう等の問題が生じるからである。寸法 D10の上限 は、チップ部品 16aの長手方向（一対の電極 12Eが並ぶ方向）の長さを上限とすると 、特に限定されないが、例えば 0. 4mm程度である。  Therefore, in the first embodiment, the insulating layer 13 is left behind between the adjacent electrodes 12E of the module substrate MCB in the mounting area of the 0402 type chip component 16a. In this case, in order to leave the insulating layer 13 between the pair of electrodes 12E of the module board MCB in the mounting region of the chip component 16a, the adjacent distance D9 between the pair of electrodes 12E is, for example, 0.175 mm or more. The width of the insulating layer 13 left between the adjacent electrodes 12E (dimension in the direction in which the pair of electrodes 12E are arranged) D10, for example, 0.1 mm or more is necessary for processing. This is because if this size is not left, problems such as fading of the printed state of the insulating layer 13 occur when the pattern of the insulating layer 13 is printed. The upper limit of the dimension D10 is not particularly limited if the length in the longitudinal direction of the chip part 16a (the direction in which the pair of electrodes 12E are arranged) is the upper limit, but it is, for example, about 0.4 mm.
[0052] このように本実施の形態 1においては、 0402型のチップ部品 16aの実装領域にお いてモジュール基板 MCBの一対の電極 12Eの隣接間に、半田にぬれない性質を 持つ絶縁層 13が残されて 、ることにより、その残された絶縁層 13が溶融した半田の 流れを止めるように作用するので、半田フラッシュに起因するチップ部品 16aの一対 の電極 16E間の短絡不良を抑制または防止できる。また、一対の電極 12Eの表面に 所望の金属のめっきを施す際には、一対の電極 12E間に絶縁層 13が残されている ので、所望の金属は絶縁層 11には直接接触せず、絶縁層 13上に残される。この絶 縁層 13上に残された所望の金属の残りは洗浄処理等によりきれいに除去できるので 、本実施の形態 1の場合は、上記のような金属残りに起因するチップ部品 16aの一対 の電極 16E間の短絡不良の問題を抑制または防止できる。 Thus, in the present first embodiment, in the mounting region of the 0402 type chip component 16a, the insulating layer 13 having the property of not being wetted by the solder is provided between the adjacent electrodes 12E of the module substrate MCB. As a result, the remaining insulating layer 13 acts to stop the flow of the melted solder, thereby suppressing or preventing a short circuit failure between the pair of electrodes 16E of the chip component 16a caused by the solder flash. it can. Further, when a desired metal is plated on the surface of the pair of electrodes 12E, the insulating layer 13 is left between the pair of electrodes 12E. Therefore, the desired metal does not directly contact the insulating layer 11 and remains on the insulating layer 13. Since the desired metal residue remaining on the insulating layer 13 can be removed cleanly by a cleaning process or the like, in the case of the first embodiment, the pair of electrodes of the chip component 16a resulting from the metal residue as described above. The problem of short circuit failure between 16E can be suppressed or prevented.
[0053] また、 0402型のチップ部品 16aの配置領域において、絶縁層 13は一対の電極 12 Eの外周一部に重なっても良 、。この場合の絶縁層 13が電極 12Eに重なっても良 ヽ 寸法 (オーバーラップ量）は、例えば 0. 2mm程度までが好ましい。そして、この場合 の一対の電極 12E (この場合の電極 12Eは、絶縁層 13から露出される領域を言う） の上記長さ D6は、例えば 0. 1mm程度とされる。  [0053] In addition, in the arrangement region of the 0402 type chip component 16a, the insulating layer 13 may overlap a part of the outer periphery of the pair of electrodes 12E. In this case, even if the insulating layer 13 overlaps the electrode 12E, the good dimension (overlap amount) is preferably about 0.2 mm, for example. The length D6 of the pair of electrodes 12E in this case (the electrode 12E in this case refers to a region exposed from the insulating layer 13) is, for example, about 0.1 mm.
[0054] また、本実施の形態 1においては、上記と同様の理由力も 0603型および 1005型 のチップ部品 16b, 16cのモジュール基板 MCBの実装領域においても、一対の電 極 12E間に絶縁層 13が残されている。これにより、チップ部品 16b, 16cにおいても 、上記チップ部品 16aと同様の作用により、半田フラッシュに起因するチップ部品 16 b, 16cの一対の電極 16E間の短絡不良や上記金属残りに起因するチップ部品 16b , 16cの一対の電極 16E間の短絡不良を抑制または防止できる。また、 0603型およ び 1005型のチップ部品 16b, 16cについても一対の電極 12Eの外周一部に絶縁層 13の一部が重なっても良い。  [0054] In the first embodiment, the same reasoning force as described above is obtained, and also in the mounting area of the module substrate MCB of the 0603 type and 1005 type chip components 16b and 16c, the insulating layer 13 is provided between the pair of electrodes 12E. Is left. As a result, even in the chip parts 16b and 16c, the chip parts due to the short circuit failure between the pair of electrodes 16E of the chip parts 16b and 16c due to the solder flash and the metal residue due to the same action as the chip part 16a. Short circuit failure between the pair of electrodes 16E of 16b and 16c can be suppressed or prevented. In addition, in the 0603 type and 1005 type chip parts 16b and 16c, part of the insulating layer 13 may overlap with part of the outer periphery of the pair of electrodes 12E.
[0055] 次に、図 12はコンデンサを有するチップ部品（チップコンデンサ） 16 (16a— 16c) の図 10の X2-X2線の断面図の一例を示している。コンデンサを有するチップ部品 1 6は、一対の電極 16Eと、これに電気的に接続され互いに対向するように配置された 複数の内部電極 16IEと、複数の内部電極 16IEの対向面間に形成された誘電体 16 Dとを有している。一対の電極 16Eは、例えば銀力もなる下地電極の表面に、例えば ニッケルからなるめっき層と、例えば錫力もなるめっき層とを順に施した構成を有して いる。内部電極 16IEは、例えばパラジウム（Pd)、銅またはニッケル力 なる。また、 誘電体 16Dは、例えば酸化チタン、ジルコン酸カルシウムまたはチタン酸バリウムか らなる。コンデンサを有するチップ部品 16のうち、 0402型のチップ部品 16aの定格 電圧は、例えば 16V程度、容量値範囲は、例えば 2— 6pF、 0603型のチップ部品 1 6bの定格電圧は、例えば 25V、容量値範囲は、例えば 0. 5— 100pF、 1005型の チップ部品 16cの定格電圧は、例えば 50V、容量値範囲は、例えば 0. 5— lOOOpF である。 Next, FIG. 12 shows an example of a cross-sectional view taken along line X2-X2 of FIG. 10 of a chip component (chip capacitor) 16 (16a-16c) having a capacitor. A chip component 16 having a capacitor is formed between a pair of electrodes 16E, a plurality of internal electrodes 16IE electrically connected to and opposed to each other, and a facing surface of the plurality of internal electrodes 16IE. And a dielectric 16D. The pair of electrodes 16E has a configuration in which, for example, a plating layer made of nickel, for example, and a plating layer also made of tin force, for example, are formed on the surface of the base electrode also having silver strength. The internal electrode 16IE is made of, for example, palladium (Pd), copper, or nickel. The dielectric 16D is made of, for example, titanium oxide, calcium zirconate or barium titanate. Of the chip parts 16 having capacitors, the rated voltage of the 0402 type chip part 16a is, for example, about 16V, the capacitance value range is, for example, 2-6pF, and the rated voltage of the 0603 type chip part 16b is, for example, 25V, capacity For example, the value range is 0.5-100 pF, 1005 type The rated voltage of the chip component 16c is, for example, 50V, and the capacitance value range is, for example, 0.5-lOOOOpF.
[0056] 次に、図 13は抵抗を有するチップ部品（チップ抵抗） 16 (16a— 16c)の図 10の X2  [0056] Next, FIG. 13 shows a chip component having resistance (chip resistance) 16 (16a-16c) X2 in FIG.
X2線の断面図の一例を示している。抵抗を有するチップ部品 16は、基板 16Bと、 その長手方向両端に形成された一対の電極 16Eと、その一対の電極 16Eの各々に 電気的に接続された内部電極 16IEと、各々の内部電極 16IEの間に電気的に接続 された抵抗体 16Rと、抵抗体 16Rおよび内部電極 16IEを保護する保護膜 16Pとを 有している。基板 16Bは、例えばアルミナ等力 なる。電極 16Eの構成は、上記図 12 で説明したのとほぼ同じである。内部電極 16IEは、特殊なメタルフィルムで形成され ている。抵抗体 16Rは、酸化ルテニウム (RuO)系材料力もなる。保護膜 16Pは、例 えば樹脂からなる。抵抗を有するチップ部品 16のうち、 0402型のチップ部品 16aの 定格電力は、例えば 0. 03W程度、 0603型のチップ部品 16bの定格電力は、例え ば 0. 05W、 1005型のチップ部品 16cの定格電力は、例えば 0. 063Wである。  An example of a sectional view taken along line X2 is shown. The chip component 16 having resistance includes a substrate 16B, a pair of electrodes 16E formed at both ends in the longitudinal direction, an internal electrode 16IE electrically connected to each of the pair of electrodes 16E, and each internal electrode 16IE. And a protective film 16P that protects the resistor 16R and the internal electrode 16IE. The substrate 16B is made of alumina, for example. The configuration of the electrode 16E is almost the same as that described in FIG. The internal electrode 16IE is made of a special metal film. The resistor 16R also has a ruthenium oxide (RuO) material strength. The protective film 16P is made of resin, for example. Of the chip parts 16 having resistance, the rated power of the 0402 type chip part 16a is, for example, about 0.03W, and the rated power of the 0603 type chip part 16b is, for example, 0.05W, 1005 type chip part 16c. The rated power is, for example, 0.063W.
[0057] 次に、図 14はインダクタを有するチップ部品 16 (16a— 16c)の図 10の X2— X2線 の部分破断断面図の一例を示している。インダクタを有するチップ部品 16は、素体 1 6Aと、その長手方向両端に形成された一対の電極 16Eと、その一対の電極 16Eの 各々に電気的に接続され素体 16Aの外周に巻き付かれたコイル用導体 16Lと、コィ ル用導体 16Lを被覆する外装榭脂 16Dとを有している。  Next, FIG. 14 shows an example of a partially broken cross-sectional view of the chip component 16 (16a-16c) having an inductor, taken along line X2-X2 in FIG. The chip component 16 having an inductor is wound around the outer periphery of the element body 16A, electrically connected to the element body 16A, a pair of electrodes 16E formed at both ends in the longitudinal direction, and the pair of electrodes 16E. And a coil conductor 16L and an outer resin 16D covering the coil conductor 16L.
[0058] ところで、パワーモジュール PMの小型化だけを考慮すれば、全て 0402型のチップ 部品 16aを使用することが好ましい。しかし、本発明者の検討によれば、パワーモジュ ール PMの全体回路内のチップ部品 16の組み込み箇所の中には、 0402型のチッ プ部品 16aを用いると高周波特性の効率に悪影響を及ぼす等、 0402型のチップ部 品 16aを使用することが不適格な箇所があり、全て 0402型にすることはできないし、 また、ただ単純に 0402型のチップ部品 16aを用いると問題が生じることを見出した。 そこで、本実施の形態 1では、パワーモジュール PMの回路のチップ部品 16の組み 込み箇所に応じて型（寸法)の異なるチップ部品 16を使用するようにした。これにより 、パワーモジュール PMの高周波特性の効率に悪影響を及ぼすことなぐパワーモジ ユール PMの小型化を実現することができる。この具体例を図 15および図 16に示す [0059] 図 15は上記パワーモジュール PMの高周波電力増幅回路の回路図の一例を示し 、図 16は図 15の回路図中のチップ部品 16を素子レベルの図記号で示した回路図 の一例を示している。実線は RF信号配線、破線は電源配線、二点鎖線は制御信号 配線を示している。電源配線には、高電位側の電源配線と、低電位側の電源配線（ 基準電位または接地電位供給用の配線)と、その他にバイアス配線も含む。制御信 号配線には、バンド Zモード切換スィッチ信号配線等の種々の制御信号配線がある By the way, considering only the miniaturization of the power module PM, it is preferable to use the 0402 type chip component 16a. However, according to the study of the present inventor, the use of the 0402 type chip component 16a in the installation location of the chip component 16 in the entire circuit of the power module PM adversely affects the efficiency of the high frequency characteristics. There are places where it is inappropriate to use the 0402 type chip part 16a, and it is not possible to make it all 0402 type. Also, simply using the 0402 type chip part 16a may cause problems. I found it. Therefore, in the first embodiment, the chip parts 16 having different types (dimensions) are used in accordance with the assembling locations of the chip parts 16 of the circuit of the power module PM. This makes it possible to reduce the size of the power module PM without adversely affecting the efficiency of the high frequency characteristics of the power module PM. Specific examples are shown in Figs. 15 and 16. FIG. 15 shows an example of a circuit diagram of the high frequency power amplifier circuit of the power module PM. FIG. 16 shows an example of a circuit diagram in which the chip component 16 in the circuit diagram of FIG. Show. The solid line indicates the RF signal wiring, the broken line indicates the power supply wiring, and the two-dot chain line indicates the control signal wiring. The power supply wiring includes a high-potential-side power supply wiring, a low-potential-side power supply wiring (a wiring for supplying a reference potential or a ground potential), and a bias wiring. There are various types of control signal wiring such as band Z mode switching switch signal wiring.
[0060] 符号 Ta3— Ta7, Tb3— Tb7はパワーモジュール PMの端子を示している。端子 T al— Ta7は、 GSM850および GSM900用の増幅系の端子を示し、端子 Tbl— Tb 7は、 DCS1800および DCS1900用の増幅系の端子を示している。また、符号 Pal 一 Pa7, Pbl— Pb7, Pel— Pc3は半導体チップ 15の上記パッド Pを示している。 [0060] Reference numerals Ta3-Ta7, Tb3-Tb7 denote terminals of the power module PM. The terminal Tal—Ta7 indicates an amplification system terminal for GSM850 and GSM900, and the terminal Tbl—Tb7 indicates an amplification system terminal for DCS1800 and DCS1900. The symbols Pal 1 Pa 7, Pbl—Pb 7, Pel—Pc 3 indicate the pads P of the semiconductor chip 15.
[0061] 図 15では図面を見易くするために 0402型のチップ部品 16aに梨地のハッチングを 付した。また、図 16では図面を見易くするために 0402型のチップ部品 16aの素子記 号を四角で取り囲むように示した。 0402型のチップ部品 16aは、主に印加される電 圧（あるいは流れる電流）が 0603型や 1005型のチップ部品 16b, 16cに印加される 電圧 (あるいは流れる電流)よりも小さい箇所に使用されている。ここでは、コンデンサ CGI, Rl, R3, R5等が 0402型のチップ部品 16aに形成されている場合が例示さ れている。また、フェライトビーズ FBI, FB2、コンデンサ CA1— CA3, CB2, CB3、 コンデンサ CG2— CG5, CP2— CP5、コンデンサ CG6等は 0603型のチップ部品 1 6bに形成され、インダクタ LG1, LP1等は 1005型のチップ部品 16cに形成されてい る場合が例示されている。  In FIG. 15, a matte hatching is added to the 0402 type chip part 16a for easy understanding of the drawing. Further, in FIG. 16, the element symbols of the 0402 type chip part 16a are shown as being surrounded by a square in order to make the drawing easy to see. The 0402 type chip component 16a is mainly used in places where the applied voltage (or flowing current) is smaller than the voltage (or flowing current) applied to the 0603 or 1005 type chip components 16b and 16c. Yes. Here, the case where capacitors CGI, Rl, R3, R5, etc. are formed on the 0402 type chip component 16a is illustrated. Ferrite beads FBI, FB2, capacitors CA1-CA3, CB2, CB3, capacitors CG2-CG5, CP2-CP5, capacitor CG6, etc. are formed on 0603 type chip parts 16b, and inductors LG1, LP1, etc. are 1005 type The case where it is formed on the chip part 16c is illustrated.
[0062] コンデンサ CG1は、微弱な RF信号の入力部と 1段目の増幅回路部 2A1のトランジ スタとのインピーダンス整合を行う RF入力部の整合回路用のコンデンサであり、パヮ 一モジュール PMの入力端子 Talと、初段の増幅回路部 2A1の入力に電気的に接 続されるパッド Palとを電気的に接続する RF信号配線と、接地電位との間に電気的 に接続されて 、る。この整合が合わな 、と入力信号に反射が起こり効率を低下させる 。このコンデンサ CG1に流れる電流は、例えば 20— 30mAで、印加される電圧は、 例えば ov (ほとんど印加されな 、)である。 [0062] Capacitor CG1 is a capacitor for the matching circuit of the RF input section that performs impedance matching between the weak RF signal input section and the first stage amplifier circuit section 2A1 transistor. It is electrically connected between the RF signal wiring that electrically connects the terminal Tal and the pad Pal that is electrically connected to the input of the first stage amplifier circuit section 2A1, and the ground potential. If this matching is not achieved, the input signal is reflected and the efficiency is lowered. The current that flows in this capacitor CG1 is, for example, 20-30mA, and the applied voltage is For example, ov (which is hardly applied).
[0063] 抵抗 R1は、 RF出力の変動量を決めるバイアス抵抗であり、ノッド Pelと接地電位と の間に電気的に接続されている。この抵抗 R1に流れる電流は、例えば 0. 3mAで、 印加される電圧は、例えば 1. 55Vである。抵抗 R3は、 RF出力を出力し始めるボイ ントを決めるバイアス抵抗であり、ノッド Pc2と接地電位との間に電気的に接続されて いる。この抵抗 R3に流れる電流は、例えば 0. 27mAで、印加される電圧は、例えば 1. 39Vである。抵抗 R5は、コンデンサ CG6とともに検波回路を構成するチップ部品 16であり、コンデンサ CG6でピックアップした RF信号の反射波を相殺し、必要な進 行波のみをピックアップする機能を有しており、パッド Pc3とコンデンサ CG6とを電気 的に接続する配線と接地電位との間に電気的に接続されて ヽる。この抵抗 R5に流 れる電流は、例えば 20— 30mAで、印加される電圧は、例えば OV (ほとんど印加さ れない）である。また、コンデンサ CG6に流れる電流は、例えば 1. 1Aで、印加される 電圧は、例えば 3. 5Vである。  The resistor R1 is a bias resistor that determines the amount of fluctuation of the RF output, and is electrically connected between the nod Pel and the ground potential. The current flowing through the resistor R1 is, for example, 0.3 mA, and the applied voltage is, for example, 1.55V. Resistor R3 is a bias resistor that determines the point at which RF output begins to be output, and is electrically connected between node Pc2 and the ground potential. The current flowing through the resistor R3 is, for example, 0.27 mA, and the applied voltage is, for example, 1.39V. Resistor R5 is a chip component 16 that forms a detection circuit together with capacitor CG6, and has the function of canceling the reflected wave of the RF signal picked up by capacitor CG6 and picking up only the necessary traveling wave, pad Pc3 And the capacitor CG6 are electrically connected between the wiring and the ground potential. The current flowing through the resistor R5 is, for example, 20-30 mA, and the applied voltage is, for example, OV (almost not applied). The current flowing through the capacitor CG6 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
[0064] フェライトビーズ FBI, FB2、コンデンサ CA1は、 1段目の電源回路であり、 RFフィ ルタとして発振防止の役割を持つ他、 RF回路力ゝらの RF信号の漏れによって電源 ( 直流 (DC) )が誤動作しないようにする役割を持っている。このフェライトビーズ FBI, FB2、コンデンサ CA1に流れる電流は、例えば 0. 11Aで、印加される電圧は、例え ば 3. 5Vである。  [0064] Ferrite beads FBI, FB2, and capacitor CA1 are the first-stage power supply circuit, which plays a role of preventing oscillation as an RF filter, and the power supply (direct current (DC )) Has a role to prevent malfunction. The current flowing through the ferrite beads FBI, FB2 and capacitor CA1 is, for example, 0.11A, and the applied voltage is, for example, 3.5V.
[0065] コンデンサ CA2, CB2は、 2段目の電源回路であり、役割は初段の電源回路と同じ である。コンデンサ CA2, CB2とモジュール基板 MCB上のライン（配線 12)とによつ て RFフィルタを形成している。このコンデンサ CA2に流れる電流は、例えば 0. 3Aで 、印加される電圧は、例えば 3. 5Vである。  Capacitors CA2 and CB2 are the second-stage power supply circuit, and their roles are the same as those of the first-stage power supply circuit. RF filters are formed by the capacitors CA2 and CB2 and the line (wiring 12) on the module board MCB. The current flowing through the capacitor CA2 is, for example, 0.3A, and the applied voltage is, for example, 3.5V.
[0066] コンデンサ CA3, CB3、インダクタ LG1, LP1は、 3段目の電源回路であり、 RFフィ ルタとして発振防止の役割を持っている。このコンデンサ CA3, CB3、インダクタ LG 1, LP1に流れる電流は、例えば 1. 1Aで、印加される電圧は、例えば 3. 5Vである。  [0066] Capacitors CA3 and CB3 and inductors LG1 and LP1 are the third-stage power supply circuit, and function as an RF filter to prevent oscillation. The current flowing through the capacitors CA3 and CB3 and the inductors LG1 and LP1 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
[0067] コンデンサ CG2— CG5, CP2— CP5は、出力部と 3段目の増幅回路部 2A3, 2B3 のトランジスタとのインピーダンス整合を行う RF出力部の整合回路用のコンデンサで ある。 RF信号出力が大きぐインピーダンスの差が大きいため部品を多用している。 このコンデンサ CG2— CG5, CP2— CP5に流れる電流は、例えば 1. 1Aで、印加さ れる電圧は、例えば 3. 5Vである。 Capacitors CG2—CG5, CP2—CP5 are capacitors for matching circuits in the RF output section that perform impedance matching between the output section and the transistors in the third-stage amplifier circuit sections 2A3, 2B3. Since the RF signal output is large and the impedance difference is large, many parts are used. The current flowing through the capacitors CG2-CG5, CP2-CP5 is 1.1 A, for example, and the applied voltage is 3.5 V, for example.
[0068] (実施の形態 2)  [Embodiment 2]
図 17は本実施の形態 2のパワーモジュール PMのモジュール基板 MCBの被部品 実装面であってチップ部品 16 ( 16a)の実装領域の拡大平面図、図 18は図 17のモ ジュール基板 MCBにチップ部品 16 (16a)を実装した状態を示す拡大平面図、図 1 9は図 18の X3— X3線の断面図、図 20は図 19の一対の電極 12E間のモジュール基 板 MCBの要部拡大断面図をそれぞれ示して ヽる。  FIG. 17 is an enlarged plan view of the mounting area of the module substrate MCB of the power module PM according to the second embodiment and is mounted on the chip component 16 (16a), and FIG. 18 is a chip on the module substrate MCB of FIG. Fig. 19 is a cross-sectional view taken along line X3-X3 in Fig. 18, and Fig. 20 is an enlarged view of the main part of the module board MCB between the pair of electrodes 12E in Fig. 19. Each cross-sectional view is shown.
[0069] 前記実施の形態 1では、一対の電極 12E間に絶縁層 13を残さなければならない分 、一対の電極 12Eの間隔の縮小を阻害することになる。特に 0402型よりもさらに小さ なチップ部品 16を実装する場合は問題になる。そこで、本実施の形態 2では、 0402 型のチップ部品 16aまたはそれよりも小さいチップ部品 16の実装領域の一対の電極 12Eの間に絶縁層 13を残さず、絶縁層 13に一対の電極 12Eと一対の電極 12Eの 隣接間とを含むような大きな開口部 20を形成した。この場合、一対の電極 12Eの間 に絶縁層 13を残さなくて済むので、一対の電極 12Eの隣接間を狭くすることができる 。したがって、 0402型よりもさらに小さいチップ部品 16の実装も可能となる。しかし、 前記したように一対の電極 12E間に絶縁層 13を残さないと半田フラッシュや金属残 りに起因して一対の電極 12E間で短絡不良が発生する。そこで、本実施の形態 2で は、 0402型のチップ部品 16aまたはそれよりも小さいチップ部品 16の実装領域の開 口部 20力も露出する一対の電極 12Eの間の絶縁層 11に、平面で見ると一対の電極 12Eが並ぶ方向に対して直交する方向に延び、断面で見るとモジュール基板 MCの 厚さ方向に窪む複数列の溝 25を形成した。これにより、溝 25を設けない場合に比べ て一対の電極 12E間の距離を長くすることができるので、上記半田フラッシュや金属 残りに起因する一対の電極 12E, 16E間の短絡不良を抑制または防止できる。  [0069] In the first embodiment, since the insulating layer 13 must be left between the pair of electrodes 12E, reduction of the distance between the pair of electrodes 12E is hindered. This is particularly a problem when chip components 16 smaller than 0402 type are mounted. Therefore, in the second embodiment, the insulating layer 13 is not left between the pair of electrodes 12E in the mounting region of the 0402 type chip component 16a or the smaller chip component 16 and the pair of electrodes 12E A large opening 20 was formed so as to include the space between the pair of electrodes 12E. In this case, since it is not necessary to leave the insulating layer 13 between the pair of electrodes 12E, it is possible to narrow the space between the pair of electrodes 12E. Therefore, it is possible to mount a chip component 16 smaller than the 0402 type. However, as described above, if the insulating layer 13 is not left between the pair of electrodes 12E, a short circuit failure occurs between the pair of electrodes 12E due to solder flash or metal residue. Therefore, in the second embodiment, the opening portion of the mounting area of the 0402 type chip component 16a or the chip component 16 smaller than that, and the insulating layer 11 between the pair of electrodes 12E where the force is exposed are viewed in a plane. And a plurality of grooves 25 extending in a direction perpendicular to the direction in which the pair of electrodes 12E are arranged and recessed in the thickness direction of the module substrate MC when viewed in cross section. As a result, the distance between the pair of electrodes 12E can be increased compared to the case where the groove 25 is not provided, so that the short-circuit failure between the pair of electrodes 12E and 16E due to the solder flash or the metal residue is suppressed or prevented. it can.
[0070] (実施の形態 3)  [Embodiment 3]
図 21は本実施の形態 3のパワーモジュール PMのモジュール基板 MCBの被部品 実装面であってチップ部品 16 ( 16a)の実装領域の拡大平面図、図 22は図 21のモ ジュール基板 MCBにチップ部品 16 (16a)を実装した状態を示す拡大平面図、図 2 3は図 22の X4— X4線の断面図、図 24は図 23の一対の電極 12E間のモジュール基 板 MCBの要部拡大断面図をそれぞれ示して ヽる。 FIG. 21 is a mounting surface of the module substrate MCB of the power module PM according to the third embodiment, and is an enlarged plan view of the mounting region of the chip component 16 (16a), and FIG. 22 is a chip on the module substrate MCB of FIG. Fig. 2 is an enlarged plan view showing the part 16 (16a) mounted 3 is a cross-sectional view taken along the line X4-X4 in FIG. 22, and FIG. 24 is an enlarged cross-sectional view of the main part of the module board MCB between the pair of electrodes 12E in FIG.
[0071] 本実施の形態 3では、 0402型のチップ部品 16aまたはそれよりも小さいチップ部品 16の実装領域の開口部 20から露出する一対の電極 12Eの間の絶縁層 11に形成さ れた溝 25〖こ、上記絶縁層 13が埋め込まれている。これ〖こより、一対の電極 12E間に 、半田にぬれない性質を持つ絶縁層 13が残されるので半田フラッシュに起因する一 対の電極 12E, 16E間の短絡不良を抑制または防止できる。また、上記のように一対 の電極 12Eの表面に所望の金属をめつき法等により被着する際に、一対の電極 12E の間の溝 25に絶縁層 13が埋め込まれているので、上記金属めつきが溝 25の形成 箇所の絶縁層 11に直接接しないようにできる。この結果、前記実施の形態 1で説明 したのと同様に、金属残りに起因する一対の電極 12E間の短絡不良を抑制または防 止できる。  In the third embodiment, the groove formed in the insulating layer 11 between the pair of electrodes 12E exposed from the opening 20 in the mounting region of the 0402 type chip component 16a or the smaller chip component 16 is provided. The insulating layer 13 is embedded at 25 mm. Thus, since the insulating layer 13 having the property of not being wetted by the solder is left between the pair of electrodes 12E, a short circuit failure between the pair of electrodes 12E and 16E due to the solder flash can be suppressed or prevented. In addition, when the desired metal is deposited on the surface of the pair of electrodes 12E by a method such as the above, the insulating layer 13 is embedded in the groove 25 between the pair of electrodes 12E. It is possible to prevent direct contact with the insulating layer 11 where the groove 25 is formed. As a result, as described in the first embodiment, it is possible to suppress or prevent a short circuit failure between the pair of electrodes 12E due to the metal residue.
[0072] (実施の形態 4)  [Embodiment 4]
図 25は本実施の形態 4のパワーモジュール PMのモジュール基板 MCBの被部品 実装面であってチップ部品 16 (16a)の実装領域の拡大平面図、図 26は図 25のモ ジュール基板 MCBにチップ部品 16 (16a)を実装した状態を示す拡大平面図、図 2 7は図 26の X5— X5線の断面図、図 28は図 26の X6— X6線の断面図をそれぞれ示 している。なお、図 26では図面を見易くするためにチップ部品 16を透力して示してい る。  FIG. 25 is a mounting surface of the module substrate MCB of the power module PM according to the fourth embodiment, and is an enlarged plan view of the mounting region of the chip component 16 (16a). FIG. 26 is a chip on the module substrate MCB of FIG. FIG. 27 is a cross-sectional view taken along line X5-X5 in FIG. 26, and FIG. 28 is a cross-sectional view taken along line X6-X6 in FIG. 26, respectively, showing a state where the component 16 (16a) is mounted. Note that in FIG. 26, the chip component 16 is shown in a transparent manner for easy viewing of the drawing.
[0073] 本実施の形態 4では、 0402型のチップ部品 16aまたはそれよりも小さいチップ部品 16の実装領域の一対の電極 12Eの露出形状力 一対の電極 12Eの各々が露出さ れる開口部 20a, 20bの開口形状により規定されている。モジュール基板 MCBの一 対の電極 12Eは、開口部 20a, 20bから露出される部分を通じてチップ部品 16の一 対の電極 16Eと電気的に接続されるようになっている。一方の電極 12Eを露出させる 開口部 20aは、例えば平面凹状とされており、その開口部 20aから露出される電極 1 2Eの露出形状も平面凹状とされている。他方の電極 12Eを露出させる開口部 20bは 、例えば平面凸状とされており、その開口部 20bから露出される電極 12Eの露出形 状も平面凸状とされて 、る。一対の電極 12Eの!、ずれにお 、ても一部に絶縁層 13 の一部が被さっている。 In the present fourth embodiment, the exposed shape force of the pair of electrodes 12E in the mounting region of the 0402 type chip component 16a or the chip component 16 smaller than that is the opening 20a from which each of the pair of electrodes 12E is exposed. It is defined by the opening shape of 20b. The pair of electrodes 12E of the module board MCB is electrically connected to the pair of electrodes 16E of the chip component 16 through the portions exposed from the openings 20a and 20b. The opening 20a that exposes one electrode 12E is, for example, a flat concave shape, and the exposed shape of the electrode 12E exposed from the opening 20a is also a flat concave shape. The opening 20b that exposes the other electrode 12E is, for example, a planar convex shape, and the exposed shape of the electrode 12E exposed from the opening 20b is also a planar convex shape. The pair of electrodes 12E! A part of is covered.
[0074] 本実施の形態 4によれば、一対の電極 12Eの隣接間隔 D9が、前記実施の形態 1と 同じかそれよりも小さい場合であっても、一対の電極 12Eの隣接間に残される絶縁層 13の幅 D20を隣接間隔 D9よりも大きくとることができる。すなわち、一対の電極 12E の隣接間隔 D9が前記実施の形態 1と同じかそれよりも小さい場合であっても、一対 の電極 12E間に絶縁層 13を容易に形成することができる。したがって、 0402型また はそれよりも小さいチップ部品 16を実装する場合でも、前記実施の形態 1で説明した のと同様の理由から、上記半田フラッシュや金属残りに起因するチップ部品 16の一 対の電極 16E間の短絡不良を抑制または防止できる。  [0074] According to the fourth embodiment, even when the distance D9 between the pair of electrodes 12E is the same as or smaller than that of the first embodiment, it is left between the pair of electrodes 12E. The width D20 of the insulating layer 13 can be made larger than the adjacent interval D9. That is, even when the adjacent distance D9 between the pair of electrodes 12E is the same as or smaller than that of the first embodiment, the insulating layer 13 can be easily formed between the pair of electrodes 12E. Therefore, even when the 0402 type or smaller chip component 16 is mounted, a pair of chip components 16 caused by the solder flash and the metal residue is used for the same reason as described in the first embodiment. Short circuit failure between the electrodes 16E can be suppressed or prevented.
[0075] (実施の形態 5)  [0075] (Embodiment 5)
図 29は本実施の形態 5のパワーモジュール PMのモジュール基板 MCBの被部品 実装面であってチップ部品 16 (16a)の実装領域の拡大平面図、図 30は図 29のモ ジュール基板 MCBにチップ部品 16 (16a)を実装した状態を示す拡大平面図、図 3 1は図 30の X7— X7線の断面図、図 32は図 30の X8— X8線の断面図をそれぞれ示 している。なお、図 30では図面を見易くするためにチップ部品 16を透力して示してい る。  FIG. 29 is a mounting surface of the module substrate MCB of the power module PM according to the fifth embodiment, and is an enlarged plan view of the mounting area of the chip component 16 (16a). FIG. 30 is a chip on the module substrate MCB of FIG. FIG. 31 is a cross-sectional view taken along line X7—X7 in FIG. 30, and FIG. 32 is a cross-sectional view taken along line X8—X8 in FIG. Note that in FIG. 30, the chip component 16 is shown in a transparent manner for easy viewing of the drawing.
[0076] 本実施の形態 5では、 0402型のチップ部品 16aよりも小さいチップ部品 16の実装 領域の一対の電極 12Eの隣接間隔 D21がそのチップ部品 16の長手方向長さ D22 と等しくなつている。ただし、一対の電極 12E間には、絶縁層 13が前記実施の携帯 1 で説明した幅 D10を確保した状態で残されている。一対の電極 12Eの各々の対向 辺の中央には、一対の電極 12Eの隣接中央に向かって延びる凸状部 12E1が形成 されている。この凸状部 12E1は、チップ部品 16を実装した場合に、チップ部品 16の 電極 16Eへの半田の被着を促進させるための機能を有している。これにより、 0402 型よりも小さいチップ部品 16と一対の電極 12Eとの電気的な接続性を損なうことなく 、一対の電極 12E間に絶縁層 13を残すことができる。したがって、 0402型よりも小さ いチップ部品 16を実装する場合でも、前記実施の形態 1で説明したのと同様の理由 から、上記半田フラッシュや金属残りに起因するチップ部品 16の一対の電極 16E間 の短絡不良を抑制または防止できる。 [0077] (実施の形態 6) In the fifth embodiment, the adjacent distance D21 between the pair of electrodes 12E in the mounting area of the chip component 16 smaller than the 0402 type chip component 16a is equal to the longitudinal length D22 of the chip component 16. . However, the insulating layer 13 is left between the pair of electrodes 12E in a state in which the width D10 described in the first embodiment 1 is secured. A convex portion 12E1 extending toward the adjacent center of the pair of electrodes 12E is formed in the center of each of the opposing sides of the pair of electrodes 12E. The convex portion 12E1 has a function for promoting the adhesion of solder to the electrode 16E of the chip component 16 when the chip component 16 is mounted. Accordingly, the insulating layer 13 can be left between the pair of electrodes 12E without impairing the electrical connectivity between the chip component 16 smaller than the 0402 type and the pair of electrodes 12E. Therefore, even when the chip component 16 smaller than the 0402 type is mounted, for the same reason as described in the first embodiment, between the pair of electrodes 16E of the chip component 16 due to the solder flash and the metal residue. Can prevent or prevent short circuit defects. [0077] (Embodiment 6)
本実施の形態 6では、前記実施の形態 1一 5の電子装置の製造工程および実装ェ 程の一例を図 33のフロー図に沿って説明する。  In the sixth embodiment, an example of the manufacturing process and mounting process of the electronic device of the first to fifteenth embodiments will be described with reference to the flowchart of FIG.
[0078] 最初に、図 33のステップ 1に示すように、多層セラミック基板を準備する。この多層 セラミック基板には、複数のモジュール基板 MCBの形成領域が配置されている。こ の多層セラミック基板の表層の電極 12Eおよび絶縁層 13は、次のように形成する。  First, as shown in Step 1 of FIG. 33, a multilayer ceramic substrate is prepared. On this multilayer ceramic substrate, a plurality of module substrate MCB formation regions are arranged. The surface electrode 12E and the insulating layer 13 of the multilayer ceramic substrate are formed as follows.
[0079] まず、図 34に示すように、多層セラミック基板 MCBmの主面 (第 1面）に上記電極 1 2Eを印刷法により形成する。図 34は製造工程中の多層セラミック基板 MCBmの要 部拡大断面図である。続いて、図 35に示すように、上記絶縁層 13の形成用の印刷 マスク 30を用意する。図 35は印刷マスク 30の要部断面図である。印刷マスク 30は、 例えば金属薄板力 なり、その所望の箇所には主裏面を貫通する開口部 30aが形成 されている。続いて、図 36に示すように、印刷マスク 30を多層セラミック基板 MCBm の主面に位置合わせした状態で重ねる。図 36は多層セラミック基板 MCBmと印刷マ スク 30とを重ね合わせた状態の要部断面図である。  First, as shown in FIG. 34, the electrode 12E is formed on the main surface (first surface) of the multilayer ceramic substrate MCBm by a printing method. FIG. 34 is an enlarged cross-sectional view of the main part of the multilayer ceramic substrate MCBm during the manufacturing process. Subsequently, as shown in FIG. 35, a printing mask 30 for forming the insulating layer 13 is prepared. FIG. 35 is a cross-sectional view of the main part of the printing mask 30. The printing mask 30 has, for example, a metal thin plate force, and an opening 30a penetrating the main back surface is formed at a desired location. Subsequently, as shown in FIG. 36, the printing mask 30 is overlaid while being aligned with the main surface of the multilayer ceramic substrate MCBm. FIG. 36 is a cross-sectional view of the main part in a state where the multilayer ceramic substrate MCBm and the printing mask 30 are overlaid.
[0080] その後、図 37に示すように、印刷マスク 30上の絶縁材 13Aをスキージ 31により引 き伸ばし、開口部 30aを通じて多層セラミック基板 MCBmの主面に印刷する。これに より、絶縁層 13を形成する。図 37は印刷工程時の多層セラミック基板 MCBmと印刷 マスク 30との要部断面図である。続いて、図 38に示すように、印刷マスク 30を取り外 す。図 38は多層セラミック基板 MCBmの要部断面図である。また、図 39および図 40 は上記一対の電極 12E間の絶縁層 13部分の拡大断面図の一例を示している。図 3 9では、絶縁層 13の側面は多層セラミック基板 MCBmの主面に対してほぼ垂直にな つている。これに対して、図 40に示すように、絶縁層 13の側面が多層セラミック基板 MCBの主面に対して傾斜する場合もある。すなわち、絶縁層 13の側面にテーパが 形成される場合もある。この場合の幅 D10は、相対的に広い下底側の幅であり、それ が前記実施の形態 1で説明したように、 0. 1mm以上とされている。  Then, as shown in FIG. 37, the insulating material 13A on the printing mask 30 is stretched by the squeegee 31, and printed on the main surface of the multilayer ceramic substrate MCBm through the opening 30a. Thereby, the insulating layer 13 is formed. FIG. 37 is a cross-sectional view of the principal parts of the multilayer ceramic substrate MCBm and the printing mask 30 during the printing process. Next, remove the print mask 30 as shown in Figure 38. FIG. 38 is a cross-sectional view of a principal part of the multilayer ceramic substrate MCBm. 39 and 40 show an example of an enlarged sectional view of the insulating layer 13 portion between the pair of electrodes 12E. In FIG. 39, the side surface of the insulating layer 13 is substantially perpendicular to the main surface of the multilayer ceramic substrate MCBm. On the other hand, as shown in FIG. 40, the side surface of the insulating layer 13 may be inclined with respect to the main surface of the multilayer ceramic substrate MCB. That is, a taper may be formed on the side surface of the insulating layer 13. In this case, the width D10 is a relatively wide width on the lower bottom side, which is 0.1 mm or more as described in the first embodiment.
[0081] 次いで、図 33のステップ S2に示すように、多層セラミック基板 MCBmの主面に、例 えば Pb— Sn (PbZSnの割合が 37Z63 (共晶半田））力 なる半田ペースト材を上記 と同様の印刷マスクを用いた方法で印刷する。続いて、半導体チップ 15およびチッ プ部品 16 (16a— 16c)を搭載した後、図 33のステップ S4に示すように、加熱（リフ口 一）処理を施すことにより、図 41に示すように、上記チップ部品 16の一対の電極 16E と多層セラミック基板 MCBmの主面の一対の電極 12Eとを上記半田ペースト (接着 材 21)を介して接続する。図 41はチップ部品実装工程後の多層セラミック基板 MCB mの要部断面図である。この際の加熱温度（リフロー温度）は、上記半田ペーストが 溶融する程度の温度とする。 PbZSnの割合が 37Z63 (共晶半田）の場合は、例え ば 183度程度である。その後、図 33のステップ S5に示すように、洗浄処理を施した 後、ステップ S6に示すように、半導体チップ 15のパッド Pと多層セラミック基板 MCB mの所望の電極 12Eとをワイヤ BWによって電気的に接続する。 Next, as shown in Step S2 of FIG. 33, a solder paste material having a Pb—Sn (PbZSn ratio of 37Z63 (eutectic solder)) force is applied to the main surface of the multilayer ceramic substrate MCBm in the same manner as described above. Printing is performed by using a printing mask. Subsequently, the semiconductor chip 15 and the chip After mounting the chip component 16 (16a-16c), as shown in FIG. 41, a pair of electrodes of the chip component 16 is applied by performing a heating (one riff mouth) process as shown in step S4 of FIG. 16E and the pair of electrodes 12E on the main surface of the multilayer ceramic substrate MCBm are connected via the solder paste (adhesive 21). FIG. 41 is a fragmentary cross-sectional view of the multilayer ceramic substrate MCB m after the chip component mounting process. The heating temperature (reflow temperature) at this time is set to a temperature at which the solder paste is melted. When the ratio of PbZSn is 37Z63 (eutectic solder), for example, it is about 183 degrees. Then, after performing a cleaning process as shown in step S5 of FIG. 33, as shown in step S6, the pad P of the semiconductor chip 15 and the desired electrode 12E of the multilayer ceramic substrate MCB m are electrically connected by the wire BW. Connect to.
[0082] 次いで、図 33のステップ S7に示すように、多層セラミック基板 MCBmの主面の複 数のモジュール基板 MCBの形成領域を一括して覆うように、例えばシリコーン榭脂 または低弾性エポキシ榭脂等力 なる封止部材 8を上記と同様の印刷方式により形 成する。続いて、図 33のステップ S8に示すように、ベータ (加熱）処理を行って封止 部材 8を硬化させる。その後、図 33のステップ S9に示すように、多層セラミック基板 M CBmを個々のモジュール PM毎に切断し、複数のモジュール PMを切り出す（個片 化工程）。その後、図 33のステップ S10, S11〖こ示すよう〖こ、各モジュール PMに対し て電気的特性テストを行ってモジュール PMが完成する。ステップ S8とステップ S9と の間またはステップ S 10とステップ S 11との間に、モジュール基板 MCBの裏面の複 数の電極 (外部接続用電極)の各々に、上記鉛フリー半田カゝらなるバンプ電極 6を接 続する。多層セラミックス基板 MCBmの切断前のステップ S 8とステップ S 9との間に バンプ電極 6を接続する場合は、多層セラミック基板 MCBmの複数のモジュール基 板に一括してバンプ電極 6を接続できるので、工程の簡略ィ匕および製造時間の短縮 が可能である。バンプ電極 6は鉛フリー半田バンプに代えて金 (Au)バンプとしても良 い。さらに、ここでは、バンプ電極 6を接続する場合について説明した力 バンプ電極 6を接続しな 、まま出荷しても良 、 (LGAパッケージ構成の製品）。  Next, as shown in step S7 of FIG. 33, for example, a silicone resin or a low-elastic epoxy resin so as to collectively cover the formation areas of the plurality of module substrates MCB on the main surface of the multilayer ceramic substrate MCBm. The sealing member 8 having equal force is formed by the same printing method as described above. Subsequently, as shown in step S8 of FIG. 33, the sealing member 8 is cured by performing a beta (heating) process. Thereafter, as shown in step S9 of FIG. 33, the multilayer ceramic substrate MCCBm is cut into individual modules PM, and a plurality of modules PM are cut out (individualization step). Thereafter, as shown in steps S10 and S11 in FIG. 33, an electrical characteristic test is performed on each module PM to complete the module PM. Between step S8 and step S9 or between step S10 and step S11, bumps made of the lead-free solder solder are applied to each of the plurality of electrodes (external connection electrodes) on the back surface of the module board MCB. Connect electrode 6. When bump electrode 6 is connected between steps S8 and S9 before cutting multilayer ceramic substrate MCBm, bump electrode 6 can be connected to multiple module substrates on multilayer ceramic substrate MCBm. Process simplification and manufacturing time can be shortened. The bump electrode 6 may be a gold (Au) bump instead of the lead-free solder bump. Furthermore, here, the force described for connecting the bump electrode 6 may be shipped without connecting the bump electrode 6 (product of LGA package configuration).
[0083] 次いで、図 33のステップ S21に示すように、上記マザ一ボード MBを準備した後、ス テツプ S22に示すように、そのマザ一ボード MBの主面の電極に、上記鉛フリー半田 ペーストを上記と同様の印刷マスクを用いた方法で印刷する。続いて、図 33のステツ プ S23に示すように、パワーモジュール PMをマザ一ボード MBの主面上に搭載する 。すなわち、図 42に示すように、パワーモジュール PMのバンプ電極 6と、マザ一ボー ド MBの主面の電極 35とを位置合わせする。図 42はパワーモジュール実装工程時 のマザ一ボード MBの要部断面図である。マザ一ボード MBの電極 35上には、上記 鉛フリー半田力もなる半田ペースト（半田層、迎え半田層） 36が形成されている。この 状態で、図 33のステップ S24に示すように、加熱（リフロー）処理を施すことにより、図 43に示すように、パワーモジュール PMの裏面電極とマザ一ボード MBの電極 35とを バンプ電極 6を介して接続する。図 43はパワーモジュール PMの実装工程後のマザ 一ボード MBの要部断面図である。この際の加熱温度（リフロー温度）は、上記鉛フリ 一からなる半田ペーストが溶融する程度の温度とする。上記のようにバンプ電極 6が 鉛フリー半田とされている場合、その融点が Pb— Sn半田の融点よりも高いので、この マザ一ボード MBへの実装の際の半田リフロー温度は、上記ステップ S4での温度よ りも高温 (例えば約 260度）にしなければならない。このため、マザ一ボードへの実装 の際に、パワーモジュール PM内のチップ部品実装用の半田（Pb— Sn)が再溶融し、 一対の電極 16E間（または一対の電極 12E間）を短絡させる場合がある（半田フラッ シュ)。これに対して、本実施の形態 6では、上記のように、一対の電極 12Eの間に絶 縁層 13が残されていることにより、これが溶融半田に対する障壁として作用するので 、半田フラッシュに起因するチップ部品 16の一対の電極 16E間の短絡不良を抑制ま たは防止できる。なお、図 43の段階のバンプ電極 6には、バンプ電極 6を形成してい た鉛フリー半田または金と、上記半田ペースト 36とが混合されている。上記のように パワーモジュール PMの裏面の電極（外部接続用電極）にバンプ電極 6を接続しな!ヽ 製品（LGAパッケージ）の場合は、パワーモジュール PMの裏面の電極とマザ一ボー ド MBの電極 35とを半田ペースト 36により接続する。その後、図 33のステップ S25, S26に示すように、電気的特性テストを行って 2次実装が完成する。 Next, after preparing the mother board MB as shown in step S21 of FIG. 33, the lead-free solder paste is applied to the electrodes on the main surface of the mother board MB as shown in step S22. Is printed by a method using a print mask similar to the above. Next, the steps in Figure 33 As shown in step S23, the power module PM is mounted on the main surface of the mother board MB. That is, as shown in FIG. 42, the bump electrode 6 of the power module PM and the electrode 35 on the main surface of the mother board MB are aligned. FIG. 42 is a cross-sectional view of the main part of the mother board MB during the power module mounting process. On the electrode 35 of the mother board MB, a solder paste (solder layer, soldering solder layer) 36 having the lead-free soldering force is formed. In this state, as shown in step S24 of FIG. 33, a heating (reflow) process is performed to connect the back electrode of the power module PM and the electrode 35 of the mother board MB to the bump electrode 6 as shown in FIG. Connect through. FIG. 43 is a cross-sectional view of the main part of the mother board MB after the mounting process of the power module PM. The heating temperature (reflow temperature) at this time is set to a temperature at which the solder paste made of lead-free solder is melted. When the bump electrode 6 is made of lead-free solder as described above, the melting point is higher than the melting point of Pb—Sn solder. Therefore, the solder reflow temperature when mounting on this motherboard MB is the above step S4. The temperature must be higher than the temperature at (eg about 260 degrees). For this reason, when mounting on the mother board, the solder (Pb—Sn) for mounting the chip components in the power module PM is remelted, and the pair of electrodes 16E (or the pair of electrodes 12E) are short-circuited. In some cases (solder flash). On the other hand, in Embodiment 6, as described above, the insulating layer 13 is left between the pair of electrodes 12E, and this acts as a barrier against the molten solder. The short circuit failure between the pair of electrodes 16E of the chip component 16 to be performed can be suppressed or prevented. Note that the lead-free solder or gold forming the bump electrode 6 and the solder paste 36 are mixed in the bump electrode 6 in the stage of FIG. As described above, do not connect the bump electrode 6 to the electrode (external connection electrode) on the back of the power module PM! ヽ For the product (LGA package), the electrode on the back of the power module PM and the motherboard MB The electrode 35 is connected to the solder paste 36. After that, as shown in steps S25 and S26 in FIG. 33, an electrical characteristic test is performed to complete the secondary mounting.
[0084] 以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが 、本発明は前記実施の形態に限定されるものではなぐその要旨を逸脱しない範囲 で種々変更可能であることは 、うまでもな!/、。  [0084] While the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention. There's nothing wrong!
[0085] 例えば前記実施の形態では、 GSM850、 GSM900、 GSM1800および GSM19 00の 4つの周波数帯の電波を取り扱うことが可能なフォーバンド方式の携帯電話に 適用した場合について説明した力 これに限定されるものではなぐ例えば GSM90 0および GSM1800の 2つの周波数帯の電波を取り扱うことが可能なデュアルバンド 方式または GSM900、 GSM1800および GSM1900の 3つの周波数帯の電波を取 り扱うことが可能なトリプルバンド方式の携帯電話に適用することもできる。 [0085] For example, in the above embodiment, GSM850, GSM900, GSM1800, and GSM19 The power described when applied to a four-band mobile phone capable of handling radio waves in the four frequency bands of 00. This is not limited to this example. For example, it handles radio waves in the two frequency bands of GSM90 0 and GSM1800. It can also be applied to dual-band mobile phones that can handle radio waves in the three frequency bands of GSM900, GSM1800, and GSM1900.
[0086] 以上の説明では主として本発明者によってなされた発明をその背景となった利用 分野である携帯電話用のパワーモジュールに適用した場合について説明したが、そ れに限定されるものではなぐ例えば通信機能を有する PDA (Personal Digital Assistants)等のような移動体情報処理装置や通信機能を有するパーソナルコンビュ ータ等のような情報処理装置にも適用できる。 In the above description, the case where the invention made mainly by the present inventor is applied to a power module for a mobile phone, which is a field of use behind the invention, has been described. However, the present invention is not limited to this. The present invention can also be applied to mobile information processing devices such as PDAs (Personal Digital Assistants) having a communication function, and information processing devices such as personal computers having a communication function.
産業上の利用可能性  Industrial applicability
[0087] 本発明の電子装置は、例えば携帯電話のような携帯型電子装置の他、通信機能を 有する PDA等のような移動体情報処理装置や通信機能を有するパーソナルコンビュ ータ等のような情報処理装置に利用できる。 [0087] The electronic device of the present invention is, for example, a mobile electronic device such as a mobile phone, a mobile information processing device such as a PDA having a communication function, a personal computer having a communication function, or the like. It can be used for information processing devices.

Claims

請求の範囲 The scope of the claims
[1] 高周波電力増幅回路を有する電子装置であって、  [1] An electronic device having a high-frequency power amplifier circuit,
第 1主面およびその反対側の第 2主面を有する第 1配線基板と、  A first wiring board having a first main surface and a second main surface opposite to the first main surface;
前記第 1配線基板の第 1主面上に実装された、前記高周波電力増幅回路の増幅回 路部を構成する能動素子を含む半導体チップと、  A semiconductor chip including active elements mounted on a first main surface of the first wiring board and constituting an amplification circuit portion of the high-frequency power amplifier circuit;
前記第 1配線基板の第 1主面上に半田を介し実装された、前記高周波電力増幅回 路を構成する 0402型の第 1受動部品と、  A 0402 type first passive component mounted on the first main surface of the first wiring board via solder and constituting the high frequency power amplification circuit;
前記第 1配線基板の第 1主面上に半田を介し実装された、前記高周波電力増幅回 路を構成する、前記 0402型よりも寸法の大きな第 2受動部品と、  A second passive component having a size larger than that of the 0402 type, constituting the high-frequency power amplification circuit, mounted on the first main surface of the first wiring board via solder;
前記第 1配線基板の第 2主面に形成された複数の外部接続用電極とを備え、 前記 0402型の第 1受動部品は、前記高周波電力増幅回路において、前記第 2受 動部品に印加される電圧よりも小さい電圧が印加される箇所に電気的に接続されて A plurality of external connection electrodes formed on the second main surface of the first wiring board, and the 0402 type first passive component is applied to the second passive component in the high-frequency power amplifier circuit. Is electrically connected to a location where a voltage smaller than the
Vヽることを特徴とする電子装置。 An electronic device characterized by V.
[2] 請求項 1記載の電子装置において、前記第 2受動部品は、 1005型、 0603型また はその両方であることを特徴とする電子装置。 2. The electronic apparatus according to claim 1, wherein the second passive component is a 1005 type, a 0603 type, or both.
[3] 請求項 1記載の電子装置において、前記 0402型の第 1受動部品は、前記高周波 電力増幅回路の入力のインピーダンス整合回路用のコンデンサであることを特徴と する電子装置。 3. The electronic device according to claim 1, wherein the 0402 type first passive component is a capacitor for an impedance matching circuit at an input of the high frequency power amplifier circuit.
[4] 請求項 1記載の電子装置において、前記 0402型の第 1受動部品は、前記高周波 電力増幅回路の検波回路用の抵抗であることを特徴とする電子装置。  4. The electronic device according to claim 1, wherein the 0402 type first passive component is a resistor for a detection circuit of the high-frequency power amplifier circuit.
[5] 請求項 1記載の電子装置において、前記 0402型の第 1受動部品は、前記高周波 電力増幅回路の高周波電力を出力し始めるポイントを決める抵抗であることを特徴と する電子装置。  5. The electronic device according to claim 1, wherein the 0402 type first passive component is a resistor that determines a point at which the high-frequency power of the high-frequency power amplifier circuit starts to be output.
[6] 請求項 1記載の電子装置において、前記 0402型の第 1受動部品は、前記高周波 電力増幅回路の高周波出力の変動量を決める抵抗であることを特徴とする電子装置  6. The electronic device according to claim 1, wherein the 0402 type first passive component is a resistor that determines a fluctuation amount of a high frequency output of the high frequency power amplifier circuit.
[7] 請求項 1記載の電子装置において、前記第 1配線基板の最表層に絶縁層が形成さ れ、 前記第 1受動部品および前記第 2受動部品はそれぞれ一対の電極を有し、 前記第 1受動部品および前記第 2受動部品の各々の一対の電極は、前記第 1配線 基板の最表層に形成された絶縁層に開口された開口部から露出される一対の電極 と接続されており、前記第 1配線基板の前記開口部から露出される一対の電極の隣 接間には前記絶縁層が残されていることを特徴とする電子装置。 [7] The electronic device according to claim 1, wherein an insulating layer is formed on an outermost layer of the first wiring board, Each of the first passive component and the second passive component has a pair of electrodes, and each of the pair of electrodes of the first passive component and the second passive component is formed on the outermost layer of the first wiring board. Connected to a pair of electrodes exposed from the opening formed in the insulating layer, and the insulating layer is left between the adjacent electrodes exposed from the opening of the first wiring board. An electronic device characterized by that.
[8] 請求項 7記載の電子装置にお ヽて、前記第 1配線基板の最表層に形成された前記 絶縁層はガラスカゝらなることを特徴とする電子装置。 8. The electronic device according to claim 7, wherein the insulating layer formed on the outermost layer of the first wiring board is made of glass.
[9] 請求項 7記載の電子装置において、前記第 1配線基板の前記開口部から露出され る一対の電極の隣接間に残されている前記絶縁層の幅は 0. 1mm以上であることを 特徴とする電子装置。 [9] In the electronic device according to [7], the width of the insulating layer left between the pair of electrodes exposed from the opening of the first wiring board is 0.1 mm or more. Electronic device characterized.
[10] 請求項 9記載の電子装置において、前記第 1配線基板の前記開口部から露出され る一対の電極の隣接間に残されている前記絶縁層の幅は 0. 4mm以下であることを 特徴とする電子装置。  [10] In the electronic device according to [9], the width of the insulating layer left between the pair of electrodes exposed from the opening of the first wiring board is 0.4 mm or less. Electronic device characterized.
[11] 請求項 7記載の電子装置において、前記複数の外部接続用電極には、鉛を含まな [11] The electronic device according to claim 7, wherein the plurality of external connection electrodes do not contain lead.
V、半田バンプが接続されて 、ることを特徴とする電子装置。 V, an electronic device characterized in that a solder bump is connected.
[12] 請求項 11記載の電子装置において，前記電子装置は主面に配線パターンを有す る第2配線基板に搭載され、 [12] The electronic device according to claim 11, wherein the electronic device is mounted on a second wiring board having a wiring pattern on a main surface,
前記電子装置の外部接続用電極と前記第 2配線基板の配線パターンは、前記半 田バンプを介して電気的に接続されることを特徴とする電子装置。  An electronic device, wherein an external connection electrode of the electronic device and a wiring pattern of the second wiring substrate are electrically connected via the solder bump.
[13] 請求項 1記載の電子装置において，前記電子装置は主面に配線パターンを有する 第 2配線基板に搭載され、 [13] The electronic device according to claim 1, wherein the electronic device is mounted on a second wiring board having a wiring pattern on a main surface,
前記電子装置の外部接続用電極と前記第 2配線基板の配線パターンは、前記配 線パターン上に形成された鉛を含まない半田層を介して電気的に接続されることを 特徴とする前記電子装置。  The external connection electrode of the electronic device and the wiring pattern of the second wiring board are electrically connected through a solder layer not containing lead formed on the wiring pattern. apparatus.
[14] 請求項 11記載の電子装置において、前記鉛を含まない半田バンプは、錫 銅系合 金、錫 銀系合金、錫 亜鉛系合金、錫 ビスマス系合金または錫 アンチモン合金 力 なることを特徴とする電子装置。 [14] The electronic device according to [11], wherein the lead-free solder bump includes a tin-copper alloy, a tin-silver alloy, a tin-zinc alloy, a tin-bismuth alloy, or a tin antimony alloy. An electronic device.
[15] 請求項 1記載の電子装置において、前記高周波電力増幅回路は、複数の周波数 帯の高周波信号に対応可能なマルチバンド方式を採用していることを特徴とする電 子装置。 15. The electronic device according to claim 1, wherein the high frequency power amplifier circuit has a plurality of frequencies. An electronic device that employs a multiband system that can handle high-frequency signals.
[16] 請求項 1記載の電子装置において、前記高周波電力増幅回路は、 850MHz帯、 9 OOMHz帯、 1800MHz帯または 1900MHz帯で動作することを特徴とする電子装 置。  16. The electronic device according to claim 1, wherein the high-frequency power amplifier circuit operates in an 850 MHz band, a 9 OO MHz band, a 1800 MHz band, or a 1900 MHz band.
[17] 高周波電力増幅回路を有する電子装置であって、  [17] An electronic device having a high-frequency power amplifier circuit,
(a)第 1主面およびその反対側の第 2主面を有する配線基板と、  (a) a wiring board having a first main surface and a second main surface opposite to the first main surface;
(b)前記高周波電力増幅回路の増幅回路部を構成する電子部品であって、前記 配線基板の第 1主面上に実装された半導体チップと、  (b) an electronic component constituting an amplifier circuit portion of the high-frequency power amplifier circuit, the semiconductor chip mounted on the first main surface of the wiring board;
(c)前記高周波電力増幅回路を構成する電子部品であって、前記配線基板の第 1 主面上に実装された 0402型の第 1受動部品とを備え、  (c) an electronic component constituting the high-frequency power amplifier circuit, comprising a 0402 type first passive component mounted on the first main surface of the wiring board;
前記第 1受動部品一対の電極は、前記配線基板の最表層に形成された絶縁層に 開口された開口部カゝら露出される一対の電極と接続されており、前記配線基板の前 記開口部から露出される一対の電極の隣接間には前記絶縁層が残されており、前記 配線基板の前記開口部カゝら露出される一対の電極の隣接間に残されている前記絶 縁層の幅は 0. 1mm以上であることを特徴とする電子装置。  The first passive component pair of electrodes is connected to a pair of electrodes exposed from an opening portion opened in an insulating layer formed on the outermost layer of the wiring board, and the opening of the wiring board The insulating layer is left between a pair of electrodes exposed from a portion, and the insulating layer is left between a pair of electrodes exposed from the opening portion of the wiring board. The width of the electronic device is 0.1 mm or more.
[18] 請求項 17記載の電子装置において、前記配線基板の第 2主面の電極には、鉛を 含まな 、半田バンプが接続されて 、ることを特徴とする電子装置。  18. The electronic device according to claim 17, wherein a solder bump containing no lead is connected to the electrode on the second main surface of the wiring board.
[19] 請求項 18記載の電子装置において、前記鉛を含まない半田バンプは、錫 銅系合 金、錫 銀系合金、錫 亜鉛系合金、錫 ビスマス系合金または錫 アンチモン合金 力 なることを特徴とする電子装置。  [19] The electronic device according to [18], wherein the lead-free solder bump includes a tin-copper alloy, a tin-silver alloy, a tin-zinc alloy, a tin-bismuth alloy, or a tin antimony alloy. An electronic device.
[20] 請求項 17記載の電子装置において、前記高周波電力増幅回路は、 850MHz帯、 900MHz帯、 1800MHz帯または 1900MHz帯で動作することを特徴とする電子装 置。  20. The electronic device according to claim 17, wherein the high-frequency power amplifier circuit operates in an 850 MHz band, a 900 MHz band, a 1800 MHz band, or a 1900 MHz band.
[21] 高周波電力増幅回路を有する電子装置の製造方法であって、  [21] A method of manufacturing an electronic device having a high-frequency power amplifier circuit,
(a)第 1主面およびその反対側の第 2主面を有する第 1配線基板を準備する工程と (a) preparing a first wiring board having a first main surface and a second main surface opposite to the first main surface;
(b)前記第 1配線基板の第 1主面上に前記高周波電力増幅回路の増幅回路部を 構成する能動素子を含む半導体チップを実装する工程と (c)前記第 1配線基板の第 1主面上に、前記高周波電力増幅回路を構成する 040 2型の第 1受動部品を半田を用いて実装する工程と (b) mounting a semiconductor chip including an active element constituting an amplifier circuit portion of the high-frequency power amplifier circuit on the first main surface of the first wiring board; (c) mounting a 0402-type first passive component constituting the high-frequency power amplifier circuit on the first main surface of the first wiring board using solder; and
(d)前記第 1配線基板の第 1主面上に、前記高周波電力増幅回路を構成する、前 記 0402型よりも寸法の大きな第 2受動部品を半田を用いて実装する工程とを含み、 前記第 1配線基板の前記第 2主面には複数の外部接続用電極が形成され、 前記複数の外部接続用電極には鉛を含まない半田バンプが接続され、 前記高周波電力増幅回路において、前記第 2受動部品に印加される電圧よりも小 さい電圧が印加される箇所に電気的に接続されていることを特徴とする電子装置の 製造方法。  (d) mounting a second passive component having a size larger than that of the 0402 type on the first main surface of the first wiring board using solder. A plurality of external connection electrodes are formed on the second main surface of the first wiring board, solder bumps not containing lead are connected to the plurality of external connection electrodes, and in the high-frequency power amplifier circuit, A method of manufacturing an electronic device, characterized in that the electronic device is electrically connected to a location where a voltage smaller than the voltage applied to the second passive component is applied.
[22] 請求項 21記載の電子装置の製造方法であって、前記電子装置は主面に配線バタ ーンを有する第 2配線基板に搭載され、  [22] The method of manufacturing an electronic device according to claim 21, wherein the electronic device is mounted on a second wiring board having a wiring pattern on a main surface,
前記電子装置の外部接続用電極と前記第 2配線基板の配線パターンは、前記半 田バンプによって接続されることを特徴とする電子装置の製造方法。  A method for manufacturing an electronic device, wherein an external connection electrode of the electronic device and a wiring pattern of the second wiring substrate are connected by the solder bump.
[23] 請求項 22記載の電子装置の製造方法であって、前記電子装置を前記第 2配線基 板に搭載する際に、前記半田バンプが溶融する温度まで加熱する工程を含むことを 特徴とする電子装置の製造方法。 23. The method of manufacturing an electronic device according to claim 22, further comprising a step of heating the electronic device to a temperature at which the solder bump melts when the electronic device is mounted on the second wiring board. A method for manufacturing an electronic device.
[24] 請求項 21記載の電子装置の製造方法であって、 [24] The method of manufacturing an electronic device according to claim 21,
前記第 1配線基板の最表層にガラスカゝらなる絶縁層が印刷法によって形成され、 前記第 1受動部品および前記第 2受動部品はそれぞれ一対の電極を有し、 前記第 1受動部品および前記第 2受動部品の一対の電極は、前記ガラスからなる 絶縁層に開口された開口部カゝら露出される一対の電極と接続されており、  An insulating layer such as a glass cover is formed on the outermost layer of the first wiring board by a printing method, and each of the first passive component and the second passive component has a pair of electrodes, and the first passive component and the first passive component (2) The pair of electrodes of the passive component is connected to the pair of electrodes exposed from the opening portion opened in the insulating layer made of the glass,
前記第 1配線基板の前記開口部力 露出される一対の電極間には前記絶縁層が 残され、  The insulating layer is left between the pair of electrodes exposed to the opening force of the first wiring board,
前記第 1配線基板の前記開口部から露出される一対の電極間に残されている前記 絶縁層の幅は 0. 1mm以上であることを特徴とする電子装置の製造方法。  The method for manufacturing an electronic device according to claim 1, wherein the width of the insulating layer left between the pair of electrodes exposed from the opening of the first wiring board is 0.1 mm or more.
PCT/JP2004/016324 2004-11-04 2004-11-04 Electronic device and electronic device manufacturing method WO2006048932A1 (en)

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