JP2007149931A - Semiconductor device, and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve reliability and impact resistance of electrical connection of a semiconductor device. <P>SOLUTION: In an RF power module 1 for a mobile phone; a semiconductor chip 2 is flip-chip mounted via solder bumps 5 on the upper surface 3a of a wiring circuit board 3, and a passive component 4 is mounted via the solder 17. Among the solder bumps 5; a first resin 6 formed of an elastic silicone resin is filled, and moreover a second resin 7 formed of an epoxy region having the elasticity higher than that of the first resin 6 is also formed to fix between the side surface of the semiconductor chip 2 and the upper surface 3a of the wiring circuit board 3. The first resin 6 having lower elasticity prevents termination between terminals resulting from volume expansion due to re-fusion of the semiconductor bump 5 during the secondary mounting of the RF power module 1, and the second resin 7 having higher elasticity can improve impact resistance. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device in which a semiconductor chip is connected to a wiring board through solder bumps and a technology effective when applied to the manufacturing technology.

  There is a technique for manufacturing a semiconductor device by face-up bonding a semiconductor chip on a wiring substrate, wire bonding between the semiconductor chip and the wiring substrate, and sealing with a resin.

  Further, there is a technique for manufacturing a semiconductor device by flip-chip connecting a semiconductor chip having solder bumps on a wiring board and filling an underfill between the semiconductor chip and the wiring board.

  In JP-A-8-55938 (Patent Document 1), a semiconductor element (chip) is attached to a circuit board by solder bumps and connected to a wiring layer of the circuit board. The first resin and the second resin having different rates are filled, and the first resin filled in the center portion of the chip in the gap between the chip and the circuit board has a Young's modulus higher than the second resin filled in the peripheral portion of the chip. However, the technology that can fix the chip sufficiently is described.

Japanese Patent Laid-Open No. 2002-208668 (Patent Document 2) discloses a semiconductor chip, a chip component, a module substrate, a solder connection portion that connects the chip component and the board-side terminal of the module substrate, and a semiconductor chip. Sealing formed by a low elastic resin such as an insulating silicone resin or a low elastic epoxy resin, covering the gold wire connecting the board side terminal of the module substrate, the semiconductor chip, the chip component, the solder connection part and the gold wire. The technology which consists of a part and prevents the outflow by remelting of the solder of a solder connection part is described.
JP-A-8-55938 JP 2002-208668 A

  According to the study of the present inventor, the following has been found.

  Mobile communication devices (for example, mobile phones) have become widespread worldwide. In general, a mobile phone includes an antenna that radiates and receives radio waves, a high-frequency power amplifier (RF power module) that amplifies a power-modulated high-frequency signal and supplies the signal to the antenna, and a receiving unit that processes the high-frequency signal received by the antenna , And a control unit that performs these controls, and a battery (battery) that supplies a power supply voltage thereto.

  In recent years, with the miniaturization and thinning of mobile phones, there has been a demand for miniaturization and thinning of RF power modules used therefor.

  When a semiconductor chip is face-up bonded on a wiring board and an RF power module is manufactured by wire bonding the semiconductor chip and the wiring board, the thickness of the RF power module is increased by the height of the wire loop of the bonding wire. In addition, since an area for extending the bonding wire is required, the planar size of the RF power module is increased. For this reason, it becomes disadvantageous for size reduction and thickness reduction of the RF power module.

  Therefore, it is conceivable to connect the semiconductor chip on the wiring board face-down with a lip chip and connect the semiconductor chip to the wiring board via solder bumps. Thereby, compared with the case where a bonding wire is used, RF power module can be reduced in size and thickness.

  When flip-chip mounting a semiconductor chip on a wiring board, it is preferable to provide an underfill resin to protect the solder bumps that are the connection between the semiconductor chip and the wiring board.

  However, at the time of secondary solder reflow for mounting the RF power module on the mounting board on the customer side, not only solder for connecting the RF power module to the mounting board but also solder bumps in the underfill of the RF power module May remelt.

  When the underfill resin is formed of a highly elastic resin, if the solder bump in the underfill of the RF power module is remelted during the solder reflow process of the secondary mounting, the underfill resin made of the highly elastic resin is re-applied to the solder bump. Volume expansion due to melting cannot be absorbed, and solder flash may occur. When solder (here, solder bumps) is re-melted, solder flash means that the melting and expansion pressure causes the interface between the component (here, the semiconductor chip) and the resin (resin), or the interface between the resin and the module substrate (wiring board). The solder is peeled off, and the solder flows into the flash (in a flash form), and the terminals (here, between the solder bumps of the semiconductor chip or between the terminals of the wiring board connected to the solder bumps) are connected by the solder, resulting in a short circuit. This may reduce the reliability of the electrical connection inside the RF power module.

  When the underfill resin is formed of a low elastic resin, even if the solder bumps in the underfill of the RF power module are remelted during the secondary reflow solder reflow process, Since the volume expansion due to remelting can be absorbed, it is possible to prevent a short circuit (solder flash) between the terminals due to the solder expansion. However, when an RF power module or a mobile phone using the RF module is dropped, the impact stress applied to the solder bump cannot be reduced with a soft underfill resin having low elasticity, and between the solder bump and the semiconductor chip, Or a crack etc. may generate | occur | produce between a solder bump and the board | substrate side terminal of a wiring board, and the reliability of electrical connection may fall. For this reason, the resistance (impact resistance) with respect to physical impacts, such as a fall, in RF power module and a mobile telephone using the same will become low.

  An object of the present invention is to provide a technique capable of improving the reliability of electrical connection of a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the resistance of a semiconductor device to physical impact.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention relates to a wiring board, a semiconductor chip mounted on the main surface of the wiring board via a plurality of solder bumps, a first resin filled between the plurality of solder bumps, and the semiconductor chip. A second resin that fixes between the side surface and the main surface of the wiring board; and an elastic modulus of the second resin is larger than an elastic modulus of the first resin.

  In the present invention, a semiconductor chip is mounted on the main surface of the wiring board via a plurality of solder bumps, and a first resin is filled between the plurality of solder bumps. A second resin having a higher elastic modulus than the first resin is formed between the main surface of the wiring board.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The reliability of electrical connection of the semiconductor device can be improved.

  In addition, the resistance of the semiconductor device to physical impact can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view or a perspective view may be hatched to make the drawing easy to see.

(Embodiment 1)
In this embodiment, for example, power such as an RF (Radio Frequency) power module used (installed) in a digital mobile phone (mobile communication device, mobile communication device) that transmits information using a network such as the GSM system. An amplification module (semiconductor device).

  Here, GSM (Global System for Mobile Communication) refers to one or standard of a wireless communication method used for digital mobile phones. GSM has three frequency bands of radio waves to be used: GSM900 for 900 MHz band or simply GSM, 1800 MHz band for GSM1800 or DCS (Digital Cellular System) 1800 or PCN, 1900 MHz band for GSM1900 or DCS1900 or PCS (Personal Communication Services) ). GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may also be used. The RF power module 1 which is a semiconductor device of the present embodiment is an RF power module used in these frequency bands (high frequency bands), for example. In addition, a high frequency means a frequency of about 500 MHz or more.

  FIG. 1 shows an RF power module (high-frequency power amplifier, high-frequency power amplifier, high-frequency power amplifier module, high-frequency power amplifier module, power amplifier module, power amplifier module, RF module, RF module, HPA (High 1 is a circuit block diagram of an amplifier circuit constituting a power amplifier 1 and an electronic device 1. In this figure, for example, two frequency bands of GSM900 and DCS1800 can be used (dual band system), and GMSK (Gaussian filtered Minimum Shift Keying) modulation system and EDGE (Enhanced Data GSM Environment) modulation system in each frequency band. The circuit block diagram (amplifier circuit) of the RF power module which can use two communication systems is shown. Note that the GMSK modulation method is a method used for communication of audio signals, and is a method of shifting the phase of a carrier wave according to transmission data. The EDGE modulation method is a method used for data communication and is a method in which an amplitude shift is further added to the phase shift of GMSK modulation.

  As shown in FIG. 1, the circuit configuration of the RF power module 1 includes a power amplification circuit 102A for GSM900 (824 to 915 MHz) including three amplification stages 102A1, 102A2, and 102A3, and three amplification stages 102B1, 102B2, and 102A2. A power amplifier circuit 102B for DCS1800 (1710 to 1910 MHz) made up of 102B3 and a peripheral circuit 103 for controlling and assisting the amplification operation of the power amplifier circuits 102A and 102B are provided. The RF power module 1 further includes a matching circuit (input matching circuit) 105A between the input terminal 104a and the power amplifier circuit 102A for GSM900, and a matching circuit (input matching circuit 104B and the power amplifier circuit 102B for DCS1800). Input matching circuit) 105B. The circuit configuration of the RF power module 1 further includes a matching circuit (output matching circuit) 107A and a low-pass filter 108A between the output terminal 106a for the GSM900 and the power amplifier circuit 102A, and an output terminal 106b for the DCS 1800 and the power amplifier circuit 102B. Matching circuit (output matching circuit) 107B and low-pass filter 108B. Further, an interstage matching circuit (interstage matching circuit) 102AM1 is provided between the amplification stage 102A1 and the amplification stage 102A2 of the power amplification circuit 102A for GSM900, and a stage is provided between the amplification stage 102A2 and the amplification stage 102A3. An intervening matching circuit (interstage matching circuit) 102AM2 is provided. An interstage matching circuit (interstage matching circuit) 102BM1 is provided between the amplification stage 102B1 and the amplification stage 102B2 of the power amplification circuit 102B for the DCS 1800, and a stage is provided between the amplification stage 102B2 and the amplification stage 102B3. An inter-matching circuit (inter-stage matching circuit) 102BM2 is provided.

  Among these, the power amplifier circuit 102A for GSM900, the power amplifier circuit 102B for DCS1800, and the peripheral circuit 103 are formed in one semiconductor chip 2. As another form, the power amplifying circuit 102A for GSM900, the power amplifying circuit 102B for DCS1800, and the peripheral circuit 103 can be formed by a plurality of semiconductor chips, for example, a semiconductor chip in which amplification stages 102A1 and 102B1 are formed. Alternatively, the semiconductor chip on which the amplification stages 102A2 and 102B2 are formed and the semiconductor chip on which the amplification stages 102A3 and 102B3 are formed can be formed individually.

  The peripheral circuit 103 includes a control circuit 103A and a bias circuit 103B for applying a bias voltage to the amplification stages 102A1 to 102A3 and 102B1 to 102B3. The control circuit 103A is a circuit that generates a desired voltage to be applied to the power amplifier circuits 102A and 102B, and includes a power supply control circuit 103A1 and a bias voltage generation circuit 103A2. The power supply control circuit 103A1 generates a first power supply voltage to be applied to the drain terminal of the output amplification element (for example, MISFET (Metal Insulator Semiconductor Field Effect Transistor)) of each of the amplification stages 102A1 to 102A3 and 102B1 to 102B3. Circuit. The bias voltage generation circuit 103A2 is a circuit that generates a first control voltage for controlling the bias circuit 103B. Here, when the power supply control circuit 103A1 generates the first power supply voltage based on the output level designation signal supplied from the external baseband circuit, the bias voltage generation circuit 103A2 is generated by the power supply control circuit 103A1. The first control voltage is generated based on the power supply voltage. The baseband circuit is a circuit that generates the output level designation signal. This output level designation signal is a signal that designates the output level of the power amplifier circuits 102A and 102B, and is generated based on the distance between the mobile phone and the base station, that is, the output level corresponding to the strength of the radio wave. It is like that.

  An RF (high frequency) input signal inputted to the GSM 900 input terminal 104a of the RF power module 1 is inputted to the semiconductor chip 2 through the matching circuit 105A, and the power amplification circuit 102A in the semiconductor chip 2, that is, three amplification stages. The signals are amplified by 102A1 to 102A3, output from the semiconductor chip 2, and output as an RF (high frequency) output signal from the output terminal 106a for GSM900 through the matching circuit 107A and the low-pass filter 108A. Further, the RF input signal input to the DCS 1800 input terminal 104b of the RF power module 1 is input to the semiconductor chip 2 via the matching circuit 105B, and the power amplifier circuit 102B in the semiconductor chip 2, that is, the three amplification stages 102B1. Is amplified by ˜102B3, outputted from the semiconductor chip 2, and outputted as an RF output signal from the output terminal 106b for DCS1800 through the matching circuit 107B and the low-pass filter 108B. Each matching circuit is a circuit that performs impedance matching, and low-pass filters (low-pass filter circuit, band-pass filter circuit) 108A and 108B are circuits that attenuate harmonics.

  As described above, the RF power module 1 of the present embodiment has two systems (that is, for GSM900 and DCS1800) of power amplification circuits 102A and 102B, and the transmission frequency bands of the two systems of power amplification circuits 102A and 102B are: They are 0.9 GHz band and 1.8 GHz band, respectively.

  Next, FIG. 2 shows an example of a digital cellular phone system DPS (electronic device) using the RF power module 1 of the present embodiment. This digital cellular phone system DPS is a digital cellular phone system that transmits information using, for example, a GSM network, and is constructed by modules, circuits, elements, and the like mounted on a motherboard (mounting substrate) MB. .

  Reference numeral ANT in FIG. 2 is an antenna for transmitting and receiving signal radio waves, reference numeral 151 is a front-end module, reference numeral 152 is a voice signal converted into a baseband signal, a received signal is converted into a voice signal, and a modulation system switching signal. And a baseband circuit for generating a band switching signal. Reference numeral 153 is a modulation / demodulation circuit for down-converting and demodulating the received signal to generate a baseband signal and modulating the transmission signal, and FLT1 and FLT2 are filters for removing noise and interference waves from the received signal. The filter FLT1 is for GSM, and the filter FLT2 is for DCS. The baseband circuit 152 includes a plurality of semiconductor integrated circuits such as a DSP (Digital Signal Processor), a microprocessor, and a semiconductor memory. The front end module 151 includes switch circuits (antenna switches and antenna switch circuits) 154a and 154b, capacitors C5 and C6, and a duplexer 156. The switch circuits 154a and 154b are switch circuits for switching between transmission and reception, the capacitors C5 and C6 are elements for cutting a DC component from the received signal, and the demultiplexer 156 is a circuit for demultiplexing a signal in the GSM900 band and a signal in the DCS1800 band These circuits and elements are mounted on one wiring board to form a module. The switching signals CNT1 and CNT2 of the switch circuits 154a and 154b are supplied from the baseband circuit 152. As can be seen from FIG. 2, the outputs of the power amplifier circuits 102A and 102B are output from the RF power module 1 (output terminals 106a and 106b) via the matching circuits 107A and 107B and the low-pass filters 108A and 108B. (Antenna switch circuits) 154a and 154b are connected.

  FIG. 3 is a conceptual top view (plan view) showing the structure of the RF power module 1 of the present embodiment, and FIG. 4 is a conceptual sectional view (side cross-section) of the RF power module 1 of the present embodiment. Figure). 4 corresponds to a cross-sectional view, but shows a conceptual structure of the RF power module 1 and does not completely match a cross section obtained by cutting the structure of FIG. 3 at a predetermined position.

  The RF power module 1 of the present embodiment shown in FIGS. 3 and 4 includes a wiring board (first wiring board) 3 and a semiconductor chip (semiconductor element, active element) mounted (mounted) on the wiring board 3. 2, a passive component (passive element, chip component) 4 mounted (mounted) on the wiring substrate 3, a first resin portion 6 filled between a plurality of solder bumps 5 of the semiconductor chip 2, and a semiconductor chip 2 side resin 2c and the 2nd resin part 7 which fixes between the upper surface 3a of the wiring board 3 is provided.

  The wiring board (multilayer board, multilayer wiring board, module board) 3 is formed by, for example, laminating a plurality of insulator layers (dielectric layers) 11 and a plurality of conductor layers or wiring layers (not shown). This is a multilayer board (multilayer wiring board). In FIG. 3, the four insulating layers 11 are laminated to form the wiring board 3, but the number of the insulating layers 11 to be laminated is not limited to this and can be variously changed. As a material for forming the insulator layer 11 of the wiring board 3, for example, a ceramic material such as alumina (aluminum oxide, Al2O3) can be used. In this case, the wiring board 3 is a ceramic multilayer board. The material of the insulator layer 11 of the wiring board 3 is not limited to a ceramic material and can be variously changed. For example, a glass epoxy resin may be used.

  Between the upper surface (front surface, main surface, first main surface) 3a and lower surface (main surface, back surface, second main surface opposite to the upper surface 3a) 3b of the wiring board 3 and between the insulator layers 11 A conductor layer (wiring layer, wiring pattern, conductor pattern) for wiring formation is formed. A plurality of board-side terminals (electrodes, terminals, wiring patterns, first electrodes) 12 made of a conductor are formed on the upper surface 3 a of the wiring board 3 by the uppermost conductor layer of the wiring board 3. A plurality of external connection terminals (terminals, electrodes, module electrodes, second electrodes) 13 made of a conductor are formed on the lower surface 3b of the wiring board 3 by the conductor layer. The external connection terminal 13 corresponds to, for example, the input terminals 104a and 104b and the output terminals 106a and 106b in FIG. A conductor layer (wiring layer, wiring pattern, conductor pattern) is also formed inside the wiring board 3, that is, between the insulator layers 11, but is not shown in FIG. 3 for the sake of simplicity. Among the wiring patterns formed by the conductor layer of the wiring substrate 3, the wiring pattern for supplying the reference potential (for example, the reference potential supplying terminal 13 a on the lower surface 3 b of the wiring substrate 3) is used for forming the wiring of the insulator layer 11. The wiring pattern for the transmission line can be formed as a belt-like pattern so as to cover the most area of the surface. Note that not only the external connection terminal 13 but also the reference potential supply terminal 13 a can be regarded as an external connection terminal or electrode of the RF power module 1.

  Each conductor layer (wiring layer) constituting the wiring board 3 is electrically connected through a conductor or a conductor film in a via hole (not shown) formed in the insulator layer 11 as necessary. Accordingly, the board-side terminal 12 on the upper surface 3a of the wiring board 3 is connected via the upper surface 3a of the wiring board 3 and / or the internal wiring layer, the conductor film in the via hole, or the like as necessary. 3b is electrically connected to the external connection terminal 13 or the reference potential supply terminal 13a. Also, via holes that function as thermal vias for conducting heat generated in the semiconductor chip 2 to the lower surface 3 b side of the wiring substrate 3 can be provided in the wiring substrate 3 below the semiconductor chip 2.

  The semiconductor chip 2 is a semiconductor chip 2 on which a semiconductor integrated circuit corresponding to a circuit configuration surrounded by a dotted line indicating the semiconductor chip 2 in the circuit block diagram of FIG. 1 is formed. Therefore, the semiconductor chip 2 includes an amplifier circuit (power amplifier circuit). In the semiconductor chip 2 (or the surface layer portion), semiconductor amplifier elements (for example, MISFET, heterojunction bipolar transistor or HEMT (High Electron Mobility Transistor)) constituting each amplification stage of the power amplifier circuits 102A and 102B, peripheral circuit 103 And the passive elements constituting the matching circuits 102AM1, 102AM2, 102BM1, 102BM1 are formed. As described above, the RF power module 1 has the power amplifier circuits (102A and 102B), and the semiconductor chip 2 is an active element constituting the power amplifier circuits (102A and 102B). A plurality of solder bumps (solder bump electrodes, bump electrodes made of solder, protruding electrodes made of solder) 5 are formed on the surface of the semiconductor chip 2 (main surface on the element forming side). It is more preferable that the solder bump 5 is formed of lead (Pb) -free solder that does not contain lead (Pb). For example, Sn—Ag—Cu-based lead-free solder can be used as a material constituting the solder bump 5. Each solder bump 5 is electrically connected to a semiconductor integrated circuit formed in the semiconductor chip 2.

  FIG. 5 shows, as an example, an LDMOSFET (Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor), a lateral diffusion MOSFET. 2 is a cross-sectional view of the main part of the semiconductor chip 2 when formed by (1).

  As shown in FIG. 5, an epitaxial layer 202 made of p− type single crystal silicon is formed on the main surface of a semiconductor substrate 201 made of p + type single crystal silicon, and a part of the main surface of the epitaxial layer 202 is formed on the main surface. A p-type well 206 that functions as a punch-through stopper that suppresses the extension of the depletion layer from the drain to the source of the LDMOSFET is formed. On the surface of the p-type well 206, a gate electrode 208 of the LDMOSFET is formed via a gate insulating film 207 made of silicon oxide or the like. The gate electrode 208 is made of, for example, an n-type polycrystalline silicon film or a laminated film of an n-type polycrystalline silicon film and a metal silicide film. A sidewall spacer 211 made of silicon oxide or the like is formed on the side wall of the gate electrode 208. Is formed.

  The source and drain of the LDMOSFET are formed in regions separated from each other across the channel formation region inside the epitaxial layer 202. The drain has an n − type offset drain region 209 in contact with the channel formation region, an n type offset drain region 212 in contact with the n − type offset drain region 209 and spaced apart from the channel formation region, and an n type offset drain region. And an n + -type drain region 213 formed in contact with 212 and further away from the channel formation region. Among these n − type offset drain region 209, n type offset drain region 212 and n + type drain region 213, the n − type offset drain region 209 closest to the gate electrode 208 has the lowest impurity concentration and is the farthest from the gate electrode 208. The n + -type drain region 213 has the highest impurity concentration.

  The source of the LDMOSFET is an n − type source region 210 that is in contact with the channel formation region, an n + type source region 210 that is in contact with and spaced from the channel formation region, and n + having a higher impurity concentration than the n − type source region 210. It consists of a mold source region 214. A p-type halo region (not shown) may be formed below the n − -type source region 210.

  A p-type punching layer 204 in contact with the n + type source region 214 is formed at the end of the n + type source region 214 (the end opposite to the side in contact with the n− type source region 210). Near the surface of the p-type punching layer 204, a p + -type semiconductor region 215 is formed. The p-type punching layer 204 is a conductive layer for electrically connecting the source of the LDMOSFET and the semiconductor substrate 201, and is formed of, for example, a p-type polycrystalline silicon film embedded in the groove 203 formed in the epitaxial layer 202. Is done.

  An insulating film (interlayer insulating film) 221 is formed on the p-type punched layer 204 (p + type semiconductor region 215), source (n + type source region 214), and drain (n + type drain region 213) of the LDMOSFET. The plug 223 in the contact hole 222 is connected. A source electrode 224a (wiring 224) is connected to the p-type punching layer 204 (p + type semiconductor region 215) and the source (n + type source region 214) through a plug 223, and to the drain (n + type drain region 213). The drain electrode 224b (wiring 224) is connected through the plug 223.

  A wiring 228 is connected to each of the source electrode 224a and the drain electrode 224b via a plug 227 in a through hole 226 formed in an insulating film (interlayer insulating film) 225 that covers the source electrode 224a and the drain electrode 224b. . A surface protective film (insulating film) 229 made of a laminated film of a silicon oxide film and a silicon nitride film is formed on the insulating film 225 so as to cover the wiring 228. A plurality of openings 230 are formed in the surface protective film 229, and solder bumps 232 are formed on the wirings 228 exposed from the openings 280 via UBM (Under Bump Metal, bump base metal layer) films 231 such as a gold film. (Corresponding to the solder bump 5) is formed. A back electrode (source back electrode) 233 is formed on the back surface of the semiconductor substrate 201.

  In FIG. 6, as another example, the semiconductor amplifying elements constituting the power amplifier circuits 102A and 102B (amplification stages 102A1 to 102A3 and 102B1 to 102B3) are formed by heterojunction bipolar transistors (HBTs). It is principal part sectional drawing of the semiconductor chip 2 in the case.

  As shown in FIG. 6, a subcollector layer 252 made of an n + type GaAs layer is formed on a semi-insulating GaAs substrate (semiconductor substrate) 251, and an HBT 253 is formed on the subcollector layer 252.

  Each HBT 253 has a collector electrode 254 made of gold or the like formed on the sub-collector layer 252 and a collector mesa 255 formed at a predetermined distance from the collector electrode 254. The collector mesa 255 is formed of, for example, an n-type GaAs layer, and the collector mesa 255 and the collector electrode 254 are electrically connected via the subcollector layer 252.

  A base mesa 256 made of, for example, a p-type GaAs layer is formed on the collector mesa 255. A base electrode 257 made of gold or the like is formed in the peripheral region on the base mesa 256. An emitter layer 258 is formed on a substantially central portion of the base mesa 256, and an emitter electrode 259 is formed on the emitter layer 258. The emitter layer 258 is formed of, for example, an n-type InGaP layer, a GaAs layer, and an InGaAs layer, and the emitter electrode 259 is formed of, for example, tungsten silicide. As described above, a heterogeneous semiconductor junction (heterojunction) is formed between the base mesa (p-type GaAs layer) 256 and the emitter layer (n-type InGaP layer) 258.

  A collector wiring 263 is connected to the collector electrode 254 through a contact hole 262 formed in the insulating film 261. An emitter wiring 266 is connected to the emitter electrode 259 via a through hole 265 formed in the insulating films 264 and 261. Although the illustration and description of the structure above the emitter wiring 266 are omitted here, the structure corresponding to the solder bump 5 is also formed on the surface of the semiconductor chip 2 in this case.

  In the present embodiment, the semiconductor chip 2 is flip-chip mounted on the upper surface 3a of the wiring board 3 as shown in FIGS. That is, the semiconductor chip 2 has its back surface (main surface opposite to the main surface on the solder bump 5 formation side) 2b facing upward, and its front surface (main surface on the solder bump 5 formation side) 2a is on the wiring board 3. It is mounted (mounted) on the upper surface 3a of the wiring board 3 in a direction facing the upper surface 3a. Therefore, the semiconductor chip 2 is face-down bonded to the upper surface 3 a of the wiring substrate 3. The plurality of solder bumps 5 on the surface 2 a of the semiconductor chip 2 are respectively joined and electrically connected to a plurality of substrate-side terminals 12 (a plurality of substrate-side terminals 12 a among them) on the upper surface 3 a of the wiring substrate 3. Yes. Accordingly, the semiconductor chip 2 (semiconductor integrated circuit formed on the semiconductor chip 2) is electrically connected to the plurality of substrate side terminals 12 (12 a) of the wiring substrate 3 through the plurality of solder bumps 5.

  A first resin portion (first resin) 6 is filled between the plurality of solder bumps 5 (between adjacent solder bumps 5). The first resin portion 6 is formed so as to be filled (filled and supplied) between the surface 2 a of the semiconductor chip 2 and the upper surface 3 a of the wiring substrate 3 and filled (filled) between the adjacent solder bumps 5. And can function as an underfill resin. The first resin portion 6 protects the solder bump 5 (or the connection portion of the solder bump 5), or buffers the burden on the solder bump 5 due to the difference in thermal expansion coefficient between the semiconductor chip 2 and the wiring substrate 3. be able to.

  In the present embodiment, a second resin portion (second resin) 7 that fixes the side surface 2c of the semiconductor chip 2 and the upper surface 3a of the wiring board 3 is further provided. The second resin portion 7 is formed so as to contact (adhere) both the side surface 2 c of the semiconductor chip 2 and the upper surface 3 a of the wiring substrate 3.

  It is more preferable that the second resin portion 7 is in contact with (adheres to) the four side surfaces 2 c of the semiconductor chip 2. Further, the second resin portion 7 only needs to be in contact (contact) with at least a part of the side surface 2c of the semiconductor chip 2, but the side surface 2c of the semiconductor chip 2 and the second resin portion 7 are in contact (contact). The larger the area, the better. It is more preferable that the second resin portion 7 is in contact (adhered) to the entire side surface 2c of the semiconductor chip 2. Further, it is more preferable that the second resin portion 7 is formed so as to contact (adhere) the first resin portion 6 and cover the first resin portion 6. Thereby, the semiconductor chip 2 can be firmly fixed to the wiring board 3 by the second resin portion 7.

  The 1st resin part 6 and the 2nd resin part 7 consist of an insulating resin material, and can also contain a filler etc. Silica or the like can be used as the filler. If the resin material which comprises the 1st resin part 6 and the 2nd resin part 7 is a thermosetting resin material, it is more preferable.

  In the present embodiment, the elastic modulus of the second resin 7 is larger than the elastic modulus of the first resin 6. By using different resin materials for the resin material constituting the first resin part 6 and the resin material constituting the second resin part 7, the elastic modulus of the second resin 7 is made higher than that of the first resin 6. Can also be increased. It is more preferable to use a silicone resin as the resin material constituting the first resin portion 6, whereby the first resin portion 6 having a low elastic modulus can be easily realized, and as the resin material constituting the second resin portion 7. It is more preferable to use an epoxy resin, whereby the second resin portion 7 having a high elastic modulus can be easily realized. That is, by using an epoxy resin as a resin material constituting the second resin part 7 and using a silicone resin as a resin material constituting the first resin part 6, the elastic modulus of the second resin 7 is made to be the elasticity of the first resin 6. Can be greater than the rate. The preferable elastic modulus ranges of the first resin portion 6 and the second resin portion 7 will be described in detail later.

  The passive component 4 includes a passive element such as a resistance element (for example, a chip resistor), a capacitance element (for example, a chip capacitor), or an inductor element (for example, a chip inductor), and includes, for example, a chip component. The passive component 4 is a passive component that constitutes, for example, matching circuits (input matching circuits) 105A and 105B and matching circuits (output matching circuits) 107A and 107B. The passive elements constituting the matching circuits (interstage matching circuits) 102AM1, 102AM2, 102BM1, and 102BM1 are formed by the passive component 4 either in the semiconductor chip 2 or not in the semiconductor chip 2. May be. The passive component 4 is mounted (mounted) on the upper surface 3 a of the wiring board 3 via the solder 17. That is, the passive component 4 is mounted on the board-side terminal 12 (the board-side terminal 12b) of the upper surface 3a of the wiring board 3 by a bonding material having good conductivity such as the solder 17, and the electrode of the passive component 4 is mounted on the board. The side terminals 12 (of which the board side terminals 12b) are electrically connected via the solder 17. The solder 17 is more preferably formed of lead (Pb) -free solder that does not contain lead (Pb), and for example, Sn—Ag—Cu-based lead-free solder can be used.

  Between the substrate-side terminals 12 on the upper surface 3a of the wiring substrate 3 to which the semiconductor chip 2 and the passive component 4 are electrically connected, the upper surface 3a of the wiring substrate 3 or an internal wiring layer, a conductor film in a via hole, or the like as necessary. And are electrically connected to the external connection terminal 13 or the reference potential supply terminal 13a on the lower surface 3b of the wiring board 3.

  Next, a manufacturing process (manufacturing method) of the RF power module (semiconductor device) 1 of the present embodiment will be described with reference to the drawings.

  FIG. 7 is a manufacturing process flow diagram showing manufacturing steps of the RF power module 1 of the present embodiment. 8-16 is principal part sectional drawing or principal part top view in the manufacturing process of RF power module 1. FIG. 8 to 16, FIG. 11 and FIG. 13 are plan views, and the others are cross-sectional views. 11 and 12 correspond to plan views and cross-sectional views at the same process stage, and FIGS. 13 and 14 correspond to plan views and cross-sectional views at the same process stage.

  The RF power module 1 of the present embodiment can be manufactured as follows, for example.

  First, the semiconductor chip 2 and the wiring board 3 are prepared (prepared) (step S1). The semiconductor chip 2 is formed, for example, by forming a semiconductor integrated circuit or a solder bump on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like and then separating the semiconductor substrate into each semiconductor chip 2 by dicing or the like. be able to. The semiconductor chip 2 has a plurality of solder bumps 5 electrically connected to a semiconductor integrated circuit (semiconductor element) formed in the semiconductor chip 2 on the surface 2 a of the semiconductor chip 2. It is more preferable if the solder bump 5 is formed of lead (Pb) -free solder that does not contain lead (Pb). Further, the wiring board 3 can be manufactured by using, for example, a printing method, a sheet lamination method, a build-up method, or the like. As shown in FIG. 8, the wiring substrate 3 includes a plurality of substrate-side terminals 12 a to be connected to the plurality of solder bumps 5 of the semiconductor chip 2 and a plurality of substrate-side terminals to be connected to the electrodes of the passive component 4, respectively. A plurality of substrate-side terminals 12 including 12b are provided on the upper surface 3a, and a plurality of external connection terminals 13 and one or a plurality of reference potential supply terminals 13a are provided on the lower surface 3b. The semiconductor chip 2 may be manufactured before the wiring substrate 3, the wiring substrate 3 may be manufactured before the semiconductor chip 2, or the semiconductor chip 2 and the wiring substrate 3 may be manufactured simultaneously.

  Next, as shown in FIG. 9, the solder 21 is supplied onto the wiring board 3 (the board-side terminal 12) (step S2). In the solder 21 supplying process in step S2, the solder 21 is supplied onto the board-side terminal 12b on which the passive component 4 of the wiring board 3 is to be mounted (connected) by a printing method or a coating method. As the solder 21 to be supplied onto the board-side terminal 12b, for example, solder paste or the like can be used, and lead (Pb) -free solder that does not contain lead (Pb) is more preferable.

  Although not shown in the drawing, in step S2, the solder 21 can be supplied not only on the substrate-side terminal 12b but also on the plurality of substrate-side terminals 12a on which the semiconductor chip 2 is to be mounted, as welcome solder. As a result, the solder bumps 5 of the semiconductor chip 2 and the board-side terminals 12a of the wiring board 3 can be more accurately connected.

  Next, the passive component 4 and the semiconductor chip 2 are arranged (mounted) on the upper surface 3a of the wiring board 3 (step S3). In step S3, the semiconductor chip 2 may be placed on the wiring board 3, the passive component 4 may be placed first, or both may be placed simultaneously. In step S3, the semiconductor chip 2 is arranged face-down on the upper surface 3a of the wiring board 3 so that the back surface 2b side faces upward and the front surface 2a side faces downward (upper surface 3a side of the wiring board 3). The two solder bumps 5 are aligned so as to face the plurality of board-side terminals 12a on the upper surface 3a of the wiring board 3, respectively.

  Next, solder reflow processing (reflow processing, heat treatment) is performed (step S4). In the solder reflow process of step S4, the wiring board 3, the passive component 4, the semiconductor chip 2 (including the solder bumps 5), and the solder 21 on the wiring board 3 are heated. For example, the wiring board 3 on which the semiconductor chip 2 and the passive component 4 are mounted is arranged on a heat block (not shown), and the heating block is heated by a heater or the like built in the heat block. The component 4, the semiconductor chip 2 (including the solder bumps 5), and the solder 21 can be heated.

  Through the solder reflow process of step S4, the solder bumps 5 and the solder 21 of the semiconductor chip 2 are reflowed (solder reflow, melting / solidifying, remelting). That is, as shown in FIG. 10, the solder bump 5 and the solder 21 are once melted and solidified by the solder reflow process in step S <b> 4, so that the plurality of solder bumps 5 and the plurality of substrate-side terminals of the semiconductor chip 2 are solidified. 12a is joined (connected, soldered) and electrically connected, and the electrodes of the plurality of passive components 4 and the plurality of board-side terminals 12b are joined (connected, soldered) to be electrically connected. Connected. In other words, the terminals (electrodes) of the semiconductor chip 2 and the board-side terminals 12a of the wiring board 3 are joined (connected, soldered) via the solder bumps 5 and are electrically connected. The solder 21 solidified after melting becomes the solder 17, and the passive component 4 is mounted (mounted) on the upper surface 3a of the wiring board 3 via the solder 17 (second solder). Further, when the solder 21 is also supplied to the substrate side terminal 12a in step S2, the solder 21 on the substrate side terminal 12a is connected to the solder bump 5 to be connected to the substrate side terminal 12a by the solder reflow in step S4. Integrate.

  Next, the first resin material 6a for forming the first resin portion 6 is supplied (injected) between the surface 2a of the semiconductor chip 2 and the upper surface 3a of the wiring board 3, and between the plurality of solder bumps 5 (adjacent to each other). The first resin material 6a is filled between the solder bumps 5 (step S5). For example, as shown in FIGS. 11 and 12, the first resin material 6 a is wired to the surface 2 a of the semiconductor chip 2 from the lateral direction of the semiconductor chip 2 (side surface 2 c side of the semiconductor chip 2) by the resin injection nozzle 22. Injection (supply) between the upper surface 3 a of the substrate 3 is performed. At this time, it is preferable that the space between the adjacent solder bumps 5 is filled (filled) with the first resin material 6 a so that no voids are formed between the adjacent solder bumps 5.

  The viscosity of the first resin material 6a is adjusted to a predetermined value. When the first resin material 6a is injected between the semiconductor chip 2 and the wiring substrate 3 from the resin injection nozzle 22, the first resin material 6a is connected to the semiconductor chip 2 and the wiring. Work is performed by inclining the wiring board 3 in a direction that flows between the semiconductor chip 2 and the substrate 3 so that the first resin material 6a wraps around between the semiconductor chip 2 and the wiring board 3 in a short time. It has been conditioned. In addition, in the upper surface 3a of the wiring board 3, the area where the resin injection nozzle 22 is brought close to the semiconductor chip 2 is designed not to place the passive component 4 or the like. The first resin material 6 a can be injected between the semiconductor chip 2 and the wiring substrate 3 by bringing the resin injection nozzle 22 close to the semiconductor chip 2 without doing so.

  The 1st resin material 6a consists of resin materials, and can contain a filler (for example, silica) etc. Moreover, it is preferable that the resin material which comprises the 1st resin material 6a consists of thermosetting resins, and if it is a silicone resin, it is more preferable.

  Next, as shown in FIGS. 13 and 14, a baking process (heat treatment, heat treatment for resin curing) is performed to cure the first resin material 6a and form the first resin portion 6 (step S6). ). Since the 1st resin material 6a consists of thermosetting resins as mentioned above, the 1st resin material 6a hardens | cures by the baking process of step S6, and it becomes the hardened 1st resin part 6. FIG. The amount of the first resin material 6a supplied in step S5 is such that the space between the semiconductor chip 2 and the wiring board 3 is filled, and the space between the plurality of solder bumps 5 (between adjacent solder bumps 5) is the first resin material 6a. It is preferable to set the minimum amount necessary for filling so that the first resin material 6a is not supplied excessively more than necessary. Accordingly, at least a part of each side surface 2 c of the semiconductor chip 2 is exposed without being covered by the first resin portion 6. The second resin portion 7 to be formed later is in close contact with this exposed portion of each side surface 2c of the semiconductor chip 2.

  Next, the second resin material 7a is supplied (injected, applied, arranged, formed) between the side surface 2c of the semiconductor chip 2 and the upper surface 3a of the wiring substrate 3 (step S7). For example, as shown in FIG. 15, the resin injection nozzle 24 is brought close to the four side surfaces 2 c of the semiconductor chip 2 from above (the back surface 2 b side) of the semiconductor chip 2 to surround the four sides of the semiconductor chip 2 (on the four side surfaces 2 c). The second resin material 7a is applied from the resin injection nozzle 24 in the vicinity. Thereby, the second resin material 7 a is arranged between the side surface 2 c of the semiconductor chip 2 and the upper surface 3 a of the wiring substrate 3 so as to cover the first resin portion 6.

  In step S5, the first resin material 6a is injected while the wiring board 3 is tilted. In step S7, it is preferable that the wiring board 3 is in a horizontal state without being tilted. The resin injection nozzle 24 is manufactured in accordance with the dimensions of the semiconductor chip 2, and the second resin material 7 a can be supplied or arranged near the four side surfaces 2 c of the semiconductor chip 2 from the resin injection nozzle 24. . By supplying the second resin material 7a using the dedicated resin injection nozzle 24 corresponding to the semiconductor chip 2, the second resin material 7a can be applied reasonably and efficiently, and is unnecessary. It is possible to prevent the second resin material 7a from adhering to the back surface 2b of the semiconductor chip 2 or the like. The viscosity of the second resin material 7a is also adjusted to a predetermined value, and after application of an appropriate amount, the second resin material 7a is sufficiently applied to the side surface 2c of the semiconductor chip 2, and the four side surfaces 2c of the semiconductor chip 2 are applied. Then, the second resin material 7a is sufficiently in contact with the first resin portion 6 and the upper surface 3a of the wiring board 3.

  In step S7, the second resin material 7a is supplied by the dedicated nozzle (resin injection nozzle 24) designed according to the semiconductor chip 2 as described above, and the amount and supply range of the supplied second resin material 7a are as follows. The minimum amount and range required to achieve the purpose of fixing (reinforcing) between the semiconductor chip 2 and the wiring board 3 are set so that the second resin material 7a is not supplied excessively more than necessary. It is preferable. Thereby, the 2nd resin material 7a can be supplied to a required area | region exactly, and it can prevent that the unnecessary 2nd resin material 7a adheres to the passive component 4 grade | etc.,.

  The 2nd resin material 7a consists of resin materials, and can contain a filler (for example, silica) etc. Moreover, it is preferable that the resin material which comprises the 2nd resin material 7a consists of thermosetting resins, and if it is an epoxy resin, it is more preferable.

  Next, as shown in FIG. 16, a baking process (heat treatment, heat treatment for resin curing) is performed to cure the second resin material 7a and form the second resin portion 7 (step S8). As described above, since the second resin material 7a is made of a thermosetting resin, the second resin material 7a is cured by the baking treatment in step S7, and the cured second resin portion 7 is obtained. As described above, since the second resin material 7a is disposed so as to cover the first resin portion 6 between the side surface 2c of the semiconductor chip 2 and the upper surface 3a of the wiring substrate 3, the second resin portion 7 Is formed between the side surface 2 c of the semiconductor chip 2 and the upper surface 3 a of the wiring substrate 3 so as to cover the first resin portion 6.

  A material constituting the first resin material 6a and a material constituting the second resin material 7a so that the elastic modulus of the cured second resin portion 7 is larger than the elastic modulus of the cured first resin portion 6; Has been adjusted. The preferable range of the elastic modulus of the first resin part 6 and the second resin part 7 after curing will be described in detail later.

  In this way, the RF power module 1 that is the semiconductor device of the present embodiment is manufactured. When manufacturing a plurality of RF power modules 1 from one wiring board 3, the wiring board 3 is divided at a predetermined position after the resin curing (second resin portion 7 formation) by the baking process in step S8. (Cutting) and the RF power module 1 as each piece can be obtained.

  The RF power module 1 of the present embodiment can be mounted on a mounting board (motherboard) or the like. That is, solder can be formed on the plurality of external connection terminals 13 and the reference potential supply terminal 13a of the wiring board 3 of the RF power module 1, and the RF power module 1 can be mounted on the mounting board 31 via solder. . FIG. 17 is a mounting process flow diagram showing the mounting process of the RF power module 1. 18 to 21 are cross-sectional views of the main part of the RF power module 1 during the mounting process.

  The RF power module 1 of the present embodiment can be mounted on the mounting substrate 31 as follows.

  First, a mounting board (wiring board, second wiring board) 31 is prepared (prepared) (step S11). The mounting substrate 31 can be prepared before, during, after, or simultaneously with the manufacture of the RF power module 1.

  As shown in FIG. 18, the mounting substrate 31 is made of, for example, a wiring substrate (printed wiring substrate) having a multilayer wiring structure. The mounting substrate 31 includes a plurality of substrate-side terminals (electrodes) 33 to be connected to the plurality of external connection terminals 13 of the RF power module 1 and a substrate-side terminal to be connected to the reference potential supply terminal 13 a of the RF power module 1. (Electrode) 33a is provided on the main surface (upper surface, front surface) 31a. The mounting substrate 31 corresponds to, for example, the motherboard MB in FIG. Therefore, the mounting process of FIGS. 17 to 21 can be applied to the mounting process of the RF power module 1 in a mobile phone (for example, the digital mobile phone system DPS of FIG. 1).

  Next, as shown in FIG. 19, solder (for example, solder paste) 34 is supplied onto the board-side terminals 33 and 33a of the mounting board 31 (step S12).

  Next, as shown in FIG. 20, the RF power module 1 is disposed (mounted) on the main surface 31a of the mounting substrate 31 (step 13). At this time, the RF power module 1 is arranged on the mounting substrate 31 with the lower surface 3 b side of the wiring substrate 3 facing the main surface 31 a side of the mounting substrate 31. As a result, the plurality of external connection terminals 13 (second electrodes) of the wiring board 3 (first wiring board) of the RF power module 1 become the plurality of board-side terminals 33 (third electrodes) of the mounting board 31 (second wiring board). ) Are arranged via solder 34 (first solder), and the reference potential supply terminal 13a (second electrode) of the wiring board 3 of the RF power module 1 is connected to the substrate side terminal 33a (third electrode) of the mounting board 31. ) Over the solder 34 (first solder).

  Next, solder reflow processing (reflow processing, heat treatment) is performed (step S14). In the solder reflow process of step S14, the solder 34 is reflowed (solder reflow, melting / solidifying, remelting), and the solder 34 is once melted and then solidified. By the solder reflow in step S14, the plurality of external connection terminals 13 (second electrodes) of the RF power module 1 are soldered to the plurality of board side terminals 33 (third electrodes) of the mounting board 31, respectively, as shown in FIG. The reference potential supply terminal 13a of the RF power module 1 is soldered to the board-side terminal 33a of the mounting board 31 by being joined (connected, soldered) via 34 (first solder) and electrically connected. And are electrically connected. The solder 34 is more preferably a lead (Pb) -free solder that does not contain lead (Pb). For example, Sn—Ag—Cu-based lead-free solder can be used as the solder 34.

  In this way, the RF power module 1 can be mounted on the mounting substrate 31. Further, since the RF power module 1 is manufactured and then shipped and the customer can mount the RF power module 1 on the mounting board 31, the RF power module 1 on the mounting board 31 as shown in FIGS. This implementation can be referred to as a secondary implementation.

  Next, the effect of this embodiment will be described in more detail.

  Unlike this embodiment, when an RF power module is manufactured by face-up bonding a semiconductor chip on a wiring board and wire-bonding the semiconductor chip and the wiring board, the height of the wire loop of the bonding wire As a result, the RF power module becomes thick. Further, on the upper surface of the wiring board, an area for extending the bonding wire is required in addition to the area for arranging the semiconductor chip, so that the planar size of the RF power module is increased. As mobile phones become smaller and thinner, RF power modules used therefor are also required to be smaller and thinner. However, the formation of RF power modules using wire bonding is not possible with RF power modules. This is disadvantageous for downsizing and thinning.

  On the other hand, in the RF power module 1 which is the semiconductor device of the present embodiment, the semiconductor chip 2 is connected to the upper surface 3a of the wiring substrate 3 in a Philip chip manner face down, and the semiconductor chip 2 is wired via the solder bumps 5. The substrate 3 is electrically connected to the substrate side terminal 12. For this reason, it is not necessary to use wire bonding, and the thickness of the RF power module 1 can be reduced as compared with the case where a bonding wire is used, and the planar dimensions can be reduced. Therefore, the RF power module and a mobile phone (electronic device) using the RF power module can be reduced in size and thickness.

  When flip-chip mounting a semiconductor chip on a wiring board, due to the difference in thermal expansion coefficient (thermal expansion coefficient) between the wiring board and the semiconductor chip, between the solder bump and the wiring board or between the solder bump and the semiconductor chip. In addition, cracks may occur. For this reason, an underfill resin is provided, and the connection portion (solder bump) between the semiconductor chip and the wiring board is protected by the underfill resin, and the solder bump due to the difference in thermal expansion coefficient between the semiconductor chip and the wiring board is provided. It is preferable to buffer the burden.

  Further, during the solder reflow in step S14 for mounting (secondary mounting) the RF power module 1 on the mounting substrate 31, not only the solder 34 for mounting the RF power module 1 but also the solder bumps in the RF power module 1 5 may melt.

  Unlike this embodiment, when an underfill resin is formed so as to fill the space between the solder bumps 5 and this underfill resin is formed of a high elastic modulus epoxy resin, the solder reflow in step S14 is performed. When the solder bumps 5 in the RF power module are remelted, the highly elastic epoxy resin underfill resin cannot absorb the volume expansion due to the melting of the solder bumps 5 and may cause a short circuit between terminals due to the solder expansion. . That is, even if the solder bumps 5 are remelted and the volume is expanded, the highly elastic epoxy resin cannot be shrunk by the expanded volume, and the underfill resin and the wiring board 3 are caused by the melt expansion pressure of the solder bumps 5. Alternatively, the interface with the semiconductor chip 2 is peeled off, and the melted solder flows in a flash state, causing a short circuit between adjacent solder bumps 5 or adjacent substrate side terminals 12a (so-called solder flash). there is a possibility. In order to prevent this, it is conceivable that the underfill resin is formed of a silicone resin having a low elastic modulus. With this, the RF power module can be reflowed during solder reflow for mounting the RF power module on the mounting substrate 31. Even if the solder bumps 5 in 1 are remelted, the underfill resin having a low elastic modulus can absorb the volume expansion due to the melting of the solder bumps 5, so that the terminals between the solder bumps 5 (between the solder bumps 5 or the board side terminals 12a). Can be prevented from occurring.

  However, unlike the present embodiment, when the underfill resin is formed only of a low elastic silicone resin, the impact applied to the solder bumps 5 when the RF power module or a mobile phone using the same is dropped is reduced. The soft underfill resin cannot be relaxed, and a crack or the like occurs between the solder bump 5 and the semiconductor chip 2 or between the solder bump 5 and the board-side terminal 12 of the wiring board 3. May be reduced. Since the size of the solder bump 5 of the semiconductor chip 2 is small, the connecting portion between the solder bump 5 and the semiconductor chip 2 or between the solder bump 5 and the board-side terminal 12 of the wiring board 3 is the RF power module 1. The connection strength is the weakest among the solder connection portions, and when a physical impact is applied to the RF power module 1, a connection failure (disconnection failure) is likely to occur there. For this reason, the resistance (impact resistance) with respect to physical impacts, such as dropping, in the RF power module and a cellular phone (electronic device) using the RF power module is lowered. In particular, mobile phones are subject to physical impacts such as dropping, considering the usage environment, and therefore, impact resistance is important for mobile phones and RF power modules (semiconductor devices) used therefor.

  On the other hand, in the present embodiment, the low elasticity first resin portion 6 filled between the plurality of solder bumps 5 and the side surface 2c of the semiconductor chip 2 and the upper surface 3a of the wiring substrate 3 are fixed. The second resin part 7 having high elasticity is provided, and the first resin part 6 having low elasticity and the second resin part 7 having higher elasticity than the first resin part 6 are used as the sealing resin (underfill resin). It has a heavy structure.

  In the present embodiment, the first resin portion 6 is formed so as to fill between the surface 2 a of the semiconductor chip 2 and the upper surface 3 a of the wiring substrate 3 and to fill (fill) between the adjacent solder bumps 5. Therefore, it functions as an underfill resin. By configuring the first resin portion 6 with a low-elasticity resin, the periphery of the first resin portion 6 is surrounded by the first during the solder reflow (step S14) for mounting the RF power module 1 on the mounting substrate 31 (secondary mounting). Even if the solder bump 5 covered with the resin portion 6 is remelted, the first resin portion 6 having a low elastic modulus can absorb the volume expansion due to the melting of the solder bump 5 (the first portion corresponding to the expansion of the solder bump 5). Therefore, it is possible to prevent a short circuit (so-called solder flash) between terminals (between the solder bumps 5 or between the board-side terminals 12a) due to the expansion of the solder. Since a short circuit between adjacent solder bumps 5 or between the board-side terminals 12a due to solder expansion can be prevented, the reliability of electrical connection via the solder bumps 5 between the semiconductor chip 2 and the wiring board in the RF power module 1 can be improved. It is possible to improve the reliability of secondary mounting of the RF power module 1 (solder mounting on the mounting substrate 31).

  For this reason, it is preferable that the first resin portion 6 is a resin having a low elastic modulus. In particular, the first resin portion 6 has a low elastic modulus at the temperature of solder reflow for mounting the RF power module 1 on the mounting substrate 31 (step S14). It is preferable that In other words, it is preferable that the elastic modulus of the first resin portion 6 is low at the melting point of the solder bump 5, which is the temperature at which the solder bump 5 is remelted at the time of solder reflow in step S14, or at a temperature equal to or higher than the melting point. More specifically, in consideration of the secondary reflow temperature (solder reflow in step S14) and the conditions at the time of applying a high temperature in the temperature cycle test, the first resin portion 6 has a pressure of 1 to 1000 MPa at a temperature of 150 ° C. or higher. It is more preferable if it has an elastic modulus (1 MPa or more and 1000 MPa or less), and even more preferable if it has an elastic modulus of 1 to 200 MPa (1 MPa or more and 200 MPa or less) at a temperature of 150 ° C. or more. If the first resin part 6 has an elastic modulus of preferably 1000 MPa or less, more preferably 200 MPa or less at a temperature of 150 ° C. or higher, the first resin part 6 will expand the volume due to remelting of the solder bumps 5. Absorption can be performed more accurately, and a short circuit between terminals (solder flash) due to expansion of solder can be prevented more accurately. Moreover, if the 1st resin part 6 has the elasticity modulus of 1 Mpa or more in the temperature of 150 degreeC or more, the protection function of the solder bump 5 by the 1st resin part 6 is securable.

  In the present embodiment, the semiconductor chip 2 is fixed to the wiring substrate 3 by providing the second resin portion 7 that fixes the side surface 2 c of the semiconductor chip 2 and the upper surface 3 a of the wiring substrate 3. The second resin portion functions as a reinforcing resin (mechanical reinforcing resin) for connection (fixing) between the semiconductor chip 2 and the wiring substrate 3. By configuring the second resin portion 7 with a highly elastic resin, the semiconductor chip 2 can be firmly (strongly) fixed to the wiring substrate 3 via the second resin portion 7. Therefore, the semiconductor chip 2 is firmly fixed to the wiring substrate 3 via the second resin portion 7 even when a physical impact such as dropping is applied to the RF power module 1 or a mobile phone using the RF power module 1. Therefore, this impact (impact stress) is mitigated by the second resin portion 7 and is not easily transmitted to the solder bump 5, and is between the solder bump 5 and the semiconductor chip 2 or between the solder bump 5 and the wiring board 3. The stress (impact stress) applied to the connection part between 12 can be relieved. Therefore, a crack or the like (connection failure) occurs in the connection portion between the solder bump 5 and the semiconductor chip 2 or between the solder bump 5 and the board-side terminal 12 of the wiring board 3 due to a physical impact such as dropping. Can be prevented, and the reliability of electrical connection can be improved. Thereby, the tolerance (impact resistance) with respect to physical impacts, such as a fall, in RF power module 1 or a mobile telephone (electronic device) using the same can be improved.

  For this reason, it is preferable that the second resin portion 7 is a resin having a high elastic modulus, and in particular, normal temperature (room temperature, about 20 to 30 ° C., typical temperature is a temperature during actual use at which dropping or the like may occur) The elastic modulus at 25 ° C. is preferably high. More specifically, it is more preferable that the second resin portion 7 has an elastic modulus of 1000 MPa (1 GPa) or more at room temperature (room temperature, about 20 to 30 ° C., typical temperature is 25 ° C.). If the second resin portion 7 has an elastic modulus of 1000 MPa or more at normal temperature, the impact resistance of the RF power module 1 and a mobile phone (electronic device) using the RF power module 1 can be improved more accurately.

  Thus, in the RF power module 1 of the present embodiment, the elastic modulus of the second resin portion 7 is larger than the elastic modulus of the first resin portion 6, and the first resin portion 6 has a low elastic modulus. Thus, short-circuiting between terminals (solder flash) due to solder expansion during secondary mounting (solder reflow process in step S14) is prevented, and the second resin portion 7 has a higher elastic modulus than the first resin portion. Thus, resistance to physical impact such as dropping can be improved. As a result, the reliability of the electrical connection of the RF power module 1 is improved (or the reliability of secondary mounting is improved), and the RF power module 1 and the physical use of the electronic device (mobile phone) using (mounting) it are used. It is possible to improve both resistance to impact.

  Further, as described above, when the solder bump 5 is re-melted and changes from a solid (solid phase) state to a liquid (liquid phase) state in the solder reflow process of step S14, the volume of the solder bump 5 expands. The volume expansion due to the change in the phase state causes a short circuit between the terminals. The reason why the first resin portion 6 has a low elastic modulus is that the volume expansion at the time of remelting of the solder bump 5 is absorbed by the first resin portion 6, so the first resin at the melting point (melting point temperature) of the solder bump 5. The elastic modulus of the portion 6 needs to be smaller than the elastic modulus of the second resin portion 7 at the melting point (melting point temperature) of the solder bump 5. The reason why the second resin part 7 is made to have a high elastic modulus is to increase the impact resistance during actual use. Therefore, the elastic modulus of the second resin part 7 at room temperature, which is the actual use temperature, is It is necessary to be larger than the elastic modulus of one resin part 6. Therefore, in the present embodiment, the elastic modulus of the second resin portion 7 is larger than the elastic modulus of the first resin portion 6, but at least the elastic modulus of the second resin portion 7 at normal temperature is that of the first resin portion 6. The elastic modulus of the first resin portion 6 at the melting point of the solder bump 5 needs to be larger than the elastic modulus at room temperature and smaller than the elastic modulus of the second resin portion 7 at the melting point of the solder bump 5.

  Unlike the present embodiment, when the second resin material 7a is supplied in a state where the first resin portion 6 is not formed, the second resin material 7a reaches the periphery of the solder bump 5 and is adjacent to the second resin material 7a. There is a possibility that the space between the solder bumps 5 to be filled is filled with the second resin material 7a. In this case, since the second resin portion 7 having a high elastic modulus is formed so as to fill between the adjacent solder bumps 5, the solder reflow in step 14 for mounting the RF power module 1 on the mounting substrate 31. If the solder bumps 5 in the RF power module 1 are remelted at this time, the volume expansion due to the melting of the solder bumps 5 cannot be absorbed by the high-elasticity resin, and a short circuit between terminals (solder flash) may occur due to the solder expansion. is there.

  In contrast, in the present embodiment, the first resin portion 6 that fills the space between the adjacent solder bumps 5 is formed first, and then the second resin material 7a for forming the second resin portion 7 is supplied in step S7. Thus, the second resin portion 7 is formed. For this reason, the second resin material 7a supplied in step S7 does not reach the periphery of the solder bump 5, and the second resin material 7a can be prevented from entering between the adjacent solder bumps 5. Therefore, the space between the adjacent solder bumps 5 is prevented from being filled with the second resin portion 7 having a high elastic modulus, and the space between the adjacent solder bumps 5 is filled with the first resin portion 6 having a low elastic modulus. Therefore, even if the solder bumps 5 are remelted during the solder reflow in step 14 for mounting the RF power module 1 on the mounting substrate 31, a short circuit (solder flash) between the terminals due to solder expansion is prevented. be able to.

  The first resin portion 6 is filled between the plurality of solder bumps 5 (between adjacent solder bumps 5), but the first resin portion 6 is between the surface 2 a of the semiconductor chip 2 and the upper surface 3 a of the wiring substrate 3. It is more preferable that the resin portion 6 is filled so that no voids (spaces or gaps) are formed between the surface 2 a of the semiconductor chip 2 and the upper surface 3 a of the wiring substrate 3. This prevents the gas (air) in the void surrounded by the resin portion from expanding and adversely affecting the solder reflow in step 14 for mounting the RF power module 1 on the mounting substrate 31. Can do.

  FIG. 22 is a graph (characteristic diagram) showing an example of the temperature characteristic of the resin used for the first resin portion 6 and the second resin portion 7. The horizontal axis of the graph in FIG. 22 corresponds to the temperature, and the vertical axis corresponds to the elastic modulus. The graph of FIG. 22 shows the temperature dependence of the elastic modulus of one type of silicone resin A and four types of epoxy resins B, C, D, and T.

  If the elastic modulus of the second resin portion 7 is larger than that of the first resin portion 6, the effect of preventing a short circuit between terminals (solder flash) due to volume expansion due to remelting of the solder bump 5 at the time of secondary mounting, It is possible to obtain an effect of improving impact resistance. For this reason, among the five types of resins shown in FIG. 22, for example, when the first resin portion 6 is formed from the low-elasticity silicone resin A and the second resin portion 7 is formed from the epoxy resins B, C, and D It is also effective when the first resin portion 6 is formed of the low elasticity epoxy resins B, C, and D and the second resin portion 7 is formed of the high elasticity epoxy resin T. Alternatively, it is effective even when the first resin portion 6 is formed of the epoxy resin C and the second resin portion 7 is formed of the epoxy resin D.

  However, the lower the elastic modulus of the first resin portion 6 at the temperature at which the solder bump 5 is re-melted by the solder reflow (second solder reflow in step S14) at the time of secondary mounting (the melting point of the solder bump 5), the lower the resistance. The effect of preventing the short circuit between the terminals (solder flash) is large, and the higher the elastic modulus of the second resin portion 7 at room temperature in actual use, the greater the effect of improving the impact resistance. For this reason, among the five types of resins shown in FIG. 22, the first resin portion 6 is formed with the lowest elastic silicone resin A, and the second resin portion 7 is formed with the highest elastic epoxy resin T. This is more preferable because the effect of preventing a short circuit between terminals due to the volume expansion due to remelting of the solder bump 5 at the time of secondary mounting and the effect of improving the impact resistance are maximized.

  In addition, since the present embodiment can prevent a short circuit between terminals due to volume expansion due to remelting of the solder bump 5, during the solder reflow process of step S14 for mounting the RF power module 1 on the mounting substrate 31. When the solder bump 5 is melted (remelted), that is, when the solder reflow temperature (maximum temperature) in step S14 is higher than the melting point of the solder bump 5, the effect is great.

  Further, lead (Pb) -free solder tends to have a higher melting point than lead-containing solder, and when lead (Pb) -free solder is used as the solder 34 (solder for mounting on the mounting substrate 31), a step is performed. It is necessary to increase the temperature (maximum temperature) of S14 solder reflow (secondary mounting solder reflow) (for example, about 260 ° C.). For this reason, the solder bumps 5 are likely to be remelted during the solder reflow in step S14, but by applying this embodiment, it is possible to prevent a short circuit between the terminals due to volume expansion due to the remelting of the solder bumps 5. Therefore, if this embodiment is applied when lead (Pb) -free solder is used as the solder 34, the effect is greater.

(Embodiment 2)
FIG. 23 is a cross-sectional view (side cross-sectional view) of the semiconductor device 1a of the present embodiment, and corresponds to FIG. 4 of the first embodiment.

  The RF power module 1a, which is the semiconductor device of the present embodiment, except that the third resin portion 8 is formed on the upper surface 3a of the wiring board 3 so as to cover the semiconductor chip 2 and the passive component 4. It has substantially the same configuration as the RF power module 1 of the first embodiment. For this reason, the description of the configuration other than the third resin portion 8 is omitted here.

  The 3rd resin part 8 consists of resin materials, and can also contain a filler etc. Silica or the like can be used as the filler. The resin material constituting the third resin portion 8 is more preferably a thermosetting resin material, and more preferably a silicone resin. In the present embodiment, the elastic modulus of the third resin 8 is smaller than the elastic modulus of the second resin 7. By using different resin materials for the resin material constituting the third resin portion 8 and the resin material constituting the second resin portion 7, the elastic modulus of the third resin 8 is higher than the elastic modulus of the second resin 7. Can be small. For example, the third resin having an elastic modulus smaller than that of the second resin 7 by using an epoxy resin as the resin material constituting the second resin portion 7 and using a silicone resin as the resin material constituting the third resin portion 8. 8 can be formed easily.

  Thus, in the present embodiment, the sealing resin has a triple structure of the first resin portion 6 with low elasticity, the second resin portion 7 with high elasticity, and the third resin portion 8 with low elasticity. The elastic modulus of the second resin portion 7 is larger than the elastic modulus of the first resin portion 6, and the elastic modulus of the third resin portion 8 is smaller than the elastic modulus of the second resin portion 7.

  In order to manufacture the RF power module 1a of the present embodiment, the same processes as steps S1 to S8 of the first embodiment are performed to obtain the structure of FIG. The third resin material 8a for forming the third resin portion 8 is supplied (applied, arranged, formed) on the upper surface 3a of the wiring board 3 so as to cover the surface.

  Next, baking treatment (heat treatment, heat treatment for resin curing) is performed to cure the third resin material 8a to form the eighth resin portion 8. As described above, since the third resin material 8a is made of a thermosetting resin, the third resin material 8a is cured by the baking process, so that the cured third resin portion 8 is obtained. As described above, since the third resin material 8 a is disposed on the upper surface 3 a of the wiring substrate 3 so as to cover the semiconductor chip 2 and the passive component 4, the third resin portion 8 is connected to the semiconductor chip 2. It is formed on the upper surface 3 a of the wiring board 3 so as to cover the passive component 4.

  The material constituting the third resin material 8a is adjusted so that the elastic modulus of the third resin portion 8 after curing is smaller than the elastic modulus of the second resin portion 7 after curing. The preferable range of the elastic modulus of the third resin portion 8 after curing will be described in detail later.

  In this way, the RF power module 1a of the present embodiment as shown in FIG. 23 is manufactured. When manufacturing a plurality of RF power modules 1a from a single wiring board 3, after hardening the third resin material 8a (forming the third resin portion 8) by baking, the wiring board 3 is placed at a predetermined position. The RF power module 1a as each piece can be obtained by dividing (cutting).

  Also, the RF power module 1a of the present embodiment can be mounted on the mounting substrate 31 in the same manner as the RF power module 1 (steps S11 to S14) of the first embodiment.

  In the present embodiment, in addition to being able to obtain substantially the same effects as in the first embodiment, the following effects can be further obtained.

  Unlike the present embodiment, when the third resin portion 8 is formed of a resin having a high elastic modulus similar to that of the second resin portion 7, the solder in step S14 for mounting the RF power module 1a on the mounting substrate 31 is used. When the solder 17 for mounting the passive component 4 is remelted during reflow, the highly elastic third resin portion 8 cannot absorb the volume expansion due to the melting of the solder 17 and short-circuits between terminals due to the solder expansion (solder flash). May occur. That is, if the elastic modulus of the third resin part 3 is high, even if the solder 17 is remelted and the volume expands, the highly elastic third resin part 8 cannot contract by the amount of the expansion volume, The interface between the third resin portion 8 and the wiring board 3 or the passive component 4 is peeled off by the melt expansion pressure of the solder 17, and the melted solder flows in a flash shape, and between the electrodes of the passive component 4 or on the adjacent substrate side There is a possibility of causing a short circuit between the terminals 12b.

  In contrast, in the present embodiment, the third resin portion 8 that covers the semiconductor chip 2 and the passive component 4 is formed of a resin having a lower elastic modulus than the second resin portion 7. For this reason, even if the solder 17 for mounting the passive component 4 is remelted during the solder reflow in step S14 for mounting the RF power module 1a on the mounting substrate 31, the third resin portion 8 having a low elastic modulus is Since the volume expansion due to the melting of the solder 17 can be absorbed, it is possible to prevent a short circuit between the electrodes of the passive component 4 or the adjacent substrate side terminals 12b due to the solder expansion.

  For this reason, it is preferable that the third resin portion 8 is a low elastic modulus resin like the first resin portion 6, and in particular, solder reflow for mounting the RF power module 1a on the mounting substrate 31 (step S14 above). ) Is preferably low elastic modulus. In other words, the elastic modulus of the third resin portion 8 is preferably low at the melting point of the solder 17 that is the temperature at which the solder 17 is remelted at the time of solder reflow in step S14 or at a temperature equal to or higher than the melting point. Therefore, in the present embodiment, the elastic modulus of the third resin portion 8 is smaller than that of the second resin portion 7, but at least the elastic modulus of the third resin portion 8 at the melting point of the solder 17 is equal to that of the melting point of the solder 17. 2 It is necessary to be smaller than the elastic modulus of the resin portion 7. More specifically, considering the temperature of secondary reflow (solder reflow in step S14) and the conditions during high temperature application of the temperature cycle test, the third resin portion 8 has a pressure of 1 to 1000 MPa at a temperature of 150 ° C. or higher. It is more preferable if it has an elastic modulus (1 MPa or more and 1000 MPa or less), and even more preferable if it has an elastic modulus of 1 to 200 MPa (1 MPa or more and 200 MPa or less) at a temperature of 150 ° C. or more. If the third resin part 8 has a modulus of elasticity of preferably 1000 MPa or less, more preferably 200 MPa or less at a temperature of 150 ° C. or higher, the third resin part 8 can further expand its volume due to remelting of the solder 17. It can absorb accurately and can prevent more precisely that the short circuit between terminals by solder expansion arises. Moreover, if the 3rd resin part 8 has the elasticity modulus of 1 Mpa or more in the temperature of 150 degreeC or more, the protection function of the passive component 4 and the semiconductor chip 2 by the 3rd resin part 8 is securable. Further, if the first resin material 6a (first resin portion 6) and the third resin material 8a (third resin portion 8), which are required to have a low elastic modulus, are made of the same material (resin material), the semiconductor device 1a. Can be made more rationally or efficiently.

  In addition, the dimension of the connection region via the solder 17 between the electrode of the passive component 4 and the board side terminal 12 b of the wiring board 3 is larger than the dimension of the solder bump 5, and the passive component 4 is firmly fixed by the solder 17. It is fixed to the wiring board 4. For this reason, the connection by the solder 17 between the electrode of the passive component 4 and the board | substrate side terminal 12b of the wiring board 3 is maintained, even if impact, such as dropping, is given to RF power module 1a or a mobile phone using the same. Even if the third resin portion 8 has a low elastic modulus, the reliability of the electrical connection between the electrode of the passive component 4 and the board-side terminal 12b of the wiring board 3 is not lowered.

  Further, in the RF power module 1a of the present embodiment, since the third resin portion 8 is formed on the upper surface 3a of the wiring board 3 so as to cover the semiconductor chip 2 and the passive component 4, the RF power module 1a Can be picked up, the upper surface 8b of the third resin portion 8 can be adsorbed. FIG. 24 is a cross-sectional view schematically showing a state in which the RF power module 1a is adsorbed by the pickup nozzle (adsorption nozzle) 40. By providing the third resin portion 8, as shown in FIG. 24, the RF power module 1 a can be picked up by adsorbing the wide upper surface 8 b of the third resin portion 8 with the pickup nozzle 40. . For this reason, when the RF power module 1a is mounted on the mounting substrate 31, the RF power module 1a can be easily picked up.

  In addition, since the third resin portion 8 is provided, marking can be performed on the wide upper surface 8b of the third resin portion 8, so that the production number and the like can be easily assigned to the RF power module 1a.

  Further, the present embodiment is not only short-circuited between terminals due to volume expansion due to remelting of solder bumps 5 but also short-circuited between terminals due to volume expansion due to remelting of solder 17 for mounting passive component 4. Can be prevented. Therefore, when the solder bump 5 and the solder 17 for mounting the passive component 4 are melted (remelted) during the solder reflow process of step S14 for mounting the RF power module 1a on the mounting substrate 31, that is, step If the present embodiment is applied when the solder reflow temperature (maximum temperature) in S14 is higher than both the melting point of the solder bump 5 and the melting point of the solder 17 for mounting the passive component 4, the effect is greater. As in the first embodiment, if this embodiment is applied when lead (Pb) -free solder is used as the solder 34, the effect is greater.

(Embodiment 3)
FIG. 25 is a cross-sectional view (side cross-sectional view) of the semiconductor device 1b of the present embodiment, and corresponds to FIG. 4 of the first embodiment.

  As shown in FIG. 25, in the RF power module 1b which is the semiconductor device of the present embodiment, a metal cap 41 for heat dissipation is mounted on the upper surface 3a of the wiring board 3 so as to cover the semiconductor chip 2. .

  A part of the bottom of the metal cap 41 is connected to the board-side terminal 12c of the wiring board 3 (the board-side terminal 12c to be connected to the metal cap 41 of the board-side terminal 12) via a conductive bonding material 42 (for example, solder). The back surface 2 b of the semiconductor chip 2 is bonded to the inner surface of the ceiling portion of the metal cap 41 via a conductive bonding material 43. Thereby, the heat of the semiconductor chip 2 can be conducted (heat radiation) from the back surface 2 b of the semiconductor chip 2 to the wiring substrate 3 through the metal cap 41. As shown in FIG. 25, when the back electrode 2d is formed on the back surface 2b of the semiconductor chip 2, a predetermined potential can be supplied to the back electrode 2d of the semiconductor chip 2 through the metal cap 41. it can. For example, the reference potential supplied from the reference potential supply terminal 13 a on the lower surface 3 b of the wiring substrate 3 is connected to the back electrode of the back surface 2 b of the semiconductor chip 2 via the substrate-side terminal 12 c on the upper surface 3 a of the wiring substrate 3 and the metal cap 41. 2d.

  Since the other configuration of the RF power module 1b is substantially the same as that of the RF power module 1 of the first embodiment, the description thereof is omitted here.

  In addition, after performing the process similar to step S1-S8 of the said Embodiment 1, and obtaining the structure of the said FIG. 16, the metal cap 20 is mounted on the wiring board 3 like FIG. The RF power module 1b of the embodiment can be manufactured.

  Further, the RF power module 1b of the present embodiment can also be mounted on the mounting substrate 31 in the same manner as the RF power module 1 (steps S11 to S14) of the first embodiment.

  In the present embodiment, in addition to being able to obtain substantially the same effects as in the first embodiment, the following effects can be further obtained.

  Since the heat of the semiconductor chip 2 can be conducted (heat radiation) from the back surface 2b of the semiconductor chip 2 to the wiring substrate 3 through the metal cap 20, the heat radiation characteristics of the RF power module 1b can be further improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above description, the case where the invention made mainly by the present inventor is applied to the RF power module, which is the field of use as the background, has been described. However, the present invention is not limited to this and can be applied in various ways. The present invention can be applied to various semiconductor devices in which a semiconductor chip is connected to a wiring board through solder bumps and manufacturing techniques thereof. Further, when applied to a semiconductor device used for a mobile phone, the effect is particularly great.

  The present invention is suitable for application to a semiconductor device in which a semiconductor chip is connected to a wiring board via solder bumps and a manufacturing technique thereof.

It is a circuit block diagram of the amplifier circuit which comprises the RF power module which is one embodiment of this invention. It is explanatory drawing of an example of the digital mobile telephone system using the RF power module which is one embodiment of this invention. It is a top view of RF power module which is one embodiment of the present invention. It is sectional drawing of the RF power module which is one embodiment of this invention. It is principal part sectional drawing of a semiconductor chip at the time of forming a semiconductor amplifier element by LDMOSFET. It is principal part sectional drawing of the semiconductor chip at the time of forming a semiconductor amplifier element with a heterojunction bipolar transistor. It is a manufacturing process flowchart which shows the manufacturing process of RF power module of one embodiment of this invention. It is principal part sectional drawing in the manufacturing process of RF power module which is one embodiment of this invention. FIG. 9 is a fragmentary cross-sectional view of the RF power module during the manufacturing process following that of FIG. 8; FIG. 10 is a fragmentary cross-sectional view of the RF power module during a manufacturing step following that of FIG. 9; It is a principal part top view in the manufacturing process of the RF power module following FIG. It is principal part sectional drawing in the manufacturing process of the same RF power module as FIG. It is a principal part top view in the manufacturing process of the RF power module following FIG. It is principal part sectional drawing in the manufacturing process of the same RF power module as FIG. FIG. 15 is a fragmentary cross-sectional view of the RF power module during a manufacturing step following that of FIG. 14; FIG. 16 is a fragmentary cross-sectional view of the RF power module during a manufacturing step following that of FIG. 15; It is a mounting process flow figure which shows the mounting process of RF power module of one embodiment of this invention. It is principal part sectional drawing in the mounting process of RF power module which is one embodiment of this invention. FIG. 19 is a fragmentary cross-sectional view of the RF power module subsequent to FIG. 18 during the mounting step. FIG. 20 is an essential part cross-sectional view of the RF power module during the mounting process following FIG. 19; It is principal part sectional drawing in the mounting process of the RF power module following FIG. It is a graph which shows an example of the temperature characteristic of resin. It is sectional drawing of the RF power module which is other embodiment of this invention. It is sectional drawing which shows the state which adsorb | sucked the RF power module of FIG. It is sectional drawing of the RF power module which is further another embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 RF power module 1a RF power module 1b RF power module 2 Semiconductor chip 2a Front surface 2b Back surface 2c Side surface 2d Back surface electrode 3 Wiring board 3a Upper surface 3b Lower surface 4 Passive component 5 Solder bump 6 1st resin part 6a 1st resin material 7 2nd Resin portion 7a Second resin material 8 Third resin portion 8a Third resin material 11 Insulator layers 12, 12a, 12b, 12c Substrate side terminal 13 External connection terminal 13a Reference potential supply terminal 17 Solder 21 Solder 22 Resin injection nozzle 24 Resin injection nozzle 31 Mounting substrate 31a Main surface 33, 33a Substrate side terminal 34 Solder 40 Pickup nozzle 41 Metal cap 42 Joining material 43 Joining material 102A, 102B Power amplification circuit 102A1, 102A2, 102A3, 102B1, 102B2, 102B3 Amplifying stage 102AM1 , 10 2AM2, 102BM1, 102BM2 Matching circuit 103 Peripheral circuit 103A Control circuit 103A1 Power supply control circuit 103A2 Bias voltage generation circuit 103B Bias circuit 104a, 104b Input terminal 105A, 105B Matching circuit 106a, 106b Output terminal 107A, 107B Matching circuit 108A, 108B Low pass filter 151 Front-end module 152 Baseband circuit 153 Modulation / demodulation circuit FLT1, FLT2 Filter 154a Switch circuit 154b Switch circuit 156 Demultiplexer 201 Semiconductor substrate 202 Epitaxial layer 203 Groove 204 P-type punching layer 205 Element isolation region 206 P-type well 207 Gate Insulating film 208 Gate electrode 209 n ⁻ type offset drain region 210 n ⁻ type source region 211 Rs 212 n-type offset drain region 213 n ⁺ -type drain region 214 n ⁺ -type source region 215 p ⁺ -type semiconductor region 221 insulating film 222 contact hole 223 plug 224 wiring 224a source electrode 224b drain electrode 225 insulating film 226 through-hole 227 plug 228 Wiring 229 Surface protective film 230 Opening 231 UBM film 232 Solder bump 233 Back electrode 251 GaAs substrate 252 Subcollector layer 253 HBT
254 Collector electrode 255 Collector mesa 256 Base mesa 257 Base electrode 258 Emitter layer 259 Emitter electrode 261 Insulating film 262 Contact hole 263 Collector wiring 264 Insulating film 265 Through hole 266 Emitter wiring C5, C6 Capacitor CNT1, CNT2 Switching signal DPS Digital mobile phone system FLT1, FLT2 Filter MB Motherboard

Claims (20)

A wiring board having a plurality of first electrodes on the first main surface, and having a plurality of second electrodes for external connection on the second main surface opposite to the first main surface;
A semiconductor chip mounted on the first main surface of the wiring board and electrically connected to the plurality of first electrodes of the wiring board via a plurality of solder bumps;
A first resin filled between the plurality of solder bumps;
A second resin for fixing between a side surface of the semiconductor chip and the first main surface of the wiring board;
Have
A semiconductor device, wherein the elastic modulus of the second resin is larger than the elastic modulus of the first resin. The semiconductor device according to claim 1,
The semiconductor device, wherein the solder bump is made of lead-free solder. The semiconductor device according to claim 2,
The semiconductor device is characterized in that the solder bump is Sn-Ag-Cu solder. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first resin has an elastic modulus of 1 MPa to 1000 MPa at a temperature of 150 ° C. or higher. The semiconductor device according to claim 1,
The semiconductor device, wherein the second resin has an elastic modulus of 1000 MPa or more at room temperature. The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the first resin is made of a silicone resin, and the second resin is made of an epoxy resin. The semiconductor device according to claim 1,
A semiconductor device, wherein solder can be formed on the plurality of second electrodes of the wiring board. The semiconductor device according to claim 1,
The semiconductor device further comprising a passive component mounted on the first main surface of the wiring board via solder. The semiconductor device according to claim 8.
A semiconductor device, further comprising a third resin that covers the semiconductor chip and the passive component. The semiconductor device according to claim 9.
The semiconductor device, wherein the elastic modulus of the third resin is smaller than the elastic modulus of the second resin. The semiconductor device according to claim 1,
The semiconductor device is used for a mobile phone. The semiconductor device according to claim 1,
The elastic modulus of the second resin at normal temperature is larger than the elastic modulus of the first resin at normal temperature,
The semiconductor device, wherein an elastic modulus of the first resin at a melting point of the solder bump is smaller than an elastic modulus of the second resin at the melting point of the solder bump. (A) A semiconductor chip having a plurality of solder bumps, and a plurality of first electrodes to be connected to the plurality of solder bumps of the semiconductor chip, respectively, on the first main surface, opposite to the first main surface Preparing a first wiring board having a plurality of second electrodes for external connection on the second main surface;
(B) The semiconductor chip is mounted on the first main surface of the first wiring board, and the plurality of solder bumps of the semiconductor chip are electrically connected to the plurality of first electrodes of the first wiring board. The process of
(C) filling a first resin between the plurality of solder bumps;
(D) a step of forming a second resin between the side surface of the semiconductor chip and the first main surface of the first wiring substrate after the step (c);
Have
A method of manufacturing a semiconductor device, wherein the elastic modulus of the second resin is larger than the elastic modulus of the first resin. 14. The method of manufacturing a semiconductor device according to claim 13,
(E) preparing a second wiring board having a plurality of third electrodes on the main surface;
(F) After the step (d), disposing the plurality of second electrodes of the first wiring substrate on the plurality of third electrodes of the second wiring substrate via a first solder;
(G) Reflowing the first solder to electrically connect the plurality of third electrodes of the second wiring board and the plurality of second electrodes of the first wiring board via the first solder. Connecting to,
A method for manufacturing a semiconductor device, further comprising: 15. The method of manufacturing a semiconductor device according to claim 14,
The method for manufacturing a semiconductor device, wherein the solder is lead-free solder. 15. The method of manufacturing a semiconductor device according to claim 14,
The method of manufacturing a semiconductor device, wherein the solder bumps are also melted in the reflow process of the step (g). 14. The method of manufacturing a semiconductor device according to claim 13,
After the step (a), before the step (c),
(B1) mounting a passive component on the first main surface of the first wiring board via a second solder;
A method for manufacturing a semiconductor device, further comprising: The method of manufacturing a semiconductor device according to claim 17.
After the step (d),
(D1) forming a third resin on the first main surface of the wiring board so as to cover the semiconductor chip and the passive component;
A method for manufacturing a semiconductor device, further comprising: The method of manufacturing a semiconductor device according to claim 18.
The method of manufacturing a semiconductor device, wherein the elastic modulus of the third resin is smaller than the elastic modulus of the second resin. In the manufacturing method of the semiconductor device according to claim 19,
(E) preparing a second wiring board having a plurality of third electrodes on the main surface;
(F) After the step (d), disposing the plurality of second electrodes of the first wiring substrate on the plurality of third electrodes of the second wiring substrate via a first solder;
(G) Reflowing the first solder to electrically connect the plurality of third electrodes of the second wiring board and the plurality of second electrodes of the first wiring board via the first solder. Connecting to,
Further comprising
The method of manufacturing a semiconductor device, wherein the solder bump and the second solder are also melted by the reflow process in the step (g).

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