Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
  • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/213—Channel regions of field-effect devices
  • H10D62/221—Channel regions of field-effect devices of FETs
  • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
  • H10D62/314—Channel regions of field-effect devices of FETs of IGFETs having vertical doping variations 

Definitions

• the present invention relates to a semiconductor device having a gate electrode and a pair of impurity expansion regions (source Z drain), and is particularly suitable for application to a MOS transistor.
• an epi-channel structure has been proposed in which a non-doped silicon layer is epitaxially grown on a silicon substrate into which impurities are uniformly introduced to form a channel layer.
• This epi-channel structure with two levels of impurity concentration makes it possible to achieve high short channel resistance and prevent impurity scattering.
• Patent Document 1 Japanese Patent Laid-Open No. 11 260828
• the present invention has been made in view of the above-described problems, and suppresses a short channel effect that does not cause unnecessary diffusion of impurities during impurity activation and suppresses an increase in threshold voltage. It is an object of the present invention to provide a highly reliable semiconductor device and a manufacturing method thereof that can secure mobility and meet the demand for further miniaturization and miniaturization.
• a semiconductor device of the present invention includes a gate electrode formed on a semiconductor region of a substrate via a gate insulating film, and a first conductive type first electrode at portions corresponding to both sides of the gate electrode of the semiconductor region.
• the semiconductor region has at least a two-layer channel layer having a lower layer and an upper layer in an upper layer portion thereof, and the first layer is formed in the lower layer of the channel layer.
• a second conductivity type second impurity which is a reverse conductivity type of the first impurity is introduced, and the channel layer has a function of making the semiconductor region amorphous from the upper layer to the lower layer
• An impurity layer containing an amorphizing impurity is included, and the impurity diffusion region is included in the impurity layer.
• the lowermost surface of the impurity layer is formed in the lower layer of the channel layer.
• the amorphized impurity is at least one selected from the group consisting of Ge, Si, and inert gas.
• a crystal defect is formed on the lowermost surface of the impurity layer, and the impurity diffusion region and the crystal defect are separated from each other.
• the crystal defect is formed below the depletion layer of the semiconductor device.
• the lower layer of the channel layer has a portion where the concentration of the amorphizing impurity (eg, Ge) is 1 ⁇ 10 18 Zcm 3 ,
• the concentration of the second impurity in the part is 1 ⁇ 10 18 Zcm 3 or more.
• the upper layer of the channel layer contains only the amorphizing impurity. In one aspect of the semiconductor device of the present invention, the upper layer of the channel layer contains the first conductivity type impurity and the second conductivity type impurity in addition to the amorphization impurity. It is.
• the substrate has the semiconductor region on an insulating layer.
• the substrate has the semiconductor region on a glass substrate with an insulating layer interposed therebetween.
• a method 1 for manufacturing a semiconductor device of the present invention includes a step of introducing a second impurity of a second conductivity type, which is a reverse conductivity type of the first impurity, into a surface layer of a semiconductor region of a substrate; Depositing and forming a silicon film at a low temperature, introducing an amorphized impurity into a surface layer of the semiconductor region including the silicon film and the introduction site of the second impurity, and the silicon film and the second impurity A step of amorphizing the surface layer of the semiconductor region including the introduction site of the silicon, and annealing to form a single crystal of the surface layer of the semiconductor region including the silicon film and the second impurity introduction site.
• the semiconductor device manufacturing method 2 of the present invention includes a step of introducing a second impurity of a second conductivity type, which is a reverse conductivity type of the first impurity, into the surface layer of the semiconductor region of the substrate; Introducing an amorphous impurity into a surface layer of the semiconductor region of the substrate so as to include an impurity introduction site, and amorphizing the surface layer of the semiconductor region; and the amorphous semiconductor region
• the first impurity of the first conductivity type is introduced into the upper portion of the surface layer of the semiconductor layer, and the amorphous surface layer of the semiconductor region is single-crystallized by annealing, and the amorphous region in the semiconductor region is converted to the amorphous state.
• the lowermost surface of the surface layer of the semiconductor region that is monocrystallized is formed in the lower layer of the channel layer.
• the amorphized impurity is at least one selected from the group consisting of Ge, Si, and inert gas.
• a crystal defect is formed in the lower layer of the channel layer of the single-crystallized semiconductor region, and the impurity diffusion region is formed in the semiconductor layer. It is formed so as to be separated from the crystal defects.
• the crystal defect is formed below a depletion layer of the semiconductor device.
• the impurity layer has an amorphized impurity (eg, Ge) concentration of 1 ⁇ 10 18 Zcm 3 in the impurity layer. It is formed so as to have a certain part and the concentration of the second impurity in the part is 1 ⁇ 10 18 Zcm 3 or more.
• amorphized impurity eg, Ge
• the annealing treatment is performed at a temperature of 700 ° C. or lower.
• the substrate has the semiconductor region on the insulating layer.
• the substrate includes the semiconductor region on a glass substrate with an insulating layer interposed therebetween.
• FIG. 1A is a schematic cross-sectional view illustrating a method of manufacturing a p-type Si transistor according to the first embodiment in the order of steps.
• FIG. 1B is a schematic cross-sectional view showing the method of manufacturing the p-type Si transistor according to the first embodiment in the order of steps.
• FIG. 1C is a schematic cross-sectional view showing a method of manufacturing the p-type Si transistor according to the first embodiment in the order of steps.
• Diagram ID is a schematic cross-sectional view showing the method of manufacturing the p-type Si transistor according to the first embodiment in the order of steps.
• FIG. 1E is a schematic cross-sectional view showing the method of manufacturing the p-type Si transistor according to the first embodiment in the order of steps.
• FIG. 1F is a schematic cross-sectional view showing the method of manufacturing the p-type Si transistor according to the first embodiment in the order of steps.
• FIG. 2A is a schematic cross-sectional view showing a method of manufacturing an n-type Si transistor according to Modification 1 of the first embodiment in the order of steps.
• FIG. 2B is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 1 of the first embodiment in the order of steps.
• FIG. 2C is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to the first modification of the first embodiment in the order of steps.
• FIG. 2D is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 1 of the first embodiment in the order of steps.
• FIG. 2E is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 1 of the first embodiment in the order of steps.
• FIG. 2F is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 1 of the first embodiment in the order of steps.
• FIG. 3A is a schematic cross-sectional view showing a method of manufacturing an n-type Si transistor according to Modification 2 of the first embodiment in the order of steps.
• FIG. 3B is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the first embodiment in the order of steps.
• FIG. 3C is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to the second modification example in the first embodiment in the order of steps.
• FIG. 3D is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the first embodiment in the order of steps.
• FIG. 3E is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the first embodiment in the order of steps.
• FIG. 3F is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the first embodiment in the order of steps.
• FIG. 4A is a schematic cross-sectional view showing a method of manufacturing an n-type Si transistor according to the second embodiment in the order of steps.
• FIG. 4B is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to the second embodiment in the order of steps.
• FIG. 4C is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to the second embodiment in the order of steps.
• FIG. 4D is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to the second embodiment in the order of steps.
• FIG. 4E is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to the second embodiment in the order of steps.
• FIG. 4F is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to the second embodiment in the order of steps.
• FIG. 5 is a characteristic diagram showing a boron concentration profile in the lower layer of the channel layer of the Si transistor according to the second embodiment.
• FIG. 6A is a schematic cross-sectional view showing a method of manufacturing an n-type Si transistor according to Modification 1 of the second embodiment in the order of steps.
• FIG. 6B is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 1 of the second embodiment in the order of steps.
• FIG. 6C is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 1 of the second embodiment in the order of steps.
• FIG. 6D is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 1 of the second embodiment in the order of steps.
• FIG. 6E is a schematic cross-sectional view showing a method of manufacturing an n-type Si transistor according to Modification 1 of the second embodiment in the order of steps.
• FIG. 6F is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 1 of the second embodiment in the order of steps.
• FIG. 7A is a schematic cross-sectional view showing a method for manufacturing an n-type Si transistor according to Modification 2 of the second embodiment in the order of steps.
• FIG. 7B is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the second embodiment in the order of steps.
• FIG. 7C is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the second embodiment in the order of steps.
• FIG. 7D is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the second embodiment in the order of steps.
• FIG. 7E is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the second embodiment in the order of steps.
• FIG. 7F is a schematic cross-sectional view showing the method of manufacturing the n-type Si transistor according to Modification 2 of the second embodiment in the order of steps.
• the present inventor has a channel portion between impurity diffusion regions (source Z drain) in a semiconductor device such as a Si transistor such as a MOSFET having a lower layer impurity concentration of at least a two-layer structure, and the impurity in the lower layer portion.
• a semiconductor device such as a Si transistor such as a MOSFET having a lower layer impurity concentration of at least a two-layer structure, and the impurity in the lower layer portion.
• FIGS. 1A to 1F are schematic cross-sectional views illustrating a method of manufacturing a p-type Si transistor according to the first embodiment in the order of steps.
• a source Z drain (described later) is formed on the surface layer of a Balta type n type silicon substrate 1 containing about 1 ⁇ 10 15 Zcm 3 of n type impurities, for example, as shown in FIG. 1A.
• Impurities for example, p-type, here boron (B)
• impurities of the opposite conductivity type for example, n-type, here phosphorus (P)
• annealing is performed at 900 ° C.
• the introduced phosphorus is activated to form the reverse conductivity type impurity layer 2 having a uniform impurity distribution.
• the impurity (phosphorus) concentration of the reverse conductivity type impurity layer 2 is, for example, about 3 ⁇ 10 18 Zcm 3 .
• the reverse conductivity type impurity layer 2 may be formed so that the impurity concentration gradually changes in the depth direction.
• the surface layer of the silicon substrate 1 serving as the channel layer is not yet formed in a two-layer structure, there is no problem in performing high-temperature annealing. Thereafter, the surface of the silicon substrate 1 is cleaned by performing an ammonia overwater boil treatment, a hydrofluoric acid treatment, a hydrochloric acid overwater boil treatment and a hydrofluoric acid treatment.
• a non-doped silicon film here an amorphous silicon film 3 is formed to a thickness of, for example, about 50 nm on the silicon substrate 1 by a low temperature film formation method, here, a plasma CVD method.
• a low temperature film formation method here, a plasma CVD method.
• the process is a low temperature of 700 ° C or lower, for example, a low temperature process of about 300 ° C, phosphorus, which is an impurity, diffuses from the reverse conductivity type impurity layer 2 formed on the surface layer of the silicon substrate 1 to the amorphous silicon film 3.
• phosphorus which is an impurity
• the region including the amorphous silicon film 3 and the reverse conductivity type impurity layer 2 on the surface of the silicon substrate 1 has a function of making silicon constituting the semiconductor region amorphous.
• Inject heavy atoms here germanium (Ge).
• germanium here germanium (Ge).
• an inert gas such as silicon (Si) or argon (Ar) may be used instead of germanium.
• the implantation is performed under the condition that germanium reaches from the amorphous silicon film 3 into the reverse conductivity type impurity layer 2, for example, the condition that the speed energy is 100 keV and the dose is 1 ⁇ 10 15 / cm 2 .
• an amorphous state is formed from the surface of the amorphous silicon film 3 including the reverse conductivity type impurity layer 2 of the silicon substrate 1 to a depth of, for example, about lOOnm.
• this amorphized impurity layer (including the amorphous silicon film 3) is shown as a Ge injection layer 4, and its lowermost surface 4a is shown by a broken line.
• annealing is performed at a low temperature of 700 ° C. or less, for example, 600 ° C. for 1 hour.
• the Ge injection layer 4 becomes a single crystal.
• the channel layer 5 having a two-layer structure in which the reverse conductivity type impurity layer 2 is monocrystallized into a phosphorus-doped lower layer 5a and the amorphous silicon film 3 is monocrystallized into a non-doped upper layer 5b in the Ge injection layer 4 is formed. It is formed.
• amorphousization and low temperature annealing are performed by implanting Ge, which is an amorphous impurity, so that phosphorus does not diffuse into the non-doped upper layer 5b.
• a thin silicon oxide film is formed on the channel layer 5 by, eg, ECR-CVD.
• a high dielectric constant insulating material such as HfO or AlO is used.
• a phosphorus-doped polycrystalline silicon film is formed on the silicon oxide film by, eg, CVD. Then, the polycrystalline silicon film and the silicon oxide film are patterned into electrode shapes by photolithography and dry etching. As a result, as shown in FIG. 1E, a gate electrode 7 is formed on the channel layer 5 with the gate insulating film 6 interposed therebetween.
• a p-type impurity here boron
• (B) is ion-implanted into the channel layer 5.
• boron is ion-implanted under conditions of an acceleration energy of 7 keV and a dose of 2 ⁇ 10 15 Zcm 2 .
• a pair of impurity diffusion regions, ie, a source Z drain 8 is formed in the channel layer 5 on both sides of the gate electrode 7.
• the source Z drain 8 is separated from the lowermost surface 4 a of the Ge injection layer 4 by a predetermined distance in the channel layer 5.
• the Si transistor of this embodiment is completed through a process of forming an interlayer insulating film covering the gate electrode 7, a contact hole, an upper layer wiring, etc. (not shown).
• the main structure of the Si transistor formed through the above manufacturing process is as shown in FIG. 1F.
• the Si transistor has a channel layer 5 in which a phosphorus-doped lower layer 5a and a non-doped upper layer 5b are stacked.
• a Ge injection layer 4 containing germanium which is an amorphous impurity is formed from 5b to the lower layer 5a, and the source layer 4a is separated from the lowermost surface 4a of the Ge injection layer 4 in the channel layer 5.
• This structure has a Z drain 8.
• the depletion layer formed in the channel layer 5 when using the Si transistor is also a Ge injection layer. 4 is separated from the lowermost surface 4a. In this way, by holding the depletion layer formed in the channel layer 5 so as to be separated from the lowermost surface 4a where crystal defects remain, an electrical influence can be prevented.
• 5 can be constructed in a two-layer structure in which the phosphorus-doped lower layer 5a and the non-doped upper layer 5b are separated in impurity concentration. As a result, the vertical electric field of the channel layer 5 is relaxed and the mobility is increased. In this case, punch-through is prevented by the high phosphorus concentration lower layer 5a, and an increase in threshold voltage is suppressed by the non-doped upper layer 5b.
• This threshold voltage can be controlled by adjusting various conditions of phosphorus ion implantation when forming the lower layer 5a and adjusting the phosphorus concentration of the lower layer 5a. As a result, a highly reliable Si transistor that meets the demand for further miniaturization and miniaturization is realized.
• a so-called SOI (Silicon, Semiconauctoiv On Insulator) substrate is used instead of the Balta type silicon substrate in the first embodiment.
• 2A to 2F are schematic cross-sectional views illustrating a method of manufacturing an n-type Si transistor according to Modification 1 of the first embodiment in the order of steps.
• a single crystal SOI layer 14 of, eg, about 150 nm thickness is formed on a silicon substrate 12 via a silicon oxide film 13 of, eg, about 200 nm thickness, and the SOI layer 14 is formed according to the present invention. It corresponds to a semiconductor region.
• a source Z drain impurity (to be described later) is formed on the surface layer of a p-type SOI layer 14 containing about 1 ⁇ 10 15 / cm 3 of a p-type impurity, for example.
• a p-type impurity for example, an n-type, here phosphorus (P)) and a reverse conductivity type impurity (eg p-type, here boron (B)), for example, under conditions of a carousel energy of 30 keV and a dose of 1 X 10 13 Zcm 2 Ion implantation .
• annealing is performed at 900 ° C.
• the introduced boron is activated to form the reverse conductivity type impurity layer 15 having a uniform impurity distribution.
• the impurity (boron) concentration of the reverse conductivity type impurity layer 15 is, for example, about 3 ⁇ 10 18 Zcm 3 .
• the reverse conductivity type impurity layer 15 may be formed so that the impurity concentration gradually changes in the depth direction.
• the surface layer of the SOI layer 14 serving as the channel layer is not yet formed in a two-layer structure, there is no problem in performing a high-temperature annealing process. Thereafter, the surface of the SOI layer 14 is cleaned by ammonia ammonia water boil treatment, hydrofluoric acid treatment, hydrochloric acid hydrogen peroxide boil treatment and hydrofluoric acid treatment.
• a non-doped silicon film here an amorphous silicon film 3 is formed to a film thickness of, for example, about 50 nm on the SOI layer 14 by a low temperature film formation method, here a plasma CVD method.
• a low temperature film formation method here a plasma CVD method.
• boron as an impurity diffuses from the reverse conductivity type impurity layer 15 formed on the surface layer of the SOI layer 14 to the amorphous silicon film 3.
• a function of amorphizing the silicon constituting the semiconductor region into the region including the amorphous silicon film 3 and the reverse conductive impurity layer 15 on the surface of the SOI layer 14 is provided.
• a relatively heavy atom with germanium (Ge) is implanted here.
• an inert gas such as silicon (Si) or argon (Ar) may be used instead of germanium.
• the implantation is performed under the condition that germanium reaches from the amorphous silicon film 3 to the reverse conductivity type impurity layer 15 on the surface of the SOI layer 14, for example, the speed energy is 80 keV and the dose is 1 ⁇ 10 15 Zcm 2 .
• an amorphous state is obtained from the surface of the amorphous silicon film 3 including the reverse conductivity type impurity layer 15 of the SOI layer 14 to a depth of, for example, about lOOnm.
• this amorphized impurity layer (including the amorphous silicon film 3) is shown as a Ge injection layer 18, and its lowermost surface 18a is shown by a broken line.
• annealing is performed at a low temperature annealing of 700 ° C. or lower, for example, 600 ° C. for 1 hour.
• the Ge injection layer 18 becomes a single crystal.
• Layer 16 is formed.
• the lowermost surface 18a that is the interface between the layer 18 and the SOI layer 14 does not recover even after annealing, and does not crystallize.Therefore, crystal defects remain, and the upper layer 16b is not slightly crystallized. Some parts may remain.
• Modification 1 since amorphous formation and low temperature annealing are performed by implantation of Ge, which is an amorphous impurity, boron does not diffuse into the non-doped upper layer 16b.
• a thin silicon oxide film is formed on the channel layer 16 by, for example, the ECR-CVD method.
• a high dielectric constant insulating material such as HfO or AlO is used.
• a phosphorus-doped polycrystalline silicon film is formed on the silicon oxide film by, eg, CVD. Then, the polycrystalline silicon film and the silicon oxide film are patterned into electrode shapes by photolithography and dry etching. As a result, as shown in FIG. 2E, the gate electrode 7 is formed on the channel layer 16 via the gate insulating film 6.
• n-type impurities here phosphorus (P) are ion-implanted into the channel layer 16 using the gate electrode 7 as a mask.
• phosphorus is ion-implanted under conditions of a high speed energy of 10 keV and a dose of 2 ⁇ 10 15 Zcm 2 .
• a source Z drain 17 which is a pair of impurity diffusion regions is formed in the channel layer 16 on both sides of the gate electrode 7.
• the source Z drain 17 is separated from the lowermost surface 18 a of the Ge injection layer 18 by a predetermined distance in the channel layer 16.
• the Si transistor of Modification 1 is completed through a process of forming an interlayer insulating film covering the gate electrode 7, contact holes, upper layer wiring, etc. (not shown).
• FIG. 2F The main structure of the Si transistor formed through the above manufacturing process is as shown in FIG. 2F, which includes a channel layer 16 in which a phosphorus-doped lower layer 16a and a non-doped upper layer 16b are stacked, and an upper layer 16b.
• the source Z is separated from the lowermost surface 18a of the Ge injection layer 18 in the channel layer 16.
• the structure has a drain 17.
• the upper layer 16b of the channel layer 16 is separated from the lowermost surface 18a where the crystal defects remain, there is no electrical effect. Even when the crystal defects remain in the vicinity of the lowermost surface 18a, the lower layer 16a Since boron exists in the crystal, the crystal defects are neutralized. Further, the depletion layer formed in the channel layer 16 when using the Si transistor is also separated from the lowermost surface 18 a of the Ge injection layer 18. As described above, by holding the depletion layer formed in the channel layer 16 so as to be separated from the lowermost surface 18a where the crystal defects remain, an electrical influence can be prevented.
• the lower layer 16a has a site where the Ge concentration is 1 X 10 18 Zcm 3 , and the boron concentration of the site needs to be IX 10 18 Zcm 3 or more.
• the layer 16 can be formed in a two-layer structure in which the boron-doped lower layer 16a and the non-doped upper layer 16b are distinguished in impurity concentration. As a result, the vertical electric field of the channel layer 16 is relaxed and the mobility is increased. In this case, punch-through is prevented by the lower layer 16a having a high boron concentration, and an increase in threshold voltage is suppressed by the non-doped upper layer 16b.
• This threshold voltage can be controlled by adjusting the boron ion implantation conditions when forming the lower layer 16a and adjusting the boron concentration of the lower layer 16a. As a result, a highly reliable Si transistor that meets the demand for further miniaturization and miniaturization is realized.
• a so-called glass substrate is used instead of the Balta type silicon substrate in the first embodiment.
• 3A to 3F are schematic cross-sectional views illustrating a method of manufacturing an n-type Si transistor according to Modification 2 of the first embodiment in the order of steps.
• a silicon oxide film 22 having a thickness of, for example, about 200 nm and an amorphous silicon layer (not shown) having a thickness of, for example, about lOO nm are sequentially stacked on a glass substrate 21.
• This amorphous silicon layer corresponds to the semiconductor region of the present invention.
• an impurity of a source Z drain for example, n-type, here phosphorus (P)
• P phosphorus
• B reverse conductivity type
• Ions are implanted under the conditions of acceleration energy of 10 keV and dose of 1 X 10 13 Zcm 2 .
• the amorphous silicon layer is then annealed using a laser anneal, eg, a CW laser. At this time, the amorphous silicon layer is monocrystallized to form the silicon layer 23. Further, the reverse conductivity type impurity layer 24 having a uniform impurity distribution is formed on the silicon layer 23 by activating the introduced boron.
• the impurity (boron) concentration of the reverse conductivity type impurity layer 24 is about 3 ⁇ 10 18 Zcm 3, for example.
• the reverse conductivity type impurity layer 24 may be formed so that the impurity concentration gradually changes in the depth direction.
• crystallization and impurity activity are performed using a laser, it is possible to avoid a high-temperature process in which the heat application time is short.
• a non-doped silicon film here amorphous silicon
• a film formation method at a low temperature here a plasma CVD method.
• the film 3 is deposited to a thickness of about 50 nm, for example.
• boron as an impurity diffuses from the reverse conductivity type impurity layer 24 formed on the surface layer of the silicon layer 23 to the amorphous silicon film 3.
• the region including the reverse conductivity type impurity layer 24 on the surface of the amorphous silicon film 3 and the silicon layer 23 has a function of making the silicon constituting the semiconductor region amorphous.
• Inject heavy atoms here germanium (Ge).
• germanium here germanium (Ge).
• an inert gas such as silicon (Si) or anoregon (Ar) may be used instead of genoremanium.
• implantation is performed under the condition that germanium reaches from the amorphous silicon film 3 to the reverse conductivity type impurity layer 24 on the surface of the silicon layer 23, for example, a speed energy of 80 keV and a dose of 1 ⁇ 10 15 Zcm 2. To do.
• the silicon layer 23 is made amorphous from the surface of the silicon layer 23 to the reverse conductivity type impurity layer 24 to a depth of, for example, about lOOnm.
• this amorphized impurity layer (including the amorphous silicon film 3) is shown as a Ge injection layer 25, and its lowermost surface 25a is shown by a broken line.
• annealing is performed at a low temperature of 700 ° C or lower, for example, 600 ° C for 1 hour.
• the Ge injection layer 25 becomes a single crystal.
• a thin silicon oxide film is formed on the channel layer 26 by, eg, ECR-CVD.
• a high dielectric constant insulating material such as HfO or AlO is used.
• a molybdenum (Mo) film is formed on the silicon oxide film to a thickness of about 300 nm, for example. Then, the Mo film and the silicon oxide film are patterned into electrode shapes by photolithography and dry etching. As a result, as shown in FIG. 3E, the gate electrode 28 is formed on the channel layer 26 with the gate insulating film 6 interposed therebetween.
• Mo molybdenum
• n-type impurities here phosphorus (P) are ion-implanted into the channel layer 26 using the gate electrode 28 as a mask.
• phosphorus is ion-implanted under the conditions of a high speed energy of 10 keV and a dose of 2 ⁇ 10 15 Zcm 2 .
• a source Z drain 27 which is a pair of impurity diffusion regions is formed in the channel layer 26 on both sides of the gate electrode 28.
• the source Z drain 27 is separated from the lowermost surface 25 a of the Ge injection layer 25 by a predetermined distance in the channel layer 26.
• the Si transistor of Modification 2 is completed through a process of forming an interlayer insulating film covering the gate electrode 28, a contact hole, an upper layer wiring, etc. (not shown).
• the main structure of the Si transistor formed through the above manufacturing process is as shown in FIG. 3F.
• the Si transistor has a channel layer 5 in which a phosphorus-doped lower layer 5a and a non-doped upper layer 5b are stacked.
• a Ge injection layer 25 containing germanium which is an amorphous impurity is formed from 26b to the lower layer 26a, and the source is separated from the lowermost surface 25a of the Ge injection layer 25 in the channel layer 26.
• the structure has a Z drain 27.
• the depletion layer formed in the channel layer 26 when using the Si transistor is also separated from the lowermost surface 25a of the Ge injection layer 25. In this way, the depletion layer formed in the channel layer 26 is connected. By holding the crystal defect away from the lowermost surface 25a where the crystal defects remain, an electrical influence can be prevented.
• the lower layer 26a has a site where the Ge concentration is 1 X 10 18 Zcm 3 , and the boron concentration of the site is required to be IX 10 18 Zcm 3 or more.
• the glass substrate 21 can be used by efficiently using the low temperature treatment, and the high temperature is obtained in a state where ions are implanted in the region of the thickness to be the lower layer 26a. Avoid processing situations. Therefore, in the glass substrate 21, the channel layer 26 can be configured in a two-layer structure in which the boron-doped lower layer 26 a and the non-doped upper layer 26 b are separated in impurity concentration. As a result, the vertical electric field of the channel layer 26 is relaxed and the mobility is increased. In this case, punch-through is prevented by the high boron concentration lower layer 26a, and an increase in threshold voltage is suppressed by the non-doped upper layer 26b.
• This threshold voltage can be controlled by adjusting the boron ion implantation conditions when forming the lower layer 26a and adjusting the boron concentration of the lower layer 26a. As a result, a highly reliable Si transistor that meets the demand for further miniaturization and miniaturization is realized.
• 4A to 4F are schematic cross-sectional views showing a method of manufacturing an n-type Si transistor according to the second embodiment in order of steps.
• the same reference numerals and the like are given to the same constituent elements as those in the first embodiment for convenience of description.
• the p-type impurity is, for example, 1 X 10
• impurities of a source Z drain for example, n-type, in this case phosphorus (P)
• impurities of a reverse conductivity type for example, p-type,
• boron (B) is ion-implanted under the conditions of, for example, a speed energy of 50 keV and a dose of 1 ⁇ 10 13 / cm 2 .
• annealing is performed at 900 ° C. for 2 hours, and the introduced boron is activated to form a reverse conductivity type impurity layer 32 having a uniform impurity distribution.
• the impurity (boron) concentration in the reverse conductivity type impurity layer 32 is, for example, about 3 ⁇ 10 18 Zcm 3 .
• the reverse conductivity type impurity layer 32 may be formed so that the impurity concentration gradually changes in the depth direction.
• the surface layer of the silicon substrate 31 serving as the channel layer is still formed in a two-layer structure, so there is no problem in performing high-temperature annealing. Thereafter, the surface of the silicon substrate 31 is cleaned by performing an ammonia-hydrogen peroxide boil treatment, a hydrofluoric acid treatment, a hydrochloric acid-hydrogen peroxide boil treatment and a hydrofluoric acid treatment.
• germanium Ge
• an inert gas such as silicon (Si 2) or argon (Ar) may be used instead of germanium.
• the implantation is performed under the condition that germanium reaches the reverse conductivity type impurity layer 32 on the surface layer of the silicon substrate 31, for example, the acceleration energy is 80 keV and the dose is 1 ⁇ 10 15 Zcm 2 .
• the surface force of the silicon substrate 31 also includes the reverse conductivity type impurity layer 32 and is amorphousized to a depth of, for example, about lOOnm.
• this amorphized impurity layer is shown as a Ge injection layer 33, and its lowermost surface 33a is shown by a broken line.
• an impurity having the same conductivity type as that of a source Z drain (for example, n-type, here phosphorus (P)), which will be described later, is added to the Ge injection layer 33. It is introduced under the condition that it reaches the upper region of the reverse conductivity type impurity layer 32 in the injection layer 33.
• phosphorus is ion-implanted under the conditions of a high velocity energy of 5 keV and a dose of 1 ⁇ 10 13 Zcm 2 .
• a mixed impurity layer 34 in which boron and phosphorus are mixed is formed in the upper region of the Ge implanted layer 33, so that the Ge implanted layer 33 has its lower region formed by the formation of the mixed impurity layer 34.
• a two-layer structure is formed in which the reverse conductivity type impurity layer 32 remaining in the layer and the mixed impurity layer 34 are stacked.
• annealing is performed at a low temperature of 700 ° C. or less, for example, 600 ° C. for 1 hour.
• the Ge injection layer 33 becomes a single crystal.
• the boron-doped lower layer 35a in which the reverse conductivity type impurity layer 32 is single-crystallized in the Ge injection layer 33 and the mixed impurity layer 34 are single-crystallized and are electrically reversed.
• a channel layer 35 having a two-layer structure consisting of the upper layer 35b in a state where only the dopant is present or in a neutral state is formed, and the Ge injection layer 33 substantially remains in the lower layer 35a.
• a thin silicon oxide film is formed on the channel layer 35 by, eg, ECR-CVD.
• a high dielectric constant insulating material such as HfO or AlO is used.
• a molybdenum (Mo) film is formed on the silicon oxide film to a thickness of about 300 nm, for example. Then, the Mo film and the silicon oxide film are patterned into electrode shapes by photolithography and dry etching. As a result, as shown in FIG. 4E, the gate electrode 36 formed through the gate insulating film 6 is patterned on the channel layer 35.
• Mo molybdenum
• n-type impurities here phosphorus (P) are ion-implanted into the channel layer 35 using the gate electrode 36 as a mask.
• phosphorus is ion-implanted under the conditions of a high speed energy of 10 keV and a dose of 2 ⁇ 10 15 Zcm 2 .
• a source Z drain 37 which is a pair of impurity diffusion regions is formed in the channel layer 35 on both sides of the gate electrode 36.
• the source Z drain 37 is separated from the lowermost surface 33a of the Ge injection layer 33 within the channel layer 35 by a predetermined distance.
• the Si transistor of this embodiment is completed through a process of forming an interlayer insulating film covering the gate electrode 36, a contact hole, an upper layer wiring, etc. (not shown).
• the main structure of the Si transistor formed through the above manufacturing process includes a channel layer 35 in which a phosphorus-doped lower layer 35a and a non-doped upper layer 35b are stacked, and the upper layer 35b A Ge injection layer 33 containing germanium which is an amorphous impurity is formed in the lower layer 35a, and the source Z drain so as to be separated from the lowermost surface 33a of the Ge injection layer 33 in the channel layer 35. It is a structure having 37.
• the upper layer 35b of the channel layer 35 is separated from the lowermost surface 33a where the crystal defects remain, there is no electrical effect, and even if the crystal defects remain in the vicinity of the lowermost surface 33a, the lower layer 35a Since boron exists in the crystal, the crystal defects are neutralized.
• the depletion layer formed in the channel layer 35 when the Si transistor is used is also separated from the lowermost surface 33a of the Ge injection layer 33. As described above, by holding the depletion layer formed in the channel layer 35 so as to be separated from the lowermost surface 33a where the crystal defects remain, an electrical influence can be prevented. [0081]
• the lower layer 35a has a site where the Ge concentration is 1 X 10 18 Zcm 3 , and the boron concentration of the site needs to be IX 10 18 Zcm 3 or more.
• FIG. 5 shows a boron concentration profile in the lower layer 35 a of the channel layer 35.
• the horizontal axis represents depth
• the vertical axis represents boron concentration.
• the average concentration of boron in the lower layer 35a is about 2 ⁇ 10 18 Zcm 3 , and it can be seen that a concentration profile having a steep and shallow Gaussian distribution is formed in the lower layer 35a as shown in the figure.
• the low-temperature treatment can be efficiently used to avoid the situation in which the high-temperature treatment is performed in a state where ions are implanted in the region of the thickness serving as the lower layer 35a.
• the layer 35 can be formed into a two-layer structure in which the boron-doped lower layer 35a and the electrically non-doped upper layer 35b are separated in impurity concentration. Thereby, the vertical electric field of the channel layer 35 is relaxed and the mobility is increased. In this case, punch-through is prevented by the lower layer 35a having a high boron concentration, and an increase in threshold voltage is suppressed by the upper layer 35b that is electrically non-doped.
• This threshold voltage is finely adjusted by adjusting the conditions of ion implantation of fluorine and phosphorus when forming the lower layer 35a and the upper layer 35b, and adjusting the boron concentration and phosphorus concentration of the lower layer 35a and upper layer 35b, respectively. Force control is possible. As a result, a highly reliable Si transistor that meets the demand for further miniaturization and miniaturization can be realized.
• SOI Silicon, Semiconauctoiv On Insulator
• 6A to 6F are schematic cross-sectional views showing a method of manufacturing an n-type Si transistor according to Modification 1 of the second embodiment in the order of steps.
• the SOI substrate 41 is formed by forming a single-crystal SOI layer 44 of, eg, about 150 nm thickness on a silicon substrate 42 via a silicon oxide film 43 of, eg, about 200 nm thickness. Corresponds to the semiconductor region of the present invention.
• p-type impurities for example, a source Z drain impurity (described later)
• n-type, here phosphorous (P)) and reverse conductivity type impurities for example, under conditions of a carousel energy of 50 keV and a dose of 1 X 10 13 Zcm 2 Ion implantation.
• annealing is performed at 900 ° C.
• the introduced boron is activated to form a reverse conductivity type impurity layer 45 having a uniform impurity distribution.
• the impurity (boron) concentration of the reverse conductivity type impurity layer 45 is, for example, about 3 ⁇ 10 18 Zcm 3 .
• the reverse conductivity type impurity layer 45 may be formed so that the impurity concentration gradually changes in the depth direction.
• the surface layer of the SOI layer 44 serving as the channel layer is not yet formed in a two-layer structure, there is no problem in performing high-temperature annealing. Thereafter, the surface of the SOI layer 44 is cleaned by ammonia ammonia water boil treatment, hydrofluoric acid treatment, hydrochloric acid hydrogen peroxide boil treatment and hydrofluoric acid treatment.
• the surface layer of the SOI layer 44 including the reverse conductivity type impurity layer 45 has a relatively heavy atom having a function of amorphizing silicon constituting the semiconductor region.
• germanium Ge
• an inert gas such as silicon (Si) or argon (Ar) may be used instead of germanium.
• the implantation is performed under the condition that germanium reaches the reverse conductivity type impurity layer 45 on the surface of the SOI layer 44, for example, acceleration energy of 80 keV and dose of 1 ⁇ 10 15 Zcm 2 .
• the surface force of the SOI layer 44 also includes the reverse conductivity type impurity layer 45 and is made amorphous to a depth of, for example, about lOOnm.
• this amorphized impurity layer is shown as a Ge injection layer 46, and its lowermost surface 46a is shown by a broken line.
• an impurity having the same conductivity type as that of a source Z drain (for example, n-type, here, phosphorus (P)), which will be described later, is added to the Ge injection layer 46. It is introduced under the condition of reaching the upper region of the reverse conductivity type impurity layer 45 in the injection layer 46.
• phosphorus is ion-implanted under the conditions of a high velocity energy of 5 keV and a dose of 1 ⁇ 10 13 Zcm 2 .
• a mixed impurity layer 47 in which boron and phosphorus are mixed is formed in the upper region of the Ge implanted layer 46.
• the mixed impurity layer 47 is formed in the Ge implanted layer 46.
• a two-layer structure in which the reverse conductivity type impurity layer 45 remaining in the lower region and the mixed impurity layer 47 are stacked is formed.
• annealing is performed at a low temperature of 700 ° C. or lower, for example, 600 ° C. for 1 hour.
• the Ge injection layer 46 becomes a single crystal.
• the boron-doped lower layer 48a in which the reverse conductivity type impurity layer 45 is single-crystallized in the Ge injection layer 46 and the mixed impurity layer 47 are single-crystallized and are substantially electrically reversed.
• a channel layer 48 having a two-layer structure including the upper layer 48b in a state where only the dopant is present or in a neutral state is formed, and the Ge injection layer 46 substantially remains only below the lower layer 48a.
• the remaining Ge implanted layer 46 has an interface with the SOI layer 44 that is the lowermost surface 46a. Crystal defects that are not recovered even after annealing and are not single-crystallized remain, and are slightly single in the upper layer 48b. There may be a portion that remains uncrystallized. In the present embodiment, since amorphousization and low-temperature annealing are performed by implantation of Ge, which is an amorphous impurity, phosphorus does not diffuse into the upper layer 48b.
• a thin silicon oxide film is formed on the channel layer 48 by, eg, ECR-CVD. HfO or Al O instead of silicon oxide film
• a molybdenum (Mo) film is formed on the silicon oxide film to a thickness of about 300 nm, for example. Then, the Mo film and the silicon oxide film are patterned into electrode shapes by photolithography and dry etching. As a result, as shown in FIG. 6E, the gate electrode 36 formed through the gate insulating film 6 is patterned on the channel layer 48.
• Mo molybdenum
• n-type impurities here phosphorus (P) are ion-implanted into the channel layer 48 using the gate electrode 36 as a mask.
• phosphorus is ion-implanted under the conditions of a high speed energy of 10 keV and a dose of 2 ⁇ 10 15 Zcm 2 .
• a source Z drain 49 which is a pair of impurity diffusion regions is formed in the channel layer 46 on both sides of the gate electrode 36.
• the source Z drain 49 is separated from the lowermost surface 46 a of the Ge injection layer 46 by a predetermined distance in the channel layer 48.
• the Si transistor of Modification 1 is completed through a process of forming an interlayer insulating film, contact holes, upper layer wiring, etc. (not shown) covering the gate electrode 36.
• FIG. 6F The main structure of the Si transistor formed through the above manufacturing process is as shown in FIG. 6F.
• a channel layer 48 formed by laminating a phosphorus-doped lower layer 48a and a non-doped upper layer 48b, and a Ge injection layer 46 containing germanium which is an amorphous impurity from the upper layer 48b to the lower layer 48a.
• the source Z drain 49 is formed so as to be separated from the lowermost surface 46a of the Ge injection layer 46 in the channel layer 48.
• the depletion layer formed in the channel layer 48 when the Si transistor is used is also separated from the lowermost surface 46 a of the Ge injection layer 46. As described above, by holding the depletion layer formed in the channel layer 48 so as to be separated from the lowermost surface 46a where the crystal defects remain, an electrical influence can be prevented.
• the lower layer 48a has a site where the Ge concentration is 1 X 10 18 Zcm 3 , and the boron concentration of the site needs to be IX 10 18 Zcm 3 or more.
• the low-temperature treatment can be efficiently used to avoid the situation where the high-temperature treatment is performed in a state where ions are implanted into the region of the lower layer 48a.
• the layer 48 can be formed in a two-layer structure in which a boron-doped lower layer 48a and an electrically non-doped upper layer 48b are separated from each other in terms of impurity concentration.
• the vertical electric field of the channel layer 48 is relaxed and the mobility is increased.
• punch-through is prevented by the lower layer 48a having a high boron concentration, and an increase in threshold voltage is suppressed by the upper layer 48b in an electrically non-doped state.
• This threshold voltage is controlled by adjusting the boron and phosphorus ion implantation conditions when forming the lower layer 48a and the upper layer 48b, and adjusting the boron concentration and phosphorus concentration of the lower layer 48a and upper layer 48b, respectively. Can be controlled. As a result, a highly reliable Si transistor that meets the demand for further miniaturization and miniaturization is realized.
• a so-called glass substrate is used instead of the Balta-type silicon substrate in the second embodiment.
• FIG. 7A to 7F are schematic cross-sectional views showing a method of manufacturing an n-type Si transistor according to Modification 2 of the second embodiment in the order of steps.
• a silicon oxide film 52 having a thickness of, for example, about 200 nm and an amorphous silicon layer (not shown) having a thickness of, for example, about lOO nm are sequentially stacked on a glass substrate 51.
• This amorphous silicon layer corresponds to the semiconductor region of the present invention.
• an impurity of a source Z drain (for example, n-type, here phosphorus (P)), which will be described later, is doped on the surface layer of the amorphous silicon layer, for example, an impurity of a reverse conductivity type (for example, p-type, here boron (B)). Ions are implanted under the conditions of acceleration energy of 10 keV and dose of 1 X 10 13 Zcm 2 . The amorphous silicon layer is then annealed using a laser anneal, eg, a CW laser. At this time, the amorphous silicon layer is monocrystallized to form the silicon layer 53. Furthermore, the reverse conductivity type impurity layer 54 having a uniform impurity distribution is formed on the silicon layer 53 by activating the introduced boron.
• a source Z drain for example, n-type, here phosphorus (P)
• B boron
• the impurity (boron) concentration of the reverse conductivity type impurity layer 54 is, for example, about 3 ⁇ 10 18 Zcm 3 .
• the reverse conductivity type impurity layer 54 may be formed so that the impurity concentration gradually changes in the depth direction.
• crystallization and impurity activity are performed using a laser, it is possible to avoid a high-temperature process in which the heat application time is short.
• a relatively heavy atom having a function of amorphizing silicon constituting the semiconductor region here, germanium ( Inject Ge).
• germanium Inject Ge
• an inert gas such as silicon (Si) or argon (Ar) may be used instead of germanium.
• the implantation is performed under the condition that germanium reaches the surface of the reverse conductivity type impurity layer 54 on the surface of the silicon layer 53, for example, the acceleration energy is 80 keV and the dose is 1 ⁇ 10 15 Zcm 2 .
• an amorphous layer is formed from the surface of the silicon layer 53 to the depth of about 10 nm including the reverse conductivity type impurity layer 54.
• this amorphized impurity layer is shown as a Ge injection layer 55, and its lowermost surface 55a is shown by a broken line.
• an impurity having the same conductivity type as that of a source Z drain (for example, n-type, here, phosphorus (P)), which will be described later, is added to the Ge implanted layer 55. It is introduced under the condition of reaching the upper region of the reverse conductivity type impurity layer 54 in the injection layer 55.
• phosphorus is ion-implanted under the conditions of a high velocity energy of 5 keV and a dose of 1 ⁇ 10 13 Zcm 2 . This prevents mixing of boron and phosphorus in the upper region of the Ge injection layer 55.
• a pure layer 56 is formed, and the Ge-implanted layer 55 is formed by stacking the mixed impurity layer 56 with the reverse conductivity type impurity layer 54 remaining in the lower region and the mixed impurity layer 56.
• a two-layer structure will be formed.
• annealing is performed at a low temperature of 700 ° C. or lower, for example, 600 ° C. for 1 hour.
• the Ge injection layer 55 becomes a single crystal.
• the boron-doped lower layer 57a in which the reverse conductivity type impurity layer 54 is single-crystallized in the Ge injection layer 55 and the mixed impurity layer 56 are single-crystallized and are substantially non-doped electrically.
• a channel layer 57 having a two-layer structure composed of the upper layer 57b in a state is formed.
• a thin silicon oxide film is formed on the channel layer 57 by, eg, ECR-CVD. HfO or Al O instead of silicon oxide film
• a molybdenum (Mo) film is formed on the silicon oxide film to a thickness of about 300 nm, for example. Then, the Mo film and the silicon oxide film are patterned into electrode shapes by photolithography and dry etching. As a result, as shown in FIG. 7E, the gate electrode 36 formed through the gate insulating film 6 is patterned on the channel layer 57.
• Mo molybdenum
• n-type impurities here phosphorus (P) are ion-implanted into the channel layer 57 using the gate electrode 36 as a mask.
• phosphorus is ion-implanted under the conditions of a high speed energy of 10 keV and a dose of 2 ⁇ 10 15 Zcm 2 .
• a source Z drain 58 which is a pair of impurity diffusion regions is formed in the channel layer 57 on both sides of the gate electrode 36.
• the source Z drain 58 is separated from the lowermost surface 55 a of the Ge injection layer 55 within the channel layer 57 by a predetermined distance.
• the Si transistor of Modification 2 is completed through a process of forming an interlayer insulating film covering the gate electrode 36, contact holes, upper layer wiring, etc. (not shown).
• the main structure of the Si transistor formed through the above manufacturing process is as shown in Fig. 7F.
• a channel layer 57 formed by laminating a phosphorus-doped lower layer 57a and a non-doped upper layer 57b, and a Ge injection layer 55 containing germanium which is an amorphous impurity from the upper layer 57b to the lower layer 57a.
• the source Z drain 58 is formed so as to be separated from the lowermost surface 55 a of the Ge injection layer 55 in the channel layer 57.
• the depletion layer formed in the channel layer 57 when the Si transistor is used is also separated from the lowermost surface 55a of the Ge injection layer 55. As described above, by holding the depletion layer formed in the channel layer 57 so as to be separated from the lowermost surface 55a where the crystal defects remain, an electrical influence can be prevented.
• the lower layer 57a has a site where the Ge concentration is 1 X 10 18 Zcm 3 , and the boron concentration of the site needs to be IX 10 18 Zcm 3 or more.
• the glass substrate 51 can be used by efficiently using the low-temperature treatment, and ion-implanted into a region having a thickness to be the lower layer 57a. Since the situation of high-temperature treatment can be avoided, the channel layer 57 can be configured in a two-layer structure in which the boron-doped lower layer 57a and the electrically non-doped upper layer 57b are separated in impurity concentration. Thereby, the vertical electric field of the channel layer 57 is relaxed and the mobility is increased.

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