WO2006026054A1 - Apparatus and method for enabling digital and analog data communication over a data bus - Google Patents

Apparatus and method for enabling digital and analog data communication over a data bus Download PDF

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Publication number
WO2006026054A1
WO2006026054A1 PCT/US2005/027724 US2005027724W WO2006026054A1 WO 2006026054 A1 WO2006026054 A1 WO 2006026054A1 US 2005027724 W US2005027724 W US 2005027724W WO 2006026054 A1 WO2006026054 A1 WO 2006026054A1
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WO
WIPO (PCT)
Prior art keywords
analog
digital
connector
electronic apparatus
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2005/027724
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English (en)
French (fr)
Inventor
Sin Hui Cheah
Ronald Alexander Fleming
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thomson Licensing SAS
Original Assignee
Thomson Licensing SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing SAS filed Critical Thomson Licensing SAS
Priority to EP05778434A priority Critical patent/EP1782224B1/en
Priority to KR1020077004362A priority patent/KR101141268B1/ko
Priority to US11/659,773 priority patent/US8918546B2/en
Priority to JP2007529889A priority patent/JP5547372B2/ja
Publication of WO2006026054A1 publication Critical patent/WO2006026054A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits

Definitions

  • the present invention generally relates to data communications, and more particularly, to an apparatus and method for enabling, among other things, both digital and analog data to be communicated over a data bus such as a universal serial bus (USB) with a single low-cost connector such as a USB
  • USB Data communication over a bus
  • One well-known type of bus is the USB, which is generally used to transmit digital data between apparatuses/devices. Accordingly, many apparatuses/devices such as audio/MP3 players, computers, peripheral equipment and other devices often include a connector/jack for connecting to a USB.
  • an audio apparatus/device such as an MP3 player
  • One approach to accommodate both digital and analog data in this manner is to provide separate electrical connectors for the two different types of data.
  • the digital data may be received via a USB connector and the analog data may be output via another connector.
  • Another approach is to use a connector that is physically larger than a typical USB connector.
  • an electronic apparatus comprising interface means for coupling the electronic apparatus to one of a digital device and an analog device.
  • Control means determines whether the interface means is coupled to the digital device or the analog device.
  • Switching means couples the interface means to one of a digital element and an analog element responsive to the determination.
  • a method for controlling an electronic apparatus comprises detecting if a connector of the electronic apparatus is in a connected state, determining whether the connector is coupled to a digital device or an analog device if the connector is in the connected state, and coupling the connector to one of a digital element and an analog element of the electronic apparatus responsive to the determination.
  • an audio apparatus comprising a connector operative to couple the audio apparatus to one of a digital device and an analog device.
  • a controller is operative to determine whether the connector is coupled to the digital device or the analog device.
  • a switch is operative to couple the connector to one of a digital element and an analog element responsive to the determination.
  • FIG. 1 is a block diagram of an electronic apparatus according to an exemplary embodiment of the present invention
  • FIG. 2 is a diagram of the electronic apparatus of FIG. 1 in a digital mode according to an exemplary embodiment of the present invention
  • FIG. 3 is a diagram of the electronic apparatus of FIG. 1 in an analog mode according to an exemplary embodiment of the present invention.
  • FIG. 4 is a flowchart illustrating steps for controlling an electronic apparatus according to an exemplary embodiment of the present invention.
  • the exemplifications set out herein illustrate preferred embodiments of the invention, and such exemplifications are not to be construed as limiting the scope of the invention in any manner.
  • FIG. 1 a block diagram of an electronic apparatus 100 according to an exemplary embodiment of the present invention is shown.
  • electronic apparatus 100 is embodied as an audio apparatus such as RCA model RD2765 MP3 player, but may be embodied as another type of electronic device or apparatus.
  • Electronic apparatus 100 comprises control means such as system controller 10, memory means such as memory 20, processing means such as USB processor 30, data conversion means such as analog-to-digital converter (ADC) and/or digital-to-analog converter (DAC) 40, switching means such as field effect transistor (FET) switch 50, and interface means such as USB connector 60.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • FET field effect transistor
  • IC 1 may be embodied using integrated circuits (ICs), and some elements may be included on one or more ICs.
  • system controller 10, USB processor 30, and ADC/DAC 40 may be implemented in a single IC.
  • certain conventional elements associated with electronic apparatus 100 such as certain control signals, power signals and/or other elements may not be shown in FIG. 1.
  • System controller 10 is operative to perform various control and processing functions. According to an exemplary embodiment, system controller 10 is operative to read digital audio data from memory 20 via a data/address bus (e.g., responsive to a user input) and decode this digital audio data (e.g., MP3 decoding, etc.) to thereby generate decoded digital audio data. This decoded digital audio data is then serially provided to DAC 40 via an inter-integrated sound ("I2S") bus. System controller 10 may also receive digital audio data from ADC 40, process the received digital audio data, and cause the processed digital audio data to be stored in memory 20. System controller 10 is also operative to control a reset state of USB processor 30.
  • I2S inter-integrated sound
  • system controller 10 provides a reset signal to USB processor 30 having a logic state indicating the reset state.
  • the reset signal may exhibit a logic state of "0" (or vice-versa) when USB processor 30 is in the reset state, and may exhibit a logic state of "1" (or vice-versa) when USB processor 30 is released from the reset state.
  • System controller 10 is also operative to control an operating mode of electronic apparatus 100.
  • electronic apparatus 100 includes a digital mode and an analog mode.
  • digital mode electronic apparatus 100 is operative to receive, process and store digital data including digital audio data provided from an external digital device such as a personal computer (PC).
  • PC personal computer
  • Electronic apparatus 100 may also output such digital data to an external digital device during the digital mode.
  • FIG. 2 is a diagram showing electronic apparatus 100 connected to a PC 200 via a data bus such as a USB in the digital mode according to an exemplary embodiment of the present invention.
  • analog mode electronic apparatus 100 is operative to receive analog data such as analog audio data from an external analog device, convert the received analog data to a digital format, and store the resulting digital data.
  • FIG. 3 is a diagram showing electronic apparatus 100 connected to a docking station 300 in the analog mode according to an exemplary embodiment of the present invention.
  • docking station 300 may provide left and right analog audio signals to one or more output elements (e.g., speakers) via a data bus such as a USB.
  • system controller 10 provides a mode control signal to FET switch 50 to switch electronic apparatus 100 from the digital mode to the analog mode, and vice-versa.
  • System controller 10 is also operative to perform and/or enable other functions of electronic apparatus 100 as described herein. For example, system controller 10 loads enumeration code into USB processor 30 to facilitate identification of an external device connected to electronic apparatus 100 via USB connector 60. Although not expressly shown in FIG. 1 , system controller 10 is also operatively coupled to at least one predetermined pin (e.g., pin 1 ) of USB connector 60, and is able to detect connected and disconnected states of USB connector 60 based on a voltage present on this predetermined pin. According to an exemplary embodiment, system controller 10 determines that USB connector 60 is in the connected state if a threshold voltage (e.g., 5 volts) is present on the predetermined pin. Conversely, system controller 10 determines that USB connector 60 is in the disconnected state if the threshold voltage is not present on the predetermined pin.
  • a threshold voltage e.g., 5 volts
  • Memory 20 is operative to store digital data including digital audio data.
  • memory 20 may be embodied as a non-volatile memory such as a static dynamic random access memory (SDRAM), flash memory, hard disc drive (HDD), or other type of memory.
  • SDRAM static dynamic random access memory
  • HDD hard disc drive
  • USB processor 30 is operative to perform various USB-related processing functions. According to an exemplary embodiment, USB processor 30 performs data processing to enable data communication in accordance with the USB protocol. As is known in the art, the USB protocol includes simultaneously transmitting an original version of digital data (i.e., a D+ stream) and a complementary version of the same digital data (i.e., a D- stream). USB processor 30 is operative to convert such digital data received via FET switch 50 from a serial format to a parallel format prior to its storage in memory 20. Conversely, USB processor 30 is also operative to convert digital data read from memory 20 from a parallel format to a serial format prior to its output over a USB via USB connector 60. As will be described later herein, USB processor 30 is further operative to execute enumeration code to thereby identify a particular host device to which electronic apparatus 100 is connected.
  • the USB protocol includes simultaneously transmitting an original version of digital data (i.e., a D+ stream) and a complementary version of the same digital data (i.e.,
  • ADC/DAC 40 is operative to handle analog data.
  • ADC/DAC 40 is operative to convert data from an analog format to a digital format and/or vice-versa. That is, electronic apparatus 100 may include an ADC (and not a DAC) 1 a DAC (and not an ADC), or both elements.
  • ADC 40 receives left (L) and right (R) analog audio data from FET switch 50, and converts the received analog audio data to digital audio data. This digital audio data may then be processed via system controller 10 and stored in memory 20.
  • DAC 40 receives decoded digital audio data in a serial manner from system controller 10 via the I2S bus, and converts the decoded digital audio data to analog audio data. As indicated in FIG. 1 , this analog audio data may be provided as separate left (L) and right (R) analog audio signals.
  • FET switch 50 is operative to perform a switching function based on the mode control signal provided from system controller 10.
  • FET switch 50 provides one or more input/output paths between USB processor 30 and USB connector 60 for digital data (e.g., digital audio data) during the digital mode.
  • FET switch 50 provides one or more input/output paths between ADC/DAC 40 and USB connector 60 for analog data (e.g., L and R audio data) during the analog mode.
  • the analog data signal output from DAC 40 during the analog mode is floating on a direct current (DC) voltage that is approximately one half the applicable supply voltage. In this manner, signal excursion towards the negative potential is avoided.
  • DC direct current
  • USB connector 60 is operative to connect electronic apparatus 100 to various external devices including digital devices such as PC 200 shown in FIG. 2, and analog devices such as docking station 300 shown in FIG. 3. As indicated in FIG. 1 , the analog signal path between FET switch 50 and USB connector 60 includes one or more capacitors which filter the DC component of the analog data output from FET switch 50.
  • USB connector 60 may be embodied as a mini-B type USB connector, a standard Type-B USB connector, or other type of connector. Table 1 below shows pin definitions for the mini-B type and standard Type-B USB connectors during the digital and analog modes of the present invention.
  • FIG. 4 a flowchart 400 illustrating steps for controlling an electronic apparatus according to an exemplary embodiment of the present invention is shown.
  • steps of FIG. 4 will be described with reference to electronic apparatus 100 shown in FIGS. 1 to 3.
  • the steps of FIG. 4 are exemplary only, and are not intended to limit the present invention in any manner.
  • step 405 the process starts.
  • electronic apparatus 100 is in the digital mode when the process starts at step 405.
  • step 410 a determination is made as to whether USB connector 60 is in the connected state.
  • system controller 10 makes the determination at step 410 by detecting whether a threshold voltage (e.g., 5 volts) is present on a predetermined pin (e.g., pin 1 ) of USB connector 60, which thereby indicates that USB connector 60 is in the connected state. As indicated in FIG. 4, step 410 is repeated until system controller 10 determines that USB connector 60 is in the connected state.
  • a threshold voltage e.g., 5 volts
  • step 415 USB processor 30 is released from the reset state and enumeration code is loaded.
  • system controller 10 changes the logic state of the reset signal (e.g., from “0" to "1” or vice-versa) provided to USB processor 30 to thereby release USB processor 30 from the reset state at step 415.
  • System controller 10 also loads the enumeration code into USB processor 30 via the I2C bus at step 415. When executed, the enumeration code can enable USB processor 30 to identify the particular host device to which electronic apparatus 100 is connected.
  • USB processor 30 executes the enumeration code at step 420 which initiates a "hand-shake" process with the host device connected to electronic apparatus 100.
  • USB processor 30 provides any data received from the host device during this "hand-shake" process to system controller 10 via the I2C bus (or other digital data lines configured for such purpose), which thereby enables system controller 10 to determine whether the host device is a digital device at step 420.
  • step 420 determines whether the digital audio data is available. If the determination at step 420 is positive, process flow advances to step 425 where electronic apparatus 100 remains in the digital mode. While in the digital mode, electronic apparatus 100 may receive digital data such as digital audio data from the digital host device, as represented for example in
  • FIG. 2 and store the same in memory 20.
  • step 430 a determination is made as to whether USB connector 60 is in the disconnected state.
  • system controller 10 can determine whether USB connector 60 is in the connected or disconnected state by checking the voltage on a predetermined pin of USB connector 60. Accordingly, system controller 10 makes the determination at step 430 by checking the voltage on the predetermined pin of USB connector 60. As indicated in FIG. 4, steps 425 and 430 are repeated until system controller 10 determines that USB connector 60 is in the disconnected state.
  • step 435 USB processor 30 is reset.
  • system controller 10 changes the logic state of the reset signal (e.g., from “1" to "0” or vice-versa) provided to USB processor 30 to thereby reset USB processor 30 at step 435. From step 435, process flow loops back to step 410 as indicated in FIG. 4.
  • step 440 electronic apparatus 100 switches to the analog mode.
  • system controller 10 provides the mode control signal to FET switch 50 to thereby switch electronic apparatus 100 from the digital mode to the analog mode at step 440.
  • electronic apparatus 100 may output analog data such as analog audio data to an output device via a docking station, as represented for example in FIG. 3.
  • step 445 a determination is made as to whether USB connector 60 is in the disconnected state.
  • system controller 10 can determine whether USB connector 60 is in the connected or disconnected state by checking the voltage on a predetermined pin of USB connector 60. Accordingly, system controller 10 makes the determination at step 445 by checking the voltage on the predetermined pin of USB connector 60. As indicated in FIG. 4, steps 440 and 445 are repeated until system controller 10 determines that USB connector 60 is in the disconnected state.
  • step 450 electronic apparatus 100 switches back to the digital mode.
  • system controller 10 provides the mode control signal to FET switch 50 to thereby switch electronic apparatus 100 from the analog mode to the digital mode at step 450. From step 450, process flow loops back to step 410 as indicated in FIG. 4.
  • the present invention provides an apparatus and method for enabling, among other things, both digital and analog data to be communicated over a data bus such as a USB with a single low-cost connector such as a USB connector. While this invention has been described as having a preferred design, the present invention can be further modified within the spirit and scope of this disclosure. This application is therefore intended to cover any variations, uses, or adaptations of the invention using its general principles. Further, this application is intended to cover such departures from the present disclosure as come within known or customary practice in the art to which this invention pertains and which fall within the limits of the appended claims.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Information Transfer Systems (AREA)
  • Dc Digital Transmission (AREA)
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PCT/US2005/027724 2004-08-27 2005-08-04 Apparatus and method for enabling digital and analog data communication over a data bus Ceased WO2006026054A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP05778434A EP1782224B1 (en) 2004-08-27 2005-08-04 Apparatus and method for enabling digital and analog data communication over a data bus
KR1020077004362A KR101141268B1 (ko) 2004-08-27 2005-08-04 하나의 데이터 버스를 통해 디지털 및 아날로그 데이터통신을 가능케 하기 위한 장치 및 방법
US11/659,773 US8918546B2 (en) 2004-08-27 2005-08-04 Apparatus and method for enabling digital and analog data communication over a data bus
JP2007529889A JP5547372B2 (ja) 2004-08-27 2005-08-04 データ・バスを介してディジタルおよびアナログのデータ通信を可能にするための装置および方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US60529604P 2004-08-27 2004-08-27
US60/605,296 2004-08-27

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US (1) US8918546B2 (enExample)
EP (1) EP1782224B1 (enExample)
JP (1) JP5547372B2 (enExample)
KR (1) KR101141268B1 (enExample)
CN (1) CN101006435A (enExample)
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EP1782224A1 (en) 2007-05-09
MY142152A (en) 2010-09-30
US20080228969A1 (en) 2008-09-18
US8918546B2 (en) 2014-12-23
JP5547372B2 (ja) 2014-07-09
KR101141268B1 (ko) 2012-07-19
CN101006435A (zh) 2007-07-25
KR20070046140A (ko) 2007-05-02
EP1782224B1 (en) 2011-10-12

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