Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/113—Isolations within a component, i.e. internal isolations
  • H10D62/115—Dielectric isolations, e.g. air gaps
  • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D8/00—Diodes
  • H10D8/60—Schottky-barrier diodes 

Definitions

• This invention relates to semiconductors, and more particularly, to semiconductor devices that can operate like Schottky diodes.
• Schottky diodes have long been found to be useful in a significant number of applications.
• the Schottky diodes have a lower threshold in the forward biased direction than a PN junction diode which provides for a variety of useful functions.
• One major disadvantage of typical Schottky diodes is that the leakage current in the reverse biased direction increases exponentially as the reverse bias voltage increases. This effect is sometimes called “barrier lowering.”
• Another characteristic that is generally desirable to improve is the breakdown voltage.
• a characteristic I-V curve for a Schottky diode is shown in FIG. 1. This a semi-log scale in which the voltage (V) is linear and the current (I) is a log scale.
• FIG. 1 is an I-V curve of a conventional Schottky diode
• FIG. 2 is a circuit diagram of a Schottky device according to an embodiment of the invention
• FIG. 3 is a cross section of the Schottky device of FIG. 2 according to a first implementation
• FIG. 4 is a I-V curve of the Schottky device of FIG. 2
• FIG. 5 is a cross section of the Schottky device of FIG. 2 according to a second implementation
• FIG. 6 is a cross section of the Schottky device of FIG. 2 according to a third implementation
• FIG. 1 is an I-V curve of a conventional Schottky diode
• FIG. 2 is a circuit diagram of a Schottky device according to an embodiment of the invention
• FIG. 3 is a cross section of the Schottky device of FIG. 2 according to a first implementation
• FIG. 4 is a I-V curve of the Schottky device of FIG. 2
• FIG. 5 is a
• FIG. 7 is a circuit diagram a Schottky device according to an alternative embodiment to that of FIG. 2.
• Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
• a regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current.
• the reverse bias case there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diode begins to absorb more of the voltage.
• FIG. 1 Shown in FIG. 1 is a Schottky device 10 comprising a Schottky diode 16, a positive terminal 12, a negative terminal 14, and an N channel transistor 18.
• the convention used herein is that when Schottky device 10 is forward biased, current flows from positive terminal 12 to negative terminal 14 and when reverse biased, leakage current flows from negative terminal 14 to positive terminal 12.
• Schottky diode 16 has a positive terminal coupled to positive terminal 12 and a negative terminal.
• Transistor 18 has a first current electrode connected to the negative terminal of Schottky diode 16 at a contact 20, a gate connected to positive terminal 12, a second current electrode connected to negative terminal 14, a body connected to positive terminal 12, and a channel region 22.
• the first current electrode of transistor 20 functions as a drain when Schottky device 10 is forward biased and functions as a source when Schottky device 10 is reverse biased.
• Channel region 22 is doped to make transistor 18 an N channel depletion mode transistor that has a negative threshold voltage of, for example, -0.2 volts. This threshold voltage may be different from that but is preferably negative and thus a depletion mode device.
• transistor 18 In forward bias operation, transistor 18 is conductive, because it is a depletion mode device, and the voltage at terminal 12 is more positive than the voltage at terminal 14. Schottky diode 16 becomes conductive at the natural threshold voltage so that Schottky device 10 becomes conductive at the threshold voltage of Schottky diode 16. As the forward bias increases, transistor 18 will become a little more conductive but Schottky diode 16 clamps terminals 12 and 14 in normal Schottky diode fashion so that only minimal voltage increase is possible as the current increases. The body of transistor 18 is tied to the elevated voltage at terminal 12 to aid in the conductivity of transistor 18, but the body could be tied to the first current electrode and the device would still exhibit Schottky diode behaviour.
• transistor 18 has the effect of clamping the voltage at the negative terminal of Schottky diode.
• transistor 18 having a threshold voltage of -0.2 volt, transistor 18 would become non-conductive when the voltage at contact 20 became approximately 0.5 to 1.0 volt greater than the voltage on terminal 12.
• the voltage across Schottky diode 16 is clamped at not greater than 0.5 to 1.0 volt. This prevents the leakage current from becoming greater than that for a reverse bias of 0.5 to 1.0 volt across Schottky diode 16 and thereby avoids the exponential increase that would occur if the reverse bias voltage on terminals 12 and 14 were applied across Schottky diode 16.
• Shown in FIG. 3 is the I-V curve in the reverse bias direction for Schottky device 10.
• Schottky device 10 of Schottky diode 16 and transistor 18 as a device structure comprising a substrate 24 of P-type silicon, a well 26 of P-type in substrate 24, a well 28 of N-type in substrate 24, a contact region 30 doped to P+, an isolation region 32 adjacent to contact region 30, contact 20 which is an N+ region that encircles a region in well 26 and has a portion adjacent to isolation region 32, channel region 22 that is doped to N- and is adjacent to a portion of contact 20, an isolation region 34 spaced from channel region 22, contact region 36 doped to N+, a metal 38 as the negative terminal of Schottky diode 16 that spans the portion encircled by region 20, a gate 40 over channel region 22 and a portion of isolation 34 as well as the portion of well 53 that is between channel 22 and isolation 34, and a gate dielectric 42 under gate 40.
• Gate dielectric 42 and gate 40 are designed to overlap both regions 26 and 28.
• Contact 20 and regions 30, 32, 20, 22, 34, and 36 extend downward a short distance from the surface of substrate 24.
• Contact region 30 serves as a contact to well 26 and thus for the body of transistor 18 and the positive terminal of Schottky diode 16.
• Contact 20 serves as the conventional guard ring for Schottky diode 16, the first current electrode of transistor 18, and as the contact between the negative terminal of Schottky diode 16 and the first current electrode of transistor 18.
• Channel region 22 extends from well 26 to well 28. Isolation region 34 separates contact region 36 from channel 22 to increase the breakdown voltage of transistor 18.
• This type of arrangement of a transistor having a well body, such as well 28, be partially under the channel and a region 28 that supports high voltage in the off state between gate 40 and contact 36 is a well known structure for increasing breakdown voltage of a MOS transistor.
• Contact region 36 is a point of contact for the negative terminal 14 of Schottky device 10.
• This device structure shown in FIG. 4 combines a conventional Schottky diode with a conventional high breakdown voltage MOS structure in a manner that achieves the circuit of FIG. 2 and with some efficiencies in integration.
• the breakdown voltage is adjustable using this type of structure by adjusting, for example, the width of isolation region 34 and the distance of region 36 from the edge of gate 40.
• One efficiency in this embodiment of the invention is in using contact region 30 as both the positive terminal contact of the Schottky diode and the body contact of the transistor.
• Another efficiency is using the conventional guard ring of the Schottky diode as the drain of the transistor and thereby also achieving the contact between the Schottky diode and the transistor.
• FIG. 5 Shown in FIG. 5 is an alternative device structure 50 for achieving the circuit of FIG. 2.
• Device structure 50 comprises a substrate 51 of P type, a P well 52, an N well 53, a region 54 doped to P+, a region 56 doped to N- adjacent to region 54 and crossing from well 52 to well 53, an isolation 62 spaced from channel region 56, a region 64 that is doped to N+ and adjacent to region 64, a metal 58 over portions of regions 54 and 56, a gate 60 spaced from region 58 and overlying portions of regions 52, 53, and 56 and isolation region 62, and a gate dielectric under gate 60.
• the implant that creates channel region 56 also is received by well 53 and does increase the N-type doping concentration at the surface of well 53 but not sufficiently to cause it to be N+.
• the positive terminal of the Schottky diode is metal 58 and the negative terminal is the portion of region 56 under metal 58.
• the transistor has a first current electrode contact to the Schottky diode through the region 56 in which the gate 60 is spaced from metal 58.
• the channel that provides for the transistor being depletion mode is the portion of region 56 under gate 60.
• Well 53, region 62, and region 64 provide for an increased breakdown voltage transistor, and region 64 also provides the contact for the negative terminal of the Schottky device 50.
• Terminal 57 is contacted to both metal 58 and gate 60 as the positive terminal for Schottky device 50.
• Region 54 provides for the contact to the body of the transistor to the positive terminal 57 through metal 54.
• FIG. 6 Shown in FIG. 6 is a second alternative Schottky device 70 for forming the circuit of FIG. 2.
• Schottky device 70 comprises a substrate 72, a region 74 of P+, a region 76 of N- adjacent to region 74, a region of N+ adjacent to region 76, a metal 80 over a portion of region 74 and a portion of region 76, a gate 82 over a portion of region 76 and spaced from metal 80, and a gate dielectric 83 under gate 82.
• Gate 82 is separated from region 78 by region 76.
• Positive terminal 71 of Schottky device 70 is connected to both gate 82 and metal 80. The body contact to the transistor is from terminal 71 through metal 80 to region 74 and thereby to substrate 72.
• Metal 80 is the positive terminal of the Shottky diode.
• the portion of region 76 under metal 80 is the negative terminal of the Schottky diode.
• the portion of region 76 where metal 80 and gate 82 are spaced apart is the first current electrode of the transistor as well as the contact between the first current electrode of the transistor and the negative terminal of the Schottky diode.
• the channel of the transistor is the portion of region 76 under gate 82.
• the second current electrode is the portion of region 76 that is adjacent to region 78 and not under gate 82.
• the negative terminal of Schottky device 70 is terminal 81 connected to region 78 which in turn is connected to the second current electrode of the transistor. This approach relies on the portion of region 76 between gate 82 and region 78 to achieve the needed breakdown voltage.
• a Schottky diode is considered to be a diode formed of a metal region in contact with a semiconductor region sufficiently doped to form a diode having a forward biased threshold lower than that of a PN junction.
• a Schottky-like device is a structure having a characteristic curve like that shown in FIG. 1 and includes Schottky diodes and other structures such as that shown in US Patent Number 6,476,442 Bl which is titled "Pseudo- Schottky Diode.”
• a Schottky device is a structure that includes a Schottky-like device and enhancements in which the enhancements improve the performance of the Schottky-like device.
• FIG. 7 Shown in FIG. 7 is a circuit diagram showing a Schottky device 84 that utilizes a Schottky-like device combined with a depletion transistor in the manner described for combining a Schottky diode and a depletion transistor.
• Schottky device 84 comprises a transistor 90 and a transistor 92.
• transistor 90 is a non-depletion transistor with a very low threshold voltage, such as not greater than 0.2 volt, but not a negative one.
• Transistor 92 is the depletion transistor. In this embodiment both are N channel.
• Transistor 90 is connected in a manner that it operates as a Schottky-like device.
• Transistor 90 has a first current electrode connected to terminal 86 which is the positive terminal of Schottky device 84, a gate connected to terminal 86, a body connected to terminal 86, and a second current electrode as the negative terminal of the Schottky-like device.
• Transistor 92 has a first current electrode connected to the second current electrode of transistor 90, a gate connected to terminal 86, a body connected to terminal 86, and a second current electrode connected to a terminal 88, which is the negative terminal of Schottky device 84.

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• Electrodes Of Semiconductors (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Logic Circuits (AREA)
• Amplifiers (AREA)

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• 2004
  • 2004-05-28 US US10/856,602 patent/US7071518B2/en not_active Expired - Fee Related
• 2005
  • 2005-04-26 JP JP2007515097A patent/JP5290574B2/ja not_active Expired - Fee Related
  • 2005-04-26 EP EP05739044A patent/EP1749343A4/en not_active Withdrawn
  • 2005-04-26 CN CNB2005800173372A patent/CN100539181C/zh not_active Expired - Fee Related
  • 2005-04-26 WO PCT/US2005/014323 patent/WO2005119913A2/en not_active Ceased
  • 2005-05-19 TW TW094116366A patent/TWI372470B/zh not_active IP Right Cessation

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