WO2005119744A1 - pn接合を有する化合物半導体基板の製造方法 - Google Patents
pn接合を有する化合物半導体基板の製造方法 Download PDFInfo
- Publication number
- WO2005119744A1 WO2005119744A1 PCT/JP2005/010210 JP2005010210W WO2005119744A1 WO 2005119744 A1 WO2005119744 A1 WO 2005119744A1 JP 2005010210 W JP2005010210 W JP 2005010210W WO 2005119744 A1 WO2005119744 A1 WO 2005119744A1
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- WIPO (PCT)
- Prior art keywords
- substrate
- layer
- compound semiconductor
- compound
- diode
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 68
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 150000001875 compounds Chemical class 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title abstract description 11
- 238000004519 manufacturing process Methods 0.000 title abstract description 6
- 238000000926 separation method Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 30
- 238000000407 epitaxy Methods 0.000 description 17
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 13
- 238000004140 cleaning Methods 0.000 description 8
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000002346 layers by function Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000036571 hydration Effects 0.000 description 1
- 238000006703 hydration reaction Methods 0.000 description 1
- 239000010865 sewage Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
- H01L21/02661—In-situ cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
Definitions
- the present invention relates to a method for producing a compound semi-finished with png ⁇ by an epitaxial growth method including a step (the method of the present substrate).
- a compound semi-layer (a ⁇ long process for growing this layer at the same temperature as the epitaxy process before the mask is formed) the method comprising (e.g., JP-a-11- 204829 Gooyakeko g), also, on the compound semiconductor function layer grown based on, form a form a mask made of S I_ ⁇ 2, compound semi # I present layer
- a method involving epitaxial growth at a higher Jt than the epitaxial step before the mask is formed: a method including about 5 steps (for example, Japanese Patent Laid-Open No. 6-551-).
- the pn age (including the p-i_n age where the intermediate layer sandwiched between the p and n layers is ⁇ ffif).
- the substrate is made of SSi.
- Compound semi-conductor (This substrate is a field effect transistor (£ ield Effect Transistor), Heteroha, bipolar transistor g'e terro ipo 1 ar Trans is tor), Ray diode (J ⁇ aser Di ode)> It is used for compound semiconductor devices such as photo diodes. Due to the performance improvement, these compounds are required to have improved electrical characteristics. In addition, it is required that the compound used for $ ⁇ has a high electrical property.
- An object of the present invention is to provide a method of a compound semi-substrate suitable for $ 3 ⁇ 4 ⁇ of a semi-compound having high electrical characteristics.
- the present inventors have studied the compound half-year-old (the ⁇ i ⁇ method of the present substrate) by the S3 ⁇ 4i method including a long process, and as a result, have come to ⁇ fitT of the present invention.
- the present invention relates to a ⁇ ⁇ method for a semi-substrate having a ⁇ age, which includes an epitaxial process, a fi process, a subsequent process, and other processes of the invention. Offers less than the highest level of the epitaxy process before it is presented.
- a compound half having high electrical characteristics such as a diode having a small current, a diode having a high amplification factor, and a transistor having a high amplification factor, is suitable for the S ⁇ of a single house.
- This substrate is obtained.
- FIG. 1 shows the flow chart of each step in the method of the present invention.
- FIG. 2 shows the current-voltage characteristics of the pn diode obtained according to the present invention.
- Fig. 3 shows the current of the pn diode which is $ ⁇ under the condition that 'the epitaxy before the iimft: the highest in the R process, and the magic: the highest in the process after the SI process' is high. Is shown.
- FIG. 4 shows a layer; lit of each step at the time of a pn diode in the embodiment of the present invention.
- FIG. 5 shows the current-voltage characteristics of the pn diode of Difficult Example 1.
- FIG. 6 shows the current-3 ⁇ 41 characteristic of the pn diode of Difficult Example 2.
- FIG. 7 shows the current-voltage characteristics of the pn diode of Comparative Example 1, the best mode for carrying out the invention.
- the S3 ⁇ 4g ⁇ method of the compound semi-substrate of the present invention is a method in which a compound active layer is grown on the substrate for 1 h by HI-Epitaxial growth to make a pn-aged compound semi-substrate difficult. Success: Includes long and long processes.
- the compound semi-conductor of the present invention (in the method i of the present substrate, the maximum temperature in the step after the epitaxial growth step Sr is lower than the maximum temperature in the epitaxial growth step before the step Sr. Epitaxy before the selection step)
- the difference between the highest step in the growth step and the highest step in the step after the epitaxial step is preferably 30 ° C. or higher, more preferably 40 ° C. or higher, and preferably 300 ° C. or lower. It is.
- the step after the epitaxy process of about 51 ° C. is preferably at least 350 ° C. and no more than 720 ° C.
- Epitaxy before ⁇ fi process S process is sickle sewage satisfies S condition, depending on the process after the terrible epitaxy growth process. Fig range from 750C to 750C.
- epitaxy growth step before the long step in this specification refers to all of the epitaxy growth steps performed before the « « X step (if there is a 33 ⁇ 4 step of »: the first step). However, this does not include, for example, a substrate cleaning step (without the epitaxial growth) performed before the epitaxial growth step S.
- Such a substrate cleaning step is performed during the epitaxy step S. ⁇ ⁇ Higher (for example, Japanese Patent Laid-Open Publication No. 5-229231) and higher than the maximum temperature in the epitaxy growth process: There is 3 ⁇ 4 ⁇ , but even at this age, the epitaxy process starts. Before Therefore, it does not affect the compound semi-employed layer by epitaxial growth.
- the term “epitaxy formation: about 5 red hydration steps” refers to all of the steps performed after the epitaxy formation step S. If there is a »epitaxy growth step, the last epitaxy formation step will be performed. All of the steps that will be performed later.
- the "if degree of the epitaxial growth process” is a compound semiconductor whose highest value satisfies the lower condition than the highest value in the "epitaxial growth before long process; R process”.
- the method includes a step of epitaxially growing the substrate, and a step of forming a layer by the epitaxial growth, and includes, for example, a substrate cleaning step and a mask forming step immediately before the transfer length, which are the selected length.
- the maximum temperature in the process after the process is the same as or higher than the maximum ⁇ S in the epitaxial growth process before the selective growth process: ⁇ , separation, half of the compound obtained ⁇
- the electrical characteristics of the device deteriorate It is not clear why, but it is based on the following: First, the occurrence of structural elements occurs at the interface of each layer, and the generation of energy at the interface of each layer is severe. Characteristics is reduced. Secondly, HenYuzuru Coefficient difference force because the mask and the compound semiconductor functional layer such as sio 2, best 3 ⁇ 4g in selected views length step subsequent steps are the Most stress increases, dislocation occurs Next, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
- the semi-elevating GaAs substrate is placed in a metalorganic chemical vapor deposition (MOCVD) furnace, and the temperature is raised while flowing arsine gas. Next, in order to remove oxides and the like adhering to the substrate surface by
- MOCVD metalorganic chemical vapor deposition
- Sio 2 ⁇ m is deposited on the obtained epitaxial substrate and an opening is formed by etching.
- the epitaxial substrate with Si 2 pattern formed in the MOCVD furnace is used for substrate cleaning and p + -GaAs layer growth.
- Figure 2 shows the obtained current-voltage characteristics of the device having P ⁇ ⁇ ⁇ .
- This element has the rectifying action shown in Fig. 2.
- the current does not flow except for the leakage current in the ⁇ direction, which does not supply or operate the bias ( ⁇ i). In the forward bias direction, the current flows.
- the simplest element utilizing this phenomenon is the ⁇ diode.
- Figures 4 (a) to 4 (c) show the layer structure (cross-sectional view) of each process at ⁇ ⁇ age ⁇ ?
- ptt®5 was formed on the p + -GaAs layer 4 by the sputtering method (Fig. 4 (c)).
- FIG. 5 shows the current-temperature characteristics of the obtained pn diode. This pn diode had very low reverse leakage current. Difficult case 2
- FIG. 7 shows the current distribution characteristics of the obtained pn diode. This pn diode had very large »leakage current.
- MOCVD MOCVD
- JFET ⁇ mm field effect transistor
- HBT heterobipolar transistor
- the compound layer is composed of an organic metal layer and an organic metal layer.
- MOCVD grown by eye growth
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Bipolar Transistors (AREA)
- Junction Field-Effect Transistors (AREA)
- Led Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/597,711 US7595259B2 (en) | 2004-06-01 | 2005-05-27 | Method for manufacturing compound semiconductor substrate with pn junction |
KR1020067026604A KR101152017B1 (ko) | 2004-06-01 | 2005-05-27 | Pn 접합을 갖는 화합물 반도체 기판의 제조 방법 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-162821 | 2004-06-01 | ||
JP2004162821A JP4661088B2 (ja) | 2004-06-01 | 2004-06-01 | pn接合を有する化合物半導体基板の製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005119744A1 true WO2005119744A1 (ja) | 2005-12-15 |
Family
ID=35463118
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2005/010210 WO2005119744A1 (ja) | 2004-06-01 | 2005-05-27 | pn接合を有する化合物半導体基板の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7595259B2 (ja) |
JP (1) | JP4661088B2 (ja) |
KR (1) | KR101152017B1 (ja) |
TW (1) | TWI378495B (ja) |
WO (1) | WO2005119744A1 (ja) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041321A (ja) * | 1996-07-26 | 1998-02-13 | Sony Corp | バイポーラトランジスタの製造方法 |
JP2003077844A (ja) * | 2001-09-03 | 2003-03-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2003124124A (ja) * | 2001-10-12 | 2003-04-25 | Ngk Insulators Ltd | 半導体素子、エピタキシャル基板、半導体素子の製造方法、及びエピタキシャル基板の製造方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4686554A (en) * | 1983-07-02 | 1987-08-11 | Canon Kabushiki Kaisha | Photoelectric converter |
US4826784A (en) * | 1987-11-13 | 1989-05-02 | Kopin Corporation | Selective OMCVD growth of compound semiconductor materials on silicon substrates |
US4910165A (en) * | 1988-11-04 | 1990-03-20 | Ncr Corporation | Method for forming epitaxial silicon on insulator structures using oxidized porous silicon |
US5076860A (en) * | 1989-01-13 | 1991-12-31 | Kabushiki Kaisha Toshiba | Algan compound semiconductor material |
JP2793837B2 (ja) * | 1989-05-10 | 1998-09-03 | 株式会社日立製作所 | 半導体装置の製造方法およびヘテロ接合バイポーラトランジスタ |
US5161167A (en) * | 1990-06-21 | 1992-11-03 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor laser producing visible light |
WO1992015113A1 (en) * | 1991-02-19 | 1992-09-03 | Fujitsu Limited | Semiconductor device having an isolation region enriched in oxygen and a fabrication process thereof |
JPH0529231A (ja) | 1991-07-23 | 1993-02-05 | Sumitomo Electric Ind Ltd | Iii−v族化合物半導体の気相成長方法 |
JPH05109753A (ja) * | 1991-08-16 | 1993-04-30 | Toshiba Corp | バイポーラトランジスタ |
JPH0562906A (ja) * | 1991-08-30 | 1993-03-12 | Hitachi Ltd | 半導体装置における積層構造の形成方法 |
JP2733167B2 (ja) | 1992-06-23 | 1998-03-30 | 日本電信電話株式会社 | 化合物半導体薄膜の選択的成長方法 |
US5762706A (en) * | 1993-11-09 | 1998-06-09 | Fujitsu Limited | Method of forming compound semiconductor device |
JP3783244B2 (ja) * | 1995-04-04 | 2006-06-07 | 三菱化学株式会社 | Iii−v族化合物半導体発光素子の製造方法 |
US6348096B1 (en) * | 1997-03-13 | 2002-02-19 | Nec Corporation | Method for manufacturing group III-V compound semiconductors |
JPH11204829A (ja) | 1998-01-13 | 1999-07-30 | Sharp Corp | 半導体素子の製造方法及びその半導体素子 |
US6252261B1 (en) * | 1998-09-30 | 2001-06-26 | Nec Corporation | GaN crystal film, a group III element nitride semiconductor wafer and a manufacturing process therefor |
TW518767B (en) * | 2000-03-31 | 2003-01-21 | Toyoda Gosei Kk | Production method of III nitride compound semiconductor and III nitride compound semiconductor element |
JP4540201B2 (ja) * | 2000-09-13 | 2010-09-08 | 独立行政法人産業技術総合研究所 | ZnO系酸化物半導体層を有する半導体装置の製法 |
EP1376664A4 (en) * | 2001-03-29 | 2009-08-19 | Toyoda Gosei Kk | PROCESS FOR PREPARING A SEMICONDUCTOR WITH GROUP III NITRIDE COMPOSITION AND SEMICONDUCTOR COMPONENT WITH GROUP III NITRIDE COMPOSITION |
US6939730B2 (en) * | 2001-04-24 | 2005-09-06 | Sony Corporation | Nitride semiconductor, semiconductor device, and method of manufacturing the same |
US6936357B2 (en) * | 2001-07-06 | 2005-08-30 | Technologies And Devices International, Inc. | Bulk GaN and ALGaN single crystals |
JP3912117B2 (ja) * | 2002-01-17 | 2007-05-09 | ソニー株式会社 | 結晶成長方法、半導体発光素子及びその製造方法 |
-
2004
- 2004-06-01 JP JP2004162821A patent/JP4661088B2/ja not_active Expired - Fee Related
-
2005
- 2005-05-27 KR KR1020067026604A patent/KR101152017B1/ko not_active IP Right Cessation
- 2005-05-27 WO PCT/JP2005/010210 patent/WO2005119744A1/ja active Application Filing
- 2005-05-27 US US11/597,711 patent/US7595259B2/en not_active Expired - Fee Related
- 2005-05-30 TW TW094117633A patent/TWI378495B/zh not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1041321A (ja) * | 1996-07-26 | 1998-02-13 | Sony Corp | バイポーラトランジスタの製造方法 |
JP2003077844A (ja) * | 2001-09-03 | 2003-03-14 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2003124124A (ja) * | 2001-10-12 | 2003-04-25 | Ngk Insulators Ltd | 半導体素子、エピタキシャル基板、半導体素子の製造方法、及びエピタキシャル基板の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
KR101152017B1 (ko) | 2012-06-08 |
JP2005347366A (ja) | 2005-12-15 |
US7595259B2 (en) | 2009-09-29 |
TW200605193A (en) | 2006-02-01 |
TWI378495B (en) | 2012-12-01 |
US20070232018A1 (en) | 2007-10-04 |
KR20070032696A (ko) | 2007-03-22 |
JP4661088B2 (ja) | 2011-03-30 |
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