WO2005104226A2 - Verfahren zur herstellung von durchkontaktierungen durch eine kunststoffmasse und halbleiterbauteil mit derartigen durchkontaktierungen - Google Patents
Verfahren zur herstellung von durchkontaktierungen durch eine kunststoffmasse und halbleiterbauteil mit derartigen durchkontaktierungen Download PDFInfo
- Publication number
- WO2005104226A2 WO2005104226A2 PCT/DE2005/000754 DE2005000754W WO2005104226A2 WO 2005104226 A2 WO2005104226 A2 WO 2005104226A2 DE 2005000754 W DE2005000754 W DE 2005000754W WO 2005104226 A2 WO2005104226 A2 WO 2005104226A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- composite body
- semiconductor
- conductive particles
- plastic
- plated
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01052—Tellurium [Te]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01061—Promethium [Pm]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01084—Polonium [Po]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0373—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement containing additives, e.g. fillers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0206—Materials
- H05K2201/0215—Metallic fillers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
- H05K2201/0203—Fillers and particles
- H05K2201/0242—Shape of an individual particle
- H05K2201/0257—Nanoparticles
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/10—Using electric, magnetic and electromagnetic fields; Using laser light
- H05K2203/105—Using an electrical field; Special methods of applying an electric potential
Definitions
- the invention relates to a method for producing vias and a semiconductor component with such vias. Furthermore, the invention relates to horizontally and vertically staggered semiconductor modules with such vias.
- the semiconductor components of the module are arranged next to one another and in the case of a vertically staggered semiconductor module the semiconductor components are stacked on top of one another.
- the semiconductor components are electrically coupled to a semiconductor module via a rewiring layer.
- the semiconductor components of the stack are coupled horizontally via rewiring layers and electrically connected to one another via the plated-through holes.
- the object of the invention is to provide a method for producing through-plating and a semiconductor component with such through-plating, which is inexpensive, has increased reliability and can be implemented in the smallest possible space.
- a method for producing plated-through holes through a plate-shaped composite body is presented, which has semiconductor chips and a plastic compound.
- a plate-shaped composite body is first produced.
- the top of the plate-shaped composite body has a coplanar surface with active top sides of semiconductor chips and with surfaces of an insulating plastic compound filled with conductive particles. Despite these conductive particles in the plastic mass, it initially remains completely insulating. This composite body is then inserted between two high-voltage tip electrodes.
- the tip electrodes are aligned on the top and the bottom of the composite body in the area of the plastic mass such that the tips of the tip electrodes face each other at the positions at which plated-through holes are to be produced by the plastic mass filled with conductive particles.
- a high voltage is applied to the tip electrodes after alignment. The high voltage is then switched off and finally the plated-through plate-shaped composite body is removed from the tip electrodes.
- This method has the advantage that through contacts are formed at all positions that are to have plated-through holes, since under the high voltage the conductive particles produce a short circuit, through which an energy flow flows, which either welds the conductive particles together or sinters them together. At the same time, the plastic present between the particles is converted into conductive carbon bridges.
- This method is particularly effective when the composite body is made extremely thin in that the thickness of the composite body corresponds to the thickness of semiconductor wafers or printed circuit boards. In order to form such plated-through holes, it is therefore not necessary to make through holes through the plastic. A deposition process of conductive material in through openings is also eliminated. The masking of the composite body is completely eliminated, so that expensive photolithography techniques can be saved.
- the introduction of the through contacts using the high voltage cannot be compared to a stoving technique, since no combustion processes are associated with this method.
- the method can be compared here with the spot welding known in the automotive industry from the industrial sector, but it is forbidden to emulate this process, especially since in the case of the present invention it is a plastic in plate form filled with conductive particles and not massive metal sheets that can be mechanically connected.
- the diameter of the plated-through holes in the method according to the invention is also in the range from submicrometer dimensions to dimensions in the range from a few tens of micrometers or ⁇ m.
- the through-hole column is not shaped uniformly, with a smooth outer surface, but is based on the most favorable energy flow from one tip electrode to the other tip electrode through the plastic filled with conductive particles.
- the plated-through holes therefore do not have a smooth column casing as the outer contour, but instead show a frayed cross-section, which is, however, in the positions specified by the tips on both sides of the composite body.
- the two tip electrodes are aligned such that they form one Have a safety distance from the active top sides of the semiconductor chips embedded in the plastic compound. This safety distance is necessary to prevent the semiconducting material from being trapped in the current path of the vias that form.
- the safety distance depends on the high voltage with which the tip electrodes are operated and is between 0.2 and 5 mm.
- the semiconductor chips are arranged in rows and columns in the plastic mass, and the plated-through holes through the plastic are made around the semiconductor chips.
- the edge sides and the back of the semiconductor chips are surrounded by plastic mass, while the active top side has a coplanar surface with the surfaces of the plastic mass.
- a plurality of tip electrodes are arranged on a common electrode surface of a multi-tip electrode.
- the multi-tip electrode corresponds to the size of the composite body.
- the tips of two multiple tip electrodes can thus advantageously be aligned with the positions of vias to be formed on the top and bottom of the composite body.
- a large number of vias between the top and bottom of the composite body is realized with a single via step.
- a large number of through contacts are thus formed at predetermined positions of a plate-shaped composite body, such as a disk or a plate.
- a high voltage between 1 and 10 kV is applied to the tip electrode to introduce the vias.
- the high voltage can also be applied to the tip electrodes in the form of pulse trains. In this case, high voltages are applied to the tip electrodes by an order of magnitude, the high voltage being brought to zero in the pulse pauses.
- the plastic mass is preferably filled with conductive particles in the range from 80 to 98% by weight with a remainder of the insulating plastic mass.
- the degree of filling depends in part on the specific weight of the conductive particles and is to be set higher if the specific weight of the conductive particles is large compared to the specific weight of the plastic mass.
- nanoparticles are preferably used as metallic particles, which agglomerate in such a plastic mass to form nanoparticle heaps and thus enable through-contacting via nanoparticle agglomerates.
- Another possibility of filling the plastic with conductive particles is to use conductive silver and / or copper particles in the range from 80 to 98% by weight with a remainder of insulating plastic material for the degree of filling. Attention is paid to the fact that with a defined filling level, the plastic mass initially still has an insulating effect and only through-contacts are created with the treatment by a high voltage. In the case of metallic particles in particular, it has proven useful to add a reducing medium to the plastic mass. This eliminates the risk of oxidation For example, the copper is reduced when making the vias.
- Another aspect of the invention provides a semiconductor component with a semiconductor chip and a plastic compound.
- This semiconductor component is based on a plate-shaped composite body, the upper side of which forms a coplanar surface which has the active upper side of the semiconductor chip and a surface of the insulating plastic compound filled with conductive particles.
- plated-through holes extend through the composite body from the top to the bottom of the composite body. These vias have sintered or welded together conductive particles.
- the plated-through holes have a safety distance from the active upper side of the semiconductor chip embedded in the plastic compound. This safety distance between vias and the active top of the semiconductor chip is process-related and larger than for vias that would be produced with photoresist technology and deposition techniques.
- the conductive particles have nanoparticles which can consist of carbon or metals. Such nanoparticles have the advantage that, on the one hand, they are finely distributed in the volume of the plastic mass and, on the other hand, they can condense to agglomerates and thus can form conductor tracks in the form of vias through the plastic aces.
- nanoparticles there are also particles such as those used in conductive adhesives in the form of conductive silver and / or Copper in the plastic mass possible.
- the proportion of conductive particles is 80 to 98% by weight of the plastic mass, which ensures that, on the one hand, the plastic mass remains insulating and that a through-contact is only possible where vias were produced using the method according to the invention.
- contact areas on the active top side of the semiconductor chip that are connected to the vias via rewiring lines. These rewiring lines can be applied after the via step, so that the contact area of the active top side of the semiconductor chip can be accessed both from the bottom side of the semiconductor component and from the top side of the semiconductor component.
- a further aspect of the invention relates to a semiconductor module with a plurality of semiconductor chips in a plastic compound, which form a plate-shaped composite body, the upper side of which forms a coplanar surface from active upper sides of the semiconductor chip and surfaces of the insulating plastic compound filled with conductive particles.
- the vias extend through the plastic mass from the top of the composite body to the bottom of the composite body. These vias consist of sintered or welded together conductive particles of the plastic mass filled with conductive particles.
- the semiconductor module can have horizontally staggered semiconductor components which are electrically connected to one another via a rewiring layer on the coplanar surface.
- the vias point at their puncture points through the composite body on the top and the bottom side of the composite body on external contact surfaces.
- Extremely complex semiconductor modules can thus be produced with the simplest of means.
- Wafer level package concept are produced, both in a horizontally staggered manner and in a vertically staggered manner to form semiconductor modules.
- the plastic used is mixed with a high proportion of electrically conductive metallic nanoparticles or filled, or this plastic mass is prepared accordingly and delivered mixed.
- Other electrically conductive particles can also be used for the method according to the invention.
- soot particles or metal-coated polymer particles can be used to implement the corresponding plated-through holes.
- the nanoparticles are distributed randomly in the matrix, so that no electrical connection is yet available.
- a high electromagnetic field is then applied to the entire composite body of the wafer level package by means of the multi-tip electrodes, the nanoparticles melting along the field lines, or caking or sintering. This results in an electrically conductive via, which has the advantage that both on the underside and on the 0 appropriate rewiring layers can be applied on top for connecting additional packages.
- FIG. 1 shows a schematic cross section through a semiconductor module according to a first embodiment of the invention
- Figure 2 shows a schematic cross section through a semiconductor device according to a second embodiment of the invention
- FIGS. 3-6 show schematic cross sections through intermediate products of individual method steps of a method in the production of a composite plate with plated-through holes of a third embodiment of the invention
- Figure 3 shows a schematic cross section through a composite plate without vias
- FIG. 4 shows a schematic cross section through the composite panel according to FIG. 3 with attached multi-tip electrodes
- FIG. 5 shows a schematic cross section through the composite plate according to FIG. 4 after the through contacts have been produced
- FIG. 6 shows a schematic cross section through the composite plate according to FIG. 5 after the application of external contact areas and a wiring layer
- FIG. 7 shows a schematic cross section of a semiconductor stack according to a fourth embodiment of the invention.
- FIG. 1 shows a schematic cross section through a semiconductor module 15 according to a first embodiment of the invention.
- this semiconductor module 15 has three semiconductor chips 3 with the active top sides 7. These three semiconductor chips 3 are embedded with their side edges and their rear sides in a plastic compound 4.
- the upper side 5 of the composite body 2 carries a rewiring layer on the coplanar surface 6 26, which has external contact areas 25 in the area of the plastic surfaces 8 and contact areas 21 in the area of the active upper sides 7 of the semiconductor chips 3.
- rewiring lines 22 are arranged, which connect the contact areas 21 of the semiconductor chips 3 to the external contact areas 25.
- These external contact surfaces 25 on the upper side 5 of the composite body 2 are connected to external contact surfaces 25 on the lower side 12 of the composite body 2 via plated-through holes 1. There is thus access, both via the external contacts 25 on the top 5 and via the external contacts 25 on the underside 12 of the semiconductor module 15 to the semiconductor chips 3 and their contact surfaces 21.
- the plastic mass 4 has conductive nanoparticles 9, with which the plastic mass 4 is filled with a weight fraction relative to the plastic mass 4 of between 80 and 98% by weight, so that the plastic mass 4 is still insulating, only the plated-through holes 1 has agglomerated, welded or sintered nanoparticles 9 which form an electrical path through the plastic mass 4 filled with conductive nanoparticles 9.
- These particles can also be conductive soot particles or metal-coated polymer particles.
- the through-contacts 1 have frayed cross-sections due to their manufacturing process, which do not form smooth pillar shells. The course within the plastic compound 4 is also not straight, but is formed according to the cheapest current path when the through-contacts are produced.
- the advantage of this semiconductor module 15 is that it can be expanded as desired by stacking several semiconductor modules 15 on top of one another.
- FIG. 2 shows a schematic cross section through a semiconductor component 16 according to a second embodiment of the invention.
- This semiconductor component 16 consists of a composite body 2 with a plastic mass 4 and a semiconductor chip 3, 4 through contacts from the bottom 12 of the plastic mass filled with metallic particles 9
- the external contact surfaces 25 of the semiconductor component shown here 16 can have 2 solder balls on the top 5 as well as on the bottom 12 of the composite body or have flat external contacts.
- FIGS. 3 to 6 show schematic cross sections through intermediate products of individual process steps in the production of a composite plate 2 with plated-through holes 1 of a third embodiment of the invention.
- this composite plate 2 is the starting point for the method according to the invention, in which such a plate-shaped composite body 2 is produced, which has a coplanar surface 6 with active surfaces on its top 5 Has tops 7 of semiconductor chips 3 and surfaces 8 of an insulating plastic compound 4 filled with conductive particles 9.
- FIG. 4 shows a schematic cross section through the composite plate 2 according to FIG. 3 with attached multi-tip electrodes 19 and 20.
- These multi-tip electrodes 19 and 20 have an electrode surface 18 which corresponds in size to the size of the composite body 2.
- Tip electrodes 10 and 11, which have electrode tips 13, are distributed on the electrode surfaces 18, the lower tip electrodes 11 being aligned with the upper tip electrodes 10 in such a way that they assume positions of vias 1 to be formed on the top 5 and bottom 12 of the composite body 2.
- a safety distance s is maintained between the edges of the semiconductor chips 3 and the electrode tips 13 in order to prevent plated-through holes from forming over the semiconductor chip 3s between the electrode tips 13.
- FIG. 5 shows a schematic cross section through the composite plate 2 according to FIG.
- FIG. 6 shows the composite plate 1 according to FIG. 5 after the application of external contact areas 25 and a rewiring layer 26.
- the external contact areas 25 are arranged at the penetration points 23 and 24 of the plated-through holes 1 through the composite plate 2.
- the external contact surfaces 25 can be formed by depositing corresponding metal layers.
- rewiring lines 22 can be generated in the rewiring layer 26. These rewiring lines 22 connect the external contact areas 25 on the surfaces 8 of the plastic compound 4 to contact areas 21 of the semiconductor chips 3.
- FIG. 7 shows a schematic cross section of a semiconductor stack 17 according to a fourth embodiment of the invention.
- the semiconductor module 15 shown in FIG. 6 was applied vertically to an identical semiconductor module 27 of the same type with the same plated-through holes 1.
- external contact surfaces 25 are arranged, between which a solder resist layer 29 can be applied, in order to be able to do so during soldering of the semiconductor stack 17 on a superordinate circuit board to prevent the solder from spreading.
- a similar solder resist layer can also be arranged on the upper side of the semiconductor stack 17 in connection with the rewiring layer 26.
- a rewiring layer 26 is also arranged between the two stacked semiconductor modules 27 and 28 in order to electrically connect the semiconductor chips 3 of the lower semiconductor module 27 to the plated-through holes 1. There is thus access to all contact surfaces 21 of the semiconductor chips 3 arranged in the semiconductor stack 17 both from the top 5 and from the bottom 12.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/586,740 US7482198B2 (en) | 2004-04-26 | 2006-10-26 | Method for producing through-contacts and a semiconductor component with through-contacts |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004020497.7 | 2004-04-26 | ||
DE102004020497A DE102004020497B8 (de) | 2004-04-26 | 2004-04-26 | Verfahren zur Herstellung von Durchkontaktierungen und Halbleiterbauteil mit derartigen Durchkontaktierungen |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/586,740 Continuation US7482198B2 (en) | 2004-04-26 | 2006-10-26 | Method for producing through-contacts and a semiconductor component with through-contacts |
Publications (3)
Publication Number | Publication Date |
---|---|
WO2005104226A2 true WO2005104226A2 (de) | 2005-11-03 |
WO2005104226A3 WO2005104226A3 (de) | 2006-06-08 |
WO2005104226A8 WO2005104226A8 (de) | 2007-03-01 |
Family
ID=35197629
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2005/000754 WO2005104226A2 (de) | 2004-04-26 | 2005-04-25 | Verfahren zur herstellung von durchkontaktierungen durch eine kunststoffmasse und halbleiterbauteil mit derartigen durchkontaktierungen |
Country Status (3)
Country | Link |
---|---|
US (1) | US7482198B2 (de) |
DE (1) | DE102004020497B8 (de) |
WO (1) | WO2005104226A2 (de) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2001053A2 (de) | 2007-06-08 | 2008-12-10 | Valtion Teknillinen Tutkimuskeskus | Elektronikmodul, Herstellungsverfahren dafür und Anwendungen |
EP2001273A2 (de) | 2007-06-08 | 2008-12-10 | Valtion Teknillinen Tutkimuskeskus | Verfahren zur Herstellung von Leiterstrukturen und Anwendung |
EP2001272A2 (de) | 2007-06-08 | 2008-12-10 | Valtion Teknillinen Tutkimuskeskus | Verfahren und Vorrichtung im Zusammenhang mit Nanoteilchensystemen |
US9011762B2 (en) | 2006-07-21 | 2015-04-21 | Valtion Teknillinen Tutkimuskeskus | Method for manufacturing conductors and semiconductors |
CN108376519A (zh) * | 2018-04-27 | 2018-08-07 | 上海中航光电子有限公司 | 一种异形显示面板及其制作方法、显示装置 |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100842921B1 (ko) * | 2007-06-18 | 2008-07-02 | 주식회사 하이닉스반도체 | 반도체 패키지의 제조 방법 |
US7781877B2 (en) | 2007-08-07 | 2010-08-24 | Micron Technology, Inc. | Packaged integrated circuit devices with through-body conductive vias, and methods of making same |
KR100885924B1 (ko) | 2007-08-10 | 2009-02-26 | 삼성전자주식회사 | 묻혀진 도전성 포스트를 포함하는 반도체 패키지 및 그제조방법 |
TWI360207B (en) * | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
FR2923081B1 (fr) * | 2007-10-26 | 2009-12-11 | 3D Plus | Procede d'interconnexion verticale de modules electroniques 3d par des vias. |
WO2010063462A1 (en) * | 2008-12-02 | 2010-06-10 | Picodrill Sa | A method of introducing a structure in a substrate |
TWI456715B (zh) * | 2009-06-19 | 2014-10-11 | Advanced Semiconductor Eng | 晶片封裝結構及其製造方法 |
US8310835B2 (en) * | 2009-07-14 | 2012-11-13 | Apple Inc. | Systems and methods for providing vias through a modular component |
TWI466259B (zh) * | 2009-07-21 | 2014-12-21 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體的製造方法 |
TWI405306B (zh) * | 2009-07-23 | 2013-08-11 | Advanced Semiconductor Eng | 半導體封裝件、其製造方法及重佈晶片封膠體 |
WO2011020563A1 (en) * | 2009-08-19 | 2011-02-24 | Picodrill Sa | A method of producing an electrically conducting via in a substrate |
US8242543B2 (en) | 2009-08-26 | 2012-08-14 | Qualcomm Incorporated | Semiconductor wafer-to-wafer bonding for dissimilar semiconductor dies and/or wafers |
US20110084372A1 (en) * | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US8378466B2 (en) * | 2009-11-19 | 2013-02-19 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with electromagnetic interference shielding |
TWI497679B (zh) * | 2009-11-27 | 2015-08-21 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US8372689B2 (en) * | 2010-01-21 | 2013-02-12 | Advanced Semiconductor Engineering, Inc. | Wafer-level semiconductor device packages with three-dimensional fan-out and manufacturing methods thereof |
US8320134B2 (en) * | 2010-02-05 | 2012-11-27 | Advanced Semiconductor Engineering, Inc. | Embedded component substrate and manufacturing methods thereof |
TWI411075B (zh) * | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8278746B2 (en) | 2010-04-02 | 2012-10-02 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages including connecting elements |
US8624374B2 (en) | 2010-04-02 | 2014-01-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
JP2012209424A (ja) * | 2011-03-30 | 2012-10-25 | Tokyo Electron Ltd | 半導体装置の製造方法 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4694138A (en) * | 1984-02-10 | 1987-09-15 | Kabushiki Kaisha Toshiba | Method of forming conductor path |
US5813881A (en) * | 1994-02-08 | 1998-09-29 | Prolinx Labs Corporation | Programmable cable and cable adapter using fuses and antifuses |
DE19715898A1 (de) * | 1997-04-16 | 1998-10-22 | Polus Michael | Substrat mit Leiterbahnvernetzung und Verfahren zu dessen Herstellung |
US5906042A (en) * | 1995-10-04 | 1999-05-25 | Prolinx Labs Corporation | Method and structure to interconnect traces of two conductive layers in a printed circuit board |
US5906043A (en) * | 1995-01-18 | 1999-05-25 | Prolinx Labs Corporation | Programmable/reprogrammable structure using fuses and antifuses |
US20030057544A1 (en) * | 2001-09-13 | 2003-03-27 | Nathan Richard J. | Integrated assembly protocol |
US20030141105A1 (en) * | 1999-12-20 | 2003-07-31 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module, radio device having the same, and method for producing the same |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2902002A1 (de) * | 1979-01-19 | 1980-07-31 | Gerhard Krause | Dreidimensional integrierte elektronische schaltungen |
US5476714A (en) * | 1988-11-18 | 1995-12-19 | G & H Technology, Inc. | Electrical overstress pulse protection |
US5353498A (en) * | 1993-02-08 | 1994-10-11 | General Electric Company | Method for fabricating an integrated circuit module |
JPH0861331A (ja) * | 1994-08-15 | 1996-03-08 | Toranosuke Kawaguchi | 金属接合方法 |
US6190509B1 (en) * | 1997-03-04 | 2001-02-20 | Tessera, Inc. | Methods of making anisotropic conductive elements for use in microelectronic packaging |
DE10138278C1 (de) * | 2001-08-10 | 2003-04-03 | Infineon Technologies Ag | Elektronisches Bauteil mit aufeinander gestapelten elektronischen Bauelementen und Verfahren zur Herstellung derselben |
DE10153609C2 (de) * | 2001-11-02 | 2003-10-16 | Infineon Technologies Ag | Verfahren zur Herstellung eines elektronischen Bauelements mit mehreren übereinander gestapelten und miteinander kontaktierten Chips |
-
2004
- 2004-04-26 DE DE102004020497A patent/DE102004020497B8/de not_active Expired - Fee Related
-
2005
- 2005-04-25 WO PCT/DE2005/000754 patent/WO2005104226A2/de active Application Filing
-
2006
- 2006-10-26 US US11/586,740 patent/US7482198B2/en not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4694138A (en) * | 1984-02-10 | 1987-09-15 | Kabushiki Kaisha Toshiba | Method of forming conductor path |
US5813881A (en) * | 1994-02-08 | 1998-09-29 | Prolinx Labs Corporation | Programmable cable and cable adapter using fuses and antifuses |
US5906043A (en) * | 1995-01-18 | 1999-05-25 | Prolinx Labs Corporation | Programmable/reprogrammable structure using fuses and antifuses |
US5906042A (en) * | 1995-10-04 | 1999-05-25 | Prolinx Labs Corporation | Method and structure to interconnect traces of two conductive layers in a printed circuit board |
DE19715898A1 (de) * | 1997-04-16 | 1998-10-22 | Polus Michael | Substrat mit Leiterbahnvernetzung und Verfahren zu dessen Herstellung |
US20030141105A1 (en) * | 1999-12-20 | 2003-07-31 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module, radio device having the same, and method for producing the same |
US20030057544A1 (en) * | 2001-09-13 | 2003-03-27 | Nathan Richard J. | Integrated assembly protocol |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN Bd. 1996, Nr. 07, 31. Juli 1996 (1996-07-31) & JP 08 061331 A (KAWAGUCHI TORANOSUKE), 8. März 1996 (1996-03-08) * |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9011762B2 (en) | 2006-07-21 | 2015-04-21 | Valtion Teknillinen Tutkimuskeskus | Method for manufacturing conductors and semiconductors |
EP2001053A2 (de) | 2007-06-08 | 2008-12-10 | Valtion Teknillinen Tutkimuskeskus | Elektronikmodul, Herstellungsverfahren dafür und Anwendungen |
EP2001273A2 (de) | 2007-06-08 | 2008-12-10 | Valtion Teknillinen Tutkimuskeskus | Verfahren zur Herstellung von Leiterstrukturen und Anwendung |
EP2001272A2 (de) | 2007-06-08 | 2008-12-10 | Valtion Teknillinen Tutkimuskeskus | Verfahren und Vorrichtung im Zusammenhang mit Nanoteilchensystemen |
EP2001272A3 (de) * | 2007-06-08 | 2010-02-24 | Valtion Teknillinen Tutkimuskeskus | Verfahren und Vorrichtung im Zusammenhang mit Nanoteilchensystemen |
EP2001273A3 (de) * | 2007-06-08 | 2010-02-24 | Valtion Teknillinen Tutkimuskeskus | Verfahren zur Herstellung von Leiterstrukturen und Anwendung |
US7759160B2 (en) | 2007-06-08 | 2010-07-20 | Valtion Teknillinen Tutkimuskeskus | Method for producing conductor structures and applications thereof |
US7915097B2 (en) | 2007-06-08 | 2011-03-29 | Valtion Teknillinen Tutkimuskeskus | Electronic module with conductivity transformation region, method of manufacture and applications thereof |
US8916089B2 (en) | 2007-06-08 | 2014-12-23 | Valtion Teknillinen Tutkimuskeskus | Method and apparatus related to nanoparticle systems |
CN108376519A (zh) * | 2018-04-27 | 2018-08-07 | 上海中航光电子有限公司 | 一种异形显示面板及其制作方法、显示装置 |
CN108376519B (zh) * | 2018-04-27 | 2020-09-01 | 上海中航光电子有限公司 | 一种异形显示面板及其制作方法、显示装置 |
Also Published As
Publication number | Publication date |
---|---|
DE102004020497B3 (de) | 2006-01-19 |
WO2005104226A8 (de) | 2007-03-01 |
US7482198B2 (en) | 2009-01-27 |
WO2005104226A3 (de) | 2006-06-08 |
US20070099345A1 (en) | 2007-05-03 |
DE102004020497B8 (de) | 2006-06-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2005104226A2 (de) | Verfahren zur herstellung von durchkontaktierungen durch eine kunststoffmasse und halbleiterbauteil mit derartigen durchkontaktierungen | |
EP1716595B1 (de) | Halbleiterbauteil mit einem stapel aus halbleiterchips und verfahren zur herstellung desselben | |
DE102006004788B4 (de) | Halbleiterbauelement und Fertigungsverfahren für dieses | |
DE102005006995A1 (de) | Halbleiterbauteil mit Kunstoffgehäuse und Außenanschlüssen sowie Verfahren zur Herstellung desselben | |
WO2004015770A1 (de) | Mehrlagiger schaltungsträger und herstellung desselben | |
DE102006001767A1 (de) | Halbleitermodul mit Halbleiterchips und Verfahren zur Herstellung desselben | |
EP1620893B1 (de) | Verfahren zur herstellung eines nutzens und verfahren zur herstellung elektronischer bauteile mit gestapelten halbleiterchips aus dem nutzen | |
DE4446471C2 (de) | Verfahren zur Montage eines Chips auf einem flexiblen Schaltungsträger | |
EP1105942B1 (de) | Kontaktiervorrichtung, insbesondere zum ankontaktieren von elektrischen bauelementen und schaltungsträgern, sowie verfahren zu deren herstellung | |
DE102006053461A1 (de) | Mikroelektronische Baugruppe und Verfahren zum Herstellen einer mikroelektronischen Baugruppe | |
EP0995235B1 (de) | Kontakt für kleinste bondkontakte sowie verfahren zur herstellung eines kontaktes | |
EP0299136A2 (de) | Verfahren zur Herstellung einer Schaltungsplatte | |
DE10329143B4 (de) | Elektronisches Modul und Verfahren zur Herstellung desselben | |
DE102008009220A1 (de) | Verfahren zum Herstellen einer Leiterplatte | |
DE2611871A1 (de) | Elektrische schaltungsbaugruppe in mehrschichtbauweise und verfahren zu deren herstellung | |
WO2003100854A2 (de) | Elektronisches bauelement-modul und verfahren zu dessen herstellung | |
DE10255520B4 (de) | Verfahren zur elektrischen Kontaktierung mittels gefüllter Flüssigkeiten und elektronische Bauteile mit derartiger Kontaktierung | |
WO2001016876A2 (de) | Chipkarte und verfahren zur herstellung einer chipkarte | |
DE102021117573B4 (de) | Verfahren zur Herstellung einer elektrischen Verbindung zu einem elektronischen Bauteil und einer Chip-Baugruppe | |
DE10208910A1 (de) | Schaltungsträger und Verfahren zu dessen Herstellung | |
DE10334634B3 (de) | Verfahren zum seitlichen Kontaktieren eines Halbleiterchips | |
DE102009053255A1 (de) | Verfahren zum Herstellen einer Anordnung | |
DE102004029200B4 (de) | Verfahren zur Herstellung einer elektronischen Schaltung sowie ein Substrat für eine elektronische Schaltung | |
DE4239857A1 (de) | Leistungshalbleitermodul | |
EP4064804A1 (de) | Elektronisches bauelement und verfahren zur herstellung eines elektronischen bauelements |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KM KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SM SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GM KE LS MW MZ NA SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LT LU MC NL PL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
CFP | Corrected version of a pamphlet front page | ||
CR1 | Correction of entry in section i |
Free format text: IN PCT GAZETTE 44/2005 UNDER (22) REPLACE "24 APRIL 2005 (24.04.2005)" BY "25 APRIL 2005 (25.04.2005)" |
|
WWE | Wipo information: entry into national phase |
Ref document number: 11586740 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWW | Wipo information: withdrawn in national office |
Country of ref document: DE |
|
WWP | Wipo information: published in national office |
Ref document number: 11586740 Country of ref document: US |
|
122 | Ep: pct application non-entry in european phase |