Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W42/00—Arrangements for protection of devices
  • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
  • H01P1/00—Auxiliary devices
  • H01P1/20—Frequency-selective devices, e.g. filters
  • H01P1/2005—Electromagnetic photonic bandgaps [EPB], or photonic bandgaps [PBG]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
  • H01P1/00—Auxiliary devices
  • H01P1/16—Auxiliary devices for mode selection, e.g. mode suppression or mode promotion; for mode conversion
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
  • H05K1/0236—Electromagnetic band-gap structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W44/00—Electrical arrangements for controlling or matching impedance
  • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
  • H10W70/65—Shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/03—Use of materials for the substrate
  • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/07—Electric details
  • H05K2201/0707—Shielding
  • H05K2201/0715—Shielding provided by an outer layer of PCB
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/0929—Conductive planes
  • H05K2201/09336—Signal conductors in same plane as power plane
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09209—Shape and layout details of conductors
  • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
  • H05K2201/09681—Mesh conductors, e.g. as a ground plane
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/072—Connecting or disconnecting of bump connectors
  • H10W72/07231—Techniques
  • H10W72/07236—Soldering or alloying
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
  • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

• This invention is in the field of cross - talk suppression in a hybrid assembly at microwave frequencies.
• MMIC Monolithic Integrated Circuits
• active devices such as field effect transistors and bipolar transistors
• passive elements such as capacitors, thin film / bulk resistors, and inductors integrated on a single semi-insulating substrate, such as Gallium Arsenide.
• Hybrid technology relates to methods used for interconnecting a plurality of separate semiconductor structures, such as MMICs, to a host substrate, in single, or multi-layer configurations.
• inter- connections between the semiconductor structures is sometimes along the surface of the host substrate. These interconnections are frequently made using metallized paths connected to bumps (soft solder, or hard plated bumps). These bumps, located on the surface of the substrate, engage conductive pads on the semiconductor structures thus forming conductive, interconnecting paths between the host substrate and the semiconductor structures.
• the bumps are used as a substitute in place of wire bonds for connections.
• the advantage of bumps over wire bonds include the elimination of wafer backside processing steps such as wafer thinning, via formation, and metal deposition.
• Another advantage to using surface bumps for interconnection purposes is the lower thermal resistance between the semiconductor structures and the host substrate.
• the lower thermal resistance of the bump connection is due to the relatively large surface area of contact between the host substrate and the semiconductor structures. Heat transfer is also facilitated by the large diameter and short length of the bump, as compared to a wire interconnect.
• both the bump and the wire are made of thermally conductive metal, the favorable aspect ratio of the bump and wider surface area present a lower thermal resistance as compared to a typically thin, long wire bond.
• the lower thermal path presented by the bump facilitates the conduction of heat away from the semiconductor structures, allowing higher power density for the semiconductor /substrate hybrid assembly, especially when using thermal bumps directly under heat sources. The higher power density allows higher performance for the hybrid.
• bumps for interconnect purposes are the elimination of parasitic effects such as capacitance, inductance and radio emissions present with wire bonds and vias.
• the thin, long wire bonds, and the vias traversing the thickness of the substrate can be considered as antennas for the emission of electromagnetic interference.
• the same wires and vias present capacitance to adjacent structures, as well as an inductance to the signals transmitted by the wires.
• bumps are their lower cost and higher reliability. Typically bump type connections can be efficiently completed using a single epoxy cure/solder reflow die-attach process. This presents fewer steps during manufacture as compared to wire bond techniques. With bump interconnect, there are no mechanical wire connections to shake loose, be intermittent or fail due to thermal cycling.
• bumps are advantageous as compared to wire inter-connections, their presence between a semiconductor structure and a host substrate presents unique electromagnetic resonance and emission packaging problems.
• a particular difficulty introduced by the semiconductor structure mounted on the host substrate is the potential formation of electromagnetic boundaries which support unwanted, parallel plate, waveguide like (surface modes) of energy propagation. Such unwanted modes can propagate near the surface of the host substrate causing degradation in semiconductor performance because of signal interference.
• the degradation in semiconductor performance are caused by unwanted signal transfer among semiconductor structure inputs and outputs, affecting gain and phase response, loss of isolation between adjacent paths in multiple path / multiple channel circuit applications, and circuit instability. These negative effects are due to the introduction of unwanted coupling or feedback paths.
• GaAs Gallium Arsenide
• a hybrid assembly comprising: a substrate having an upper surface; conductive paths on said upper surface for conducting high frequency signals along said upper surface of said substrate etched from a conductive layer initially deposited on the substrate; and first polygons made of a first electromagnetic band gap material on said upper surface, said first electromagnetic band gap material having slow wave characteristics in a first band, said first polygons forming a lattice for tessellating said upper surface, each of said first polygons having a first periphery at a first position; each of said first polygons separated along said first periphery from adjacent first polygons by a first interspace ; said first polygons separated by a first distance from said conductive paths; each of said first polygons connected to a first conductive via, said first conductive via traversing said substrate and connected to said conductive layer on said lower surface of said substrate.
• semiconductor structures are mounted over said first polygons.
• Said semiconductor structures have a plurality of electrical contacts with said conductive paths and are electrically separate from the EBG polygons.
• Second polygons are made of the same or of a second electromagnetic band gap material, and positioned over said insulating layer, tessellating the same area as the first polygons.
• the second polygons also form a lattice for tessellating said upper surface, just like the first polygons.
• Each of said second polygons has a second periphery at a second position and each is separated along said second periphery from adjacent second polygons by a second interspace.
• Each of said second polygons, as well as each of the first polygons are connected to an individual, specific conductive via, said conductive via traversing said substrate and connected to said conductive layer on said lower surface of said substrate.
• the conductive layer is at ground potential.
• Semiconductor structures are mounted over said second polygons.
• the semiconductor structures have a plurality of electrical contacts with said conductive paths but are electrically insulated from said second polygons.
• the first and second polygons are hexagons, triangles, octagons, or any other regular polygon.
• the first and second polygons are centered at different positions.
• the position of the second polygons is separated from the position of the first polygons along the surface of the substrate by an amount greater than the first interspace.
• the first polygons and second polygons are equal in width, and have equal shape and periphery, the second polygons are separated from the first polygons by 1/2 of the width of one first polygon.
• the first and second polygons can be the same or different.
• the size of the first polygons, hence their periphery can be the same, larger or smaller than the second polygons.
• Fig 1 is a typical configuration of the prior art where a semiconductor structure is mounted on a substrate using bumps for inter connection means;
• Fig 2 is a typical configuration of the prior art where a redundant bump is used to minimize the undesired propagation of surface waves along an upper surface of a host substrate ;
• Fig 3 is an exemplary configuration of this invention showing EBG polygons over an upper surface of a substrate, said EBG polygons electrically separate from conductive paths to an MMIC;
• Fig 4 is a cross section of an exemplary configuration of a hybrid of the present invention having EBG polygons over the upper surface of a substrate ;
• Fig 5 shows a periodic lattice for tessellating the surface of a substrate using hexagons
• Fig 6 shows a periodic lattice for tessellating the surface of a substrate using a periodic structure made of octagons
• Fig 7 shows a periodic lattice for tessellating the surface of a substrate using a periodic structure made of triangles
• Fig 9 shows a vertical cross section of hybrid using two layers of EBG polygons shown in Fig 8.
• the present invention describes an apparatus and method for improved cross talk suppression in a hybrid assembly by incorporating one or more layers made of electromagnetic band-gap (EBG) polygons on a hybrid substrate such as, for example, alumina, LTCC (low temperature co-fired ceramic) as well as HTCC (high temperature co-fired ceramic).
• ESG electromagnetic band-gap
• the EBG polygons reduce the cross talk induced by undesired surface / waveguide modes at high operating frequencies (10 to 20 Ghz) between input/output/power and ground pins on the operation of the hybrid.
• Fig 1 is a typical configuration of a hybrid of the prior art where a semiconductor structure 103 is mounted on the upper surface 111 of a host substrate 101 using bumps 105, 107 and 109 for inter-connection means.
• Substrate 101 has an upper metalization layer deposited on upper surface 111 of substrate 101.
• Conductive paths 113 and 115 are etched from a metalization layer, and interconnect bumps 105,107 and 109 to their respective signal, ground or power sources.
• bumps 105, 107, and 109 form a continuous electrical path with pads (not shown) located on semiconductor structure 103, thus proving a path for conductively transferring the signal, ground or power from bumps 105, 107 and 109 to specific locations within semiconductor structure 103.
• An example of a semiconductor structure is a Monolithic Integrated Circuit, MMIC.
• the MMIC typically may comprise semiconductors, capacitors and resistors, as is well known in the art.
• Fig 2 shows a means of the prior art used to minimize undesired surface / waveguide mode propagation of signals from bump 105 to bump 107.
• bump 202 has been introduced between bump 105 and 107 to avoid or minimize undesired propagation of electromagnetic energy via surface / waveguide modes from bump 105 to bump 107.
• Bump 202 is grounded, and effectively reduces the space between bump 107 and bump 105, thereby attenuating surface / waveguide mode energy that may reach bump 105 from bump 107.
• the introduction of bump 202 while minimizing unwanted electromagnetic energy transfer from bump 105 to bump 107, forces an increase in the surface area of substrate 101 as well as the physical dimensions of semiconductor structure 103.
• semiconductor structure 103 is Gallium Arsenide 25 mil thick
• substrate 101 is Alumina, 50 mil thick.
• Fig 3 shows an improvement over Fig 2 in accordance with this invention.
• EBG electromagnetic band-gap
• PBG photonic band- gap
• lattice structure made of hexagons (regular polygons) exhibiting stopband and slow wave characteristics tessellates upper surface 111 of substrate 101 between signal bumps such as 105, 107 and 109.
• the hexagons are electrically separate from signal bumps such as, for example, 105, 107 and 109.
• This invention uses EBG lattice structures to minimize the propagation of electromagnetic energy using surface / waveguide modes in a specific frequency band of operation.
• EBG lattice made up of hexagonal elements, such as 301, tessellates the upper surface of substrate 101.
• a plurality of hexagonal elements 301 form single layer EBG lattice structure 303, generally printed on substrate 101.
• Undesired signals traveling from bump 107 towards bump 105 now encounter the effects of the EBG lattice 303 and are attenuated.
• the thickness of lattice structure 303, shown as t is, for example, in the order of 1 to 3 mils, depending on the type of ink used to print the lattice structure 303 onto substrate 101, the frequency band to be attenuated, physical dimensions of the semiconductor structure 103.
• Each periodic element, or polygon of EBG layer 303, such as polygon 301 and polygon 305, is connected to ground plane 307 using a via.
• via 309 connects polygon 311, part of EBG layer 303 to ground plane 307.
• Two-dimensional (2D) and three-dimensional, multilayer (3D) EBG structures are applied on a single layer and/or multi-layer substrate technology.
• Uniplanar 2D EBG structures use one layer of metalization, whereas 3D EBG structures use multiple layers of metalization and substrate layers.
• EBG concepts presented herein are applicable to LTCC (low temperature co-fired ceramic) as well as HTCC (high temperature co-fired ceramic) technologies.
• FIG. 3 A side view of the single layer EBG structure shown in Fig 3 is further detailed in Fig 4.
• EBG layer 303 is printed on upper surface 111 of substrate 101.
• a typical poligon 301 of EBG layer 303 is shown between bumps 414 and 408.
• Via 418 connects polygon 301 to ground plane 307.
• Via 416 is another example of interconnecting ground plane 307 to a hexagonal EBG polygon within EBG layer 303.
• Bump 408 is metallic, typically conducts signals, power or ground.
• D is a distance between the EBG layer element 301 and conductive bump 408. This distance D insures no direct electrical contact exists between element 301 and bump 408.
• Bump 410 and bump 412 interconnect with MMIC 406 located above substrate 101 and upper surface 111.
• EBG layer 303 is deposited between bump 410 and 412 leaving a gap to preclude electrical contact.
• Various periodic EBG structures are used with flip chip MMIC on substrate configurations.
• a multiple-layer, hexagon lattice (with vias) EBG configuration was found effective to suppress unwanted surface / waveguide electromagnetic propagation.
• This EBG structure is compatible with typical substrates and substrate fabrication techniques.
• a lattice of hexagonal building blocks tessellates the surface as shown in Fig 3.
• Hexagonal building block 103 is one of many hexagonal elements, part of the lattice that tessellates the surface of substrate 101.
• Numerous other periodic EBG arrangements show equivalent performance benefits.
• the surface of the substrate can be tessellated with a periodic lattice triangles as shown in Fig 7, or a combination of polygons.
• a single layer periodic hexagon EBG lattice is used to tessellate an LTCC and/or Alumina substrate.
• Optimization of key parameters for single and multiple EBG layer hybrids includes hexagon physical dimensions, the spacing between adjacent hexagon unit cells on the same layer, and the overlap dimension between hexagon unit cells on different layers.
• the chip-on-board configuration provides practical restrictions on the physical dimensions of the periodic EBG structure shown in Fig 3, 4 and 5. Fabrication and die attached assembly limitations establishes restriction on the minimum physical dimensions of the hexagon geometry and spacing between hexagon unit cells.
• the flip chip CLC MMIC top boundary condition places a restriction on the maximum physical dimensions of an effective periodic lattice of hexagon cells since the efficiency of attenuating undesired energy is dependent on the quantity of hexagonal cells. Actual physical dimensions are computed from the operating frequency desired keeping in mind that the surfaces of the polygons can be viewed capacitively as a C.
• the vias present an inductance L at the frequencies of interest.
• the EBG materials also contribute to these factors. Therefore, the physical structure will be proportional to ⁇ c.
• Fig 4 Shown in Fig 4 are flip chips 404 and 406 (typically GaAs CLC MMIC) mounted on a 25 mil, Alumina substrate 101. Nias 416 and 418 connected to the metalized layer 307 (forming the ground plane) are used to connect hexagonal EBG polygons from EBG layer 303.
• Phase shifters, filters, and low loss matching circuits for various amplifier applications can be realized with the insertion of the EBG boundary on the substrate.
• Fig 5 further details an EBG lattice formed from polygons, such as hexagonal EBG elements 301, 501 and 503.
• Element 301 is separated by a distance D from bump 408.
• D is 2 mils, while / is about 1 mil.
• Each EBG hexagon, such as 501 and 503, are connected to the ground plane using vias.
• element 501 has via 505 centered with respect to the six sides of the polygon, and is made of a conductive material connecting the polygon to a ground plane, such as ground plane 307 (not shown in fig 5) .
• Fig 6 shows another example of polygons used in a lattice to tessellate the upper surface 111 of substrate 101 in either one layer, or two layer configurations.
• EBG Octagonal elements 602, 604 and 606 are separated by a distance DO from bump 408.
• EBG Octagonal elements 602, 604, 612 and 614 encircle via 608.
• Each side of the regular octagon is of size SO.
• octagons 604, 606, 614 and 616 encircle via 610.
• An interspace IO is provided between adjacent octagonal EBG elements.
• Each octagonal EBG element 602, 604, 606, 614 and 616 is individually connected to the ground plane using vias.
• Interspace IO is chosen to conform to the operating frequency of the hybrid and is typically proportional to the ⁇ G quantity presented by the geometry of the EBG/via structure.
• the periphery of polygons forming the second layer is displaced from those of the first layer, as shown with octagons 618, 620.
• Fig 7 shows yet the application of yet another regular polygon applicable to the present invention using EBG triangular elements 701, 703, and 705.
• the triangular elements are arranged to be spaced DTI from bump 408 and DT2 from bump 406. DTI may be equal to DT2.
• Interspace IT separates each triangular element of size ST.
• the center of each triangle forming a row of triangular elements is displaced with respect to the next so that no direct, straight line path exists between 406 and 408.
• element 703 is displaced along the axis connecting bump 408 and bump 406 with respect to elements 701 and 705 by an amount approximately 1/2ST.
• Each EBG element has a central via interconnection to ground.
• the EBG triangles in the first layer are shifted with respect to the triangles of the second layer by an amount sufficient to allow passage of vias in the space IT without touching the EBG triangles of an adjacent layer.
• a first EBG layer comprises sample hexagonal elements 804, 808, 810, 814 and 820, each having side size S.
• the centers of these hexagonal elements are laid out on a rectangular pattern - 2 by 2D1. The pattern is duplicated until the area to be tessellated is covered, for example the top of the substrate, as shown in fig 3.
• a second EBG layer comprising sample hexagonal elements 802, 806, 812 and 816 are below the first EBG layer, are typically of the same EBG material, and are also laid out on a rectangular pattern of the same D2 by 2D1 dimension.
• This second layer is separated by an insulator from the first layer and shifted by an amount D ⁇ from the first along the surface of the substrate, thereby allowing vias centered within hexagonal element, such , for example vias 822, 824, 826, 828 and 830 to traverse vertically the substrate without touching any of the EBG elements in adjacent EBG layers.
• the insulator is alumina, LTCC (low temperature co-fired ceramic) or HTCC (high temperature co-fired ceramic), from 1 to 4 mils thick.
• EBG layer eliminates, or greatly reduces the propagation of electromagnetic energy using undesired surface modes that may exist during the operation of the hybrid.
• EBG periodic elements polygons
• FIG. 8 The side view of the structure shown in Fig 8 is further detailed in Fig 9.
• Interspace I is shown separating upper layer hexagonal elements 814 and 820, part of layer 1, 901.
• Hexagonal element 814 is connected to ground plane 307 using via 828.
• Ground plane 307 is formed from a conductive layer positioned on the underside of substrate 101.
• Hexagonal element 816 is part of the lower layer, layer 2, 903, and is also connected to ground plane 307 using via 830, traversing substrate 101.
• Layer 2 is in contact with upper surface 111 of substrate 101.
• An insulating layer 905 separates layer 2, 903 from layer 1, 901.
• the insulating layer 905 is also shown between hexagonal element 814 and hexagonal element 816.
• the insulating layer, as described for Fig 8, is made of alumina, LTCC (low temperature co-fired ceramic) or HTCC (high temperature co-fired ceramic).
• the method for manufacturing the hybrid assembly of this invention comprises the steps of: a) forming conductive paths, connected for example to bumps 406 and 408, for conducting high frequency signals along an upper surface 111 of substrate 101; b) forming first polygons, the first polygons made from a first electromagnetic band gap material on said upper surface 111. This forms the first EBG layer 303.
• the first electromagnetic band gap layer 303 has slow wave characteristics in a first band.
• the first polygons form a lattice for tessellating said upper surface 111.
• Each of the first polygons has a periphery, each of the first polygons is separated along the periphery from adjacent polygons by an interspace I.
• the polygons are positioned so that they are separated by a distance D from conductive paths, for example, bumps 406 and 408.
• the second polygons are made of a second electromagnetic band gap layer having slow wave characteristics in a second band. Said second polygons forming a lattice for tessellating said upper surface.
• Each of said second polygons has a second periphery at a second position; each of said second polygons separated along said second periphery from adjacent second polygons by a second interspace ; said second electromagnetic band gap layer separated by a second distance from said conductive paths each of said second polygons connected to a second conductive via, said second conductive via traversing said substrate and connected said conductive layer on said lower surface of said substrate; d) mounting semiconductor structures, such as 404 and 406 over said second polygons, said semiconductor structures having a plurality of electrical contacts with said conductive paths, said conductive paths, such as 414, 408, 410 and 412.
• the polygons are, for example, hexagons as in Fig 5, octagons as in Fig 6, or triangles as in fig 7, in one or more layered configurations.

Landscapes

• Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• Optics & Photonics (AREA)
• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Semiconductor Integrated Circuits (AREA)
• Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Wire Bonding (AREA)
• Structure Of Printed Boards (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

Family

ID=34912277

Family Applications (1)

Country Status (5)

Cited By (1)

Families Citing this family (60)

Family Cites Families (13)

• 2004
  • 2004-03-05 US US10/794,491 patent/US6967282B2/en not_active Expired - Lifetime
  • 2004-03-11 US US10/800,173 patent/US6949707B1/en not_active Expired - Lifetime
• 2005
  • 2005-03-04 WO PCT/US2005/007530 patent/WO2005088708A2/en not_active Ceased
  • 2005-03-04 EP EP05745171.8A patent/EP1721497B1/en not_active Ceased
  • 2005-03-04 JP JP2007502111A patent/JP5784265B2/ja not_active Expired - Fee Related
• 2006
  • 2006-10-05 NO NO20064532A patent/NO337499B1/no not_active IP Right Cessation

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events