WO2005078935A1 - Boucle a verrouillage de phase numerique avec une reponse transitoire rapide - Google Patents

Boucle a verrouillage de phase numerique avec une reponse transitoire rapide Download PDF

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Publication number
WO2005078935A1
WO2005078935A1 PCT/DE2005/000031 DE2005000031W WO2005078935A1 WO 2005078935 A1 WO2005078935 A1 WO 2005078935A1 DE 2005000031 W DE2005000031 W DE 2005000031W WO 2005078935 A1 WO2005078935 A1 WO 2005078935A1
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WO
WIPO (PCT)
Prior art keywords
digital
frequency
locked loop
signal
phase
Prior art date
Application number
PCT/DE2005/000031
Other languages
German (de)
English (en)
Inventor
Nicola Da Dalt
Lajos Gazsi
Original Assignee
Infineon Technologies Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Publication of WO2005078935A1 publication Critical patent/WO2005078935A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50—All digital phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop

Definitions

  • the invention relates to a digital phase locked loop for generating an output frequency with the aid of a digitally controlled oscillator.
  • PLL phase-locked loop
  • the voltage signal is fed to a charge pump (CP: Charge Pump), which converts the voltage signal into a corresponding current signal.
  • CP Charge Pump
  • This current signal is fed to a loop filter (LF: Loop Filter), the output signal of which drives the voltage-controlled oscillator.
  • LF Loop Filter
  • a frequency divider with a divider factor N can be arranged in the feedback path between the voltage-controlled oscillator and the phase / frequency detector.
  • the output frequency of the voltage-controlled oscillator corresponds to N times the reference frequency.
  • CMOS complementary metal-oxide-semiconductor
  • DCO Digital Controlled Oscillator
  • Binary or ternary quantizing phase detectors are often used in high-speed transmitter / receiver circuits with integrated PLL. Such transmitter / receiver circuits (transceivers) are used in a variety of applications, such as optical communication connections, chip-to-chip connections, etc.
  • the clock is not supplied with the data in such receiver / transmitter circuits.
  • the clock signal must be obtained from the data signal for synchronous operation.
  • the data signal must be readjusted in time in order to remove the jitter accumulated during the transmission.
  • Modern clock and data recovery circuits (CDR: Clock and Data Recovery) use PLL techniques, which work either in linear or in non-linear operation.
  • CDR Clock and Data Recovery
  • the binary or ternary quantizing phase detectors is that they show very simple signal processing of digital values with an inherent sampling phase adjustment, whereby the operation of the PLL can be carried out at a very high speed, which can only be achieved by the Working speed of a flip-flop is limited.
  • Other advantages of a (non-linear) PLL with a binary phase detector are the excellent jitter tolerance, jitter Transmission and jitter generation characteristics. Another advantage is that the jitter in PLL with binary phase detectors only grows with the root of the input jitter, whereas linear jitter growth is observed with linear PLL.
  • PLL with binary phase detectors are also known as Bang-Bang PLL and for example in the article “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems", RC Walker, http: //www.omnisterra. com / walker / pubs .html.
  • a difficulty with such digital PLLs is that the digitally controlled oscillator is still an analog circuit and therefore shows the typical problems of such a circuit. This is explained in more detail below with reference to FIG. 1.
  • 1 shows the output frequency of a DCO as a function of the digital input control word. The output frequency of the DCO is through the equation
  • F0 denotes the freewheeling frequency
  • KF the gain factor for the frequency tuning range
  • DCO_input the digital input control word.
  • the freewheeling frequency F0 is the output frequency of the DCO when the digital input control signal DCO_input is zero.
  • the maximum output frequency f max at the output of the DCO is reached when the largest digital control word (1-LSB) is entered as the DCO_input value, LSB designating the least significant bit.
  • the minimum output frequency F min at the output of the DCO results when the smallest digital control word -1 is entered.
  • the desired target frequency at the output of the DCO results in accordance with
  • Fgoal N * F ref , (2)
  • Fg ⁇ a ⁇ indicates the target frequency
  • N denotes the factor of the frequency multiplication (which is realized in a known manner as a divider factor in the feedback branch of the PLL)
  • Fref denotes the value of the reference frequency.
  • the digital input value k generates the desired output frequency
  • the values KF (gain factor) and F0 (freewheeling frequency) of a DCO are typically unknown because they vary due to different manufacturing processes and different operating parameters such as voltage, power, temperature. As a result, the value k for setting the desired target frequency F goa ⁇ is unknown. If the catch range of the PLL is sufficiently large for practical use and if there is a sufficiently long acquisition time (settling time), the fact that k is unknown is not a problem. In many practical applications, however, short acquisition times are required over a wide fishing range.
  • a first way to avoid the problems mentioned is to measure the freewheeling frequency F0 and the amplification factor KF of a DCO after its manufacture.
  • a suitable digital start value can be calculated in the vicinity of the value k, which is safely within the catchment range of the PLL and guarantees a rapid settling (ie a short acquisition time).
  • a disadvantage of this procedure is the considerable additional effort that is required by the measurement.
  • fuses must be provided in the circuit, which increase the costs of the circuit.
  • this procedure does not provide a solution to the changes in the oscillator properties caused by aging or temperature effects.
  • the phase detector is designed in the form of a D flip-flop 1, to which an input signal F r ⁇ f is fed at its D input.
  • the Q output of the flip-flop 1 is connected to the input 3 of the digitally controlled oscillator (DCO) 4 via two parallel paths which are brought together in an adder 2.
  • the output of the digitally controlled oscillator 4 is fed back to the clock input of the flip-flop 1.
  • a multiplier 5 is provided in the first path and multiplies the output signal of the flip-flop 1 by a fixed value ⁇ .
  • This path is also referred to as a proportional path or bang-bang path.
  • the PLL has a second path in which an integrator 6 is arranged.
  • the integrator 6 averages the signal ⁇ obtained from the flip-flop 1.
  • PLLs that only have the proportional path are also referred to as first-order loops.
  • the proportional path (alone) guarantees excellent jitter generation and jitter tolerance properties. As stated in the RC Walker document, these properties are determined by one parameter only
  • ß is also referred to as the bang-bang gain factor of the proportional path.
  • the integral path 6 In order to enlarge the capture range of the PLL, the integral path 6 must be used in addition to the proportional path 5.
  • the integrator 6 not only follows the phase differences but also the frequency error between the reference frequency F ref and the output signal of the DCO.
  • the second, integral path thus takes over the task of controlling the PLL in the transient process to the target frequency F goa ⁇ (which corresponds to the reference frequency F ref in FIG. 2). Only when the frequency error reaches the capture range of the proportional path 5 (ie when the frequency error is less than ⁇ fbb), does the proportional path 5 take over the remaining transient process of the loop.
  • parameters ⁇ and ß are not possible.
  • the bandwidth of the integral path 6 must be much smaller than the bandwidth of the proportional path for reasons of stability.
  • the bang-bang gain ⁇ must also be small in order to keep the jitter generation low. These two requirements make it necessary to choose the factor ⁇ very small. This is has the effect that long settling times have to be accepted when the PLL is switched on. The length of the settling time that occurs still depends on the analog parameters of the DCO (gain factor KF and freewheeling frequency FO), which, as already explained, depend to a large extent on the manufacturing and operating conditions of the PLL.
  • the invention has for its object to provide a digital phase locked loop with a binary or ternary phase detector, which has a high degree of digitization and shows a fast transient response over a wide capture range.
  • the digital control loop has a digitally controlled oscillator for generating an output frequency.
  • the control loop furthermore comprises a digital binary or ternary phase detector for detecting the phase difference between an input frequency and a feedback frequency which is dependent on the output frequency of the oscillator.
  • a transmission circuit is arranged between the output of the binary or ternary phase detector and the input of the digitally controlled oscillator, which converts the binary or ternary signal output by the phase detector into a digital control signal for controlling the digitally controlled oscillator.
  • the digital control circuit comprises a (further) feedback loop with a digital counting means, which determines the difference between the number of signal edges occurring in the feedback frequency and signal edges occurring in the input frequency, this difference influencing the digital control signal.
  • the differential edge count carried out in the feedback loop forms a signal which controls the digital control signal in the direction towards the steady state (ie towards the a priori unknown value k).
  • the feedback loop according to the invention thus guarantees an expanded frequency and phase acquisition range and ensures rapid settling in spite of process or temperature variations of the freewheeling frequency FO and the gain factor KF of the digitally controlled oscillator.
  • the feedback loop according to the invention is constructed completely digitally, ie, for example, no (analog) capacities are required in this loop, as is the case with conventional charge pump circuits.
  • the transmission circuit preferably comprises a first proportional branch, in which the binary or ternary signal is multiplied by a factor, and a second integral path, in which the binary or ternary signal is accumulated.
  • the transmission circuit is implemented as a second-order loop, as is basically known from the R.C. Walker is already known.
  • a particularly advantageous embodiment of the invention is characterized in that the binary or ternary signal is accumulated in the integral path by means of a digital integrator.
  • the integral path also has no analog elements, in particular capacities.
  • Another possibility is to keep this difference constant after a predetermined period of time. This can be done, for example, by means of a counting means which, after a predetermined number of counting cycles, freezes its counting output (at which the difference is available). This measure can be particularly advantageous if the input frequency is very noisy and the time between rising and falling edges is not sufficient to keep the feedback loop according to the invention according to the previously described method (use of different edge types for the phase detector and counting means) constant his.
  • the feedback loop preferably comprises a scaling unit for scaling the difference. In this way, the influence of the feedback loop on the overall behavior of the
  • PLL can be adjusted appropriately.
  • the feedback loop has a digital filter for filtering the difference. This creates a further degree of freedom to improve the transient response of the PLL.
  • Fig. 1 is a graph showing the output frequency of a digitally controlled oscillator over the digital input signal
  • FIG. 2 shows a circuit diagram of a known second order PLL with a binary phase detector
  • FIG. 3 shows the basic architecture of a digital PLL according to the invention using a digitally controlled oscillator
  • FIG. 4 shows a circuit diagram of a first embodiment of a PLL according to the invention with a binary phase detector
  • FIG. 5 shows a circuit diagram of a second embodiment of a PLL according to the invention with a binary phase detector
  • FIG. 6 shows two diagrams in which the output frequency of the phase locked loop shown in FIG. 5 is shown without the linear feedback loop according to the invention over time for a deviation of ⁇ 10 MHz between the target frequency and the starting frequencies;
  • FIG. 7 shows two graphs in which the output frequency of the phase locked loop shown in FIG. 5 without the linear feedback loop according to the invention is shown over time for a deviation of ⁇ 20 MHz between the target frequency and the starting frequencies;
  • Fig. 8 two graphs in which the output frequency of the phase locked loop shown in Fig. 5 without the linear feedback loop according to the invention over the Time for a deviation of ⁇ 30 MHz between the target frequency and the starting frequencies is shown;
  • FIG. 9 shows two graphs in which the output frequency of the phase locked loop shown in FIG. 5 without the linear feedback loop according to the invention is shown over time for a deviation of ⁇ 100 MHz between the target frequency and the starting frequencies;
  • FIGS. 4 and 5 are graphs in which the output frequency of the phase locked loops shown in FIGS. 4 and 5 with the linear feedback loop according to the invention over time for deviations of ⁇ 300 MHz, ⁇ 200 MHz and ⁇ 100 MHz between the target frequency and the start frequencies is shown;
  • FIG. 11 shows a diagram in which the output values of the integrating path of the second-order PLL and the output values of the up / down counter are shown over time in the linear feedback loop according to the invention.
  • the digital PLL comprises a digital processor 100, which is connected via a digital control bus 101 to the input 3 of a digitally controlled oscillator (DCO) 4.
  • DCO digitally controlled oscillator
  • An analog frequency signal is output at the output 7 of the digitally controlled oscillator 4. This is fed via an electrical connection 8 (possibly after frequency division) to a first input 9 of the digital processor 100.
  • An input signal is applied to a second input 10 of the digital processor 100 with a reference frequency and a refer- ence clock f re f on.
  • the processor 100 or possibly also the entire circuit shown in FIG. 3 can be implemented in a fully integrated form.
  • a first exemplary embodiment of the present invention is based on a phase locked loop with a second-order bang-bang loop, as shown in the box 11 shown in broken lines.
  • the same components as in the previous figures are again identified by the same reference numerals.
  • the phase-locked loop shown in box 11 differs from the phase-locked loop shown in FIG. 2 in that the integrator 6 'is designed as a digital integrator consisting of an accumulator (adder 12, delay element 13) and a multiplier 14.
  • the multiplier 14 multiplies the output of the accumulator 12, 13 by a factor ⁇ .
  • the signal values of the proportional and the integral path are added.
  • a quantizer 15 which, depending on the incoming digital signal values, generates suitable digital control signal values for the digitally controlled oscillator 4 which are adapted to the input word width of the digital oscillator 4.
  • a divider circuit 17 is provided between the output of the digitally controlled oscillator 4 and the clock input of the flip-flop 1.
  • the divider circuit 17 carries out a frequency division by the divider factor N.
  • ⁇ ⁇ (t n ) denotes the phase of the returned frequency signal output by divider circuit 17 and ⁇ d (t n ) the phase of the input signal with frequency Fref
  • the output signal of the flip-flop 1 thus represents a binary approximation of the phase difference between the input signal F re f and the feedback frequency signal.
  • ⁇ n can also assume the value 0, specifically when it is not possible to determine a phase error between the input signal and the returned frequency signal.
  • the second-order bang-bang PLL (box 11) is supplemented according to the invention by a feedback loop, which is shown in the dashed box 20.
  • the feedback loop comprises an up / down counter 21, a multiplier 22 and an (optional) digital filter 23.
  • the up / down counter 21 is at its up
  • Count input the feedback frequency signal supplied by the divider circuit 17.
  • the input signal of the frequency F r e f is present at the down counter input of the up / down counter 21.
  • the up / down counter 21 independently counts the edges of the feedback frequency signal and the edges of the input signal and thereby forms the difference between the respective number of edge events. This difference is weighted in the digital multiplier 22 with the constant gain factor Slin and filtered in the digital filter 23.
  • the filtered digital signal is fed to the adder 2 at a third adder input and causes the digitally controlled oscillator 4 Control signal supplied in the direction of the (unknown and depending on the parameters KF and FO different) target value k (which causes the output frequency Fg ⁇ a ⁇ predetermined by N and F re f) to be controlled.
  • phase detector flip-flop 1
  • registers in the loop filter 23 respond to a rising edge of the feedback frequency signal forming the clock
  • the up / down counter 21 updates the difference value at its output at times of falling edges of its incoming signals.
  • FIG. 5 shows a second exemplary embodiment of the present invention, which differs from the first exemplary embodiment shown in FIG. 4 only by an expansion of the linear feedback loop 20 by a warm start functionality.
  • the extended linear feedback loop 20 additionally has a multiplexer 24, which makes it possible to feed either the signal output by the digital filter 23 or a signal value held in a register 25 to the adder 2.
  • the S 'teuerein- transition the multiplexer 24 is designated WS (warm start).
  • WS warm start
  • the constant signal value output by the digital filter 23 is read into the register 25 and stored in a non-volatile memory 26 during the previous shutdown process.
  • this stored signal value is uploaded into register 25 and (if the warm start functionality is activated via WS) is sent to adder 2 via multiplexer 24. This can significantly reduce the acquisition time when restarting.
  • Q denotes the word width of the control signal for the digitally controlled oscillator 4, which is realized by the quantizer 15.
  • the following figures show simulation results of the frequency / phase acquisition time with different start values for the frequency. An implementation error with a hysteresis of 2 ps and a comparison jitter of 5.4 ps (RMS value) was assumed for the D flip-flop 1.
  • FIG. 6 shows the situation at a start frequency of 4.81 GHz (upper illustration) and 4.79 GHz (lower illustration) in the circuit according to FIGS. 4 and 5 without a linear feedback loop 20, 20 '. In this case, an acceptable acquisition time of 15 ⁇ s is observed.
  • FIGS. 7 and 8 show corresponding representations for start frequencies of 4.82 GHz (upper part of FIG. 7) and 4.78 GHz (lower part of FIG. 7) and 4.83 GHz (upper one
  • FIGS. 6 to 9 make it clear that such a tuning range cannot be achieved with conventional solutions (second-order Bang-Bang PLL).
  • the output values (determined by simulation) of the integral path 12, 13, 14 (curve K 1) and the up / down counter 21 (curve K 2) are shown in FIG. 11. It becomes clear that the output value of the up / down counter 21 is stable after 5 ⁇ s. Subsequently, the value output by the up / down counter 21 remains constant ("quiet"), while the integral path 12, 13, 14 takes on the task of reducing the frequency deviation within 20 ⁇ s.
  • the invention makes it possible to implement a digital phase-locked loop with low production costs, a wide capture range and a short acquisition time, which is ideally suited for production in CMOS technologies with small structural widths.

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Abstract

L'invention concerne un circuit de réglage numérique pourvu d'un oscillateur à commande numérique (4) destiné à la production d'une fréquence de sortie. Ce circuit de réglage comprend un détecteur de phase (1) binaire ou tertiaire numérique permettant de détecter la différence de phase entre une fréquence d'entrée et une fréquence renvoyée dépendant de la fréquence de sortie de l'oscillateur (4). L'oscillateur numérique (4) est commandé non seulement par le détecteur de phase (1) mais aussi par un compteur numérique (21) qui détermine la différence entre les flancs de signaux survenant dans la fréquence renvoyée et les flancs de signaux survenant dans la fréquence d'entrée.
PCT/DE2005/000031 2004-02-12 2005-01-12 Boucle a verrouillage de phase numerique avec une reponse transitoire rapide WO2005078935A1 (fr)

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Application Number Priority Date Filing Date Title
DE102004006996A DE102004006996B4 (de) 2004-02-12 2004-02-12 Digitaler Phasenregelkreis mit schnellem Einschwingverhalten
DE102004006996.4 2004-02-12

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Cited By (3)

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US7545222B2 (en) 2006-01-06 2009-06-09 Realtek Semiconductor Corp. Phase lock loop for rapid lock-in and method therefor
EP2136472A1 (fr) * 2008-06-17 2009-12-23 Nxp B.V. PLL à commande par tout ou rien à verrouillage rapide et faible gigue de phase en sortie
WO2018137548A1 (fr) * 2017-01-26 2018-08-02 华为技术有限公司 Dispositif et procédé de synchronisation d'horloge

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US8014487B2 (en) 2007-04-10 2011-09-06 Nxp B.V. High-frequency counter

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US5487093A (en) * 1994-05-26 1996-01-23 Texas Instruments Incorporated Autoranging digital analog phase locked loop
JPH09238072A (ja) * 1995-12-28 1997-09-09 Toshiba Corp ディジタルｐｌｌ回路
US5856762A (en) * 1996-07-22 1999-01-05 Siemens Aktiengesellschaft Phase-locked loop with course providing damping and natural frequency independence
WO2000043849A2 (fr) * 1999-01-21 2000-07-27 Infineon Technologies Ag Boucle a phase asservie electronique
US6388536B1 (en) * 1998-05-29 2002-05-14 Silicon Laboratories Inc. Method and apparatus for providing coarse and fine tuning control for synthesizing high-frequency signals for wireless communications

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JPH09238072A (ja) * 1995-12-28 1997-09-09 Toshiba Corp ディジタルｐｌｌ回路
US5856762A (en) * 1996-07-22 1999-01-05 Siemens Aktiengesellschaft Phase-locked loop with course providing damping and natural frequency independence
US6388536B1 (en) * 1998-05-29 2002-05-14 Silicon Laboratories Inc. Method and apparatus for providing coarse and fine tuning control for synthesizing high-frequency signals for wireless communications
WO2000043849A2 (fr) * 1999-01-21 2000-07-27 Infineon Technologies Ag Boucle a phase asservie electronique

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7545222B2 (en) 2006-01-06 2009-06-09 Realtek Semiconductor Corp. Phase lock loop for rapid lock-in and method therefor
EP2136472A1 (fr) * 2008-06-17 2009-12-23 Nxp B.V. PLL à commande par tout ou rien à verrouillage rapide et faible gigue de phase en sortie
WO2009153716A3 (fr) * 2008-06-17 2010-02-11 Nxp B.V. Boucle à phase asservie (pll) tout ou rien à verrouillage rapide avec gigue de sortie faible
US8203369B2 (en) 2008-06-17 2012-06-19 Nxp B.V. Fast-locking bang-bang PLL with low ouput jitter
WO2018137548A1 (fr) * 2017-01-26 2018-08-02 华为技术有限公司 Dispositif et procédé de synchronisation d'horloge

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