DE69700270T2 - Frequenzvervielfacher, bei dem das Multiplikationsverhältnis in der ersten Stufe grösser ist als in den nachfolgenden Stufen - Google Patents

Frequenzvervielfacher, bei dem das Multiplikationsverhältnis in der ersten Stufe grösser ist als in den nachfolgenden Stufen

Info

Publication number
DE69700270T2
DE69700270T2 DE69700270T DE69700270T DE69700270T2 DE 69700270 T2 DE69700270 T2 DE 69700270T2 DE 69700270 T DE69700270 T DE 69700270T DE 69700270 T DE69700270 T DE 69700270T DE 69700270 T2 DE69700270 T2 DE 69700270T2
Authority
DE
Germany
Prior art keywords
stage
frequency multiplier
subsequent stages
multiplication ratio
multiplication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69700270T
Other languages
English (en)
Other versions
DE69700270D1 (de
Inventor
Akihiko Yoshizawa
Shuichi Takada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69700270D1 publication Critical patent/DE69700270D1/de
Publication of DE69700270T2 publication Critical patent/DE69700270T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/0805Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K5/00Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006Changing the frequency
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/081Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
DE69700270T 1996-04-01 1997-04-01 Frequenzvervielfacher, bei dem das Multiplikationsverhältnis in der ersten Stufe grösser ist als in den nachfolgenden Stufen Expired - Lifetime DE69700270T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07885496A JP3323054B2 (ja) 1996-04-01 1996-04-01 周波数逓倍回路

Publications (2)

Publication Number Publication Date
DE69700270D1 DE69700270D1 (de) 1999-07-22
DE69700270T2 true DE69700270T2 (de) 1999-11-11

Family

ID=13673420

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69700270T Expired - Lifetime DE69700270T2 (de) 1996-04-01 1997-04-01 Frequenzvervielfacher, bei dem das Multiplikationsverhältnis in der ersten Stufe grösser ist als in den nachfolgenden Stufen

Country Status (6)

Country Link
US (1) US6005420A (de)
EP (1) EP0800276B1 (de)
JP (1) JP3323054B2 (de)
KR (1) KR100251263B1 (de)
DE (1) DE69700270T2 (de)
TW (1) TW370739B (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5982213A (en) * 1997-11-14 1999-11-09 Texas Instruments Incorporated Digital phase lock loop
JP2000165905A (ja) * 1998-11-27 2000-06-16 Mitsubishi Electric Corp クロック発生回路
US6415008B1 (en) * 1998-12-15 2002-07-02 BéCHADE ROLAND ALBERT Digital signal multiplier
JP3630291B2 (ja) * 1999-03-01 2005-03-16 シャープ株式会社 タイミング発生回路
CA2270516C (en) 1999-04-30 2009-11-17 Mosaid Technologies Incorporated Frequency-doubling delay locked loop
JP2000339692A (ja) * 1999-05-26 2000-12-08 Hitachi Ltd 情報の記録再生方法、及び情報の記録再生装置
JP4497708B2 (ja) * 2000-12-08 2010-07-07 三菱電機株式会社 半導体装置
JP3566686B2 (ja) * 2001-10-16 2004-09-15 Necマイクロシステム株式会社 逓倍クロック生成回路
JP3849485B2 (ja) * 2001-10-18 2006-11-22 セイコーエプソン株式会社 パルス処理回路および周波数逓倍回路
US6653876B2 (en) * 2002-04-23 2003-11-25 Broadcom Corporation Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
US6642756B1 (en) * 2002-07-25 2003-11-04 Sun Microsystems, Inc. Frequency multiplier design
KR100493046B1 (ko) * 2003-02-04 2005-06-07 삼성전자주식회사 클럭의 듀티 사이클을 조정할 수 있는 주파수 체배기 및체배방법
DE102004021224B4 (de) * 2004-04-30 2006-11-09 Advanced Micro Devices, Inc., Sunnyvale Frequenzmultiplikatorvorstufe für gebrochen-N-phasenarretierte Schleifen
WO2006030905A1 (ja) * 2004-09-17 2006-03-23 Nec Corporation クロック生成回路、及びクロック生成方法
US7158443B2 (en) * 2005-06-01 2007-01-02 Micron Technology, Inc. Delay-lock loop and method adapting itself to operate over a wide frequency range
JP4245658B2 (ja) * 2005-08-02 2009-03-25 アールエフ マジック インコーポレイテッド 多重周波数源システムにおける位相プリングを緩和するシステム及び方法
KR101088248B1 (ko) 2006-03-03 2011-11-30 노돈석 마이크로파 장비의 주파수 체배기
US7675332B1 (en) * 2007-01-31 2010-03-09 Altera Corporation Fractional delay-locked loops
US7495484B1 (en) * 2007-07-30 2009-02-24 General Instrument Corporation Programmable frequency multiplier
KR101032891B1 (ko) * 2008-08-29 2011-05-06 주식회사 하이닉스반도체 클럭생성회로
WO2010035309A1 (ja) * 2008-09-24 2010-04-01 株式会社アドバンテスト 遅延回路およびそれを用いたタイミング発生器および試験装置
US8487678B2 (en) 2011-01-18 2013-07-16 Qualcomm Incorporated Half cycle delay locked loop
US8988121B2 (en) * 2013-05-20 2015-03-24 Qualcomm Incoporated Method and apparatus for generating a reference signal for a fractional-N frequency synthesizer
US10404316B1 (en) * 2018-10-02 2019-09-03 Realtek Semiconductor Corp. Wide-band WLAN transceiver and method thereof
CN113839619B (zh) * 2021-08-15 2023-09-26 杭州电子科技大学 一种高功率、高效率的片上硅基双模太赫兹信号源结构

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2502872B1 (fr) 1981-03-27 1988-06-17 Laures Antoine Organe de recuperation de porteuse pour signal a modulations mdp2 ou mdp4
US4806879A (en) * 1987-05-01 1989-02-21 Ecrm Incorporated Method and apparatus for synchronizing to a pulse train packet signal
US4956797A (en) * 1988-07-14 1990-09-11 Siemens Transmission Systems, Inc. Frequency multiplier
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US5107264A (en) * 1990-09-26 1992-04-21 International Business Machines Corporation Digital frequency multiplication and data serialization circuits
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
JPH07202649A (ja) * 1993-12-27 1995-08-04 Toshiba Corp 逓倍回路
KR960009965B1 (ko) * 1994-04-14 1996-07-25 금성일렉트론 주식회사 주파수 배수 회로

Also Published As

Publication number Publication date
TW370739B (en) 1999-09-21
EP0800276A1 (de) 1997-10-08
US6005420A (en) 1999-12-21
JP3323054B2 (ja) 2002-09-09
KR970071989A (ko) 1997-11-07
JPH09270702A (ja) 1997-10-14
DE69700270D1 (de) 1999-07-22
KR100251263B1 (ko) 2000-04-15
EP0800276B1 (de) 1999-06-16

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