TW370739B - Multiplication circuit - Google Patents

Multiplication circuit

Info

Publication number
TW370739B
TW370739B TW086104099A TW86104099A TW370739B TW 370739 B TW370739 B TW 370739B TW 086104099 A TW086104099 A TW 086104099A TW 86104099 A TW86104099 A TW 86104099A TW 370739 B TW370739 B TW 370739B
Authority
TW
Taiwan
Prior art keywords
multiplication
circuit
voltage controlled
multiplication circuit
signals
Prior art date
Application number
TW086104099A
Other languages
English (en)
Inventor
Akihiko Yoshizawa
Shuichi Takada
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW370739B publication Critical patent/TW370739B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/68—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using pulse rate multipliers or dividers pulse rate multipliers or dividers per se
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Amplitude Modulation (AREA)
TW086104099A 1996-04-01 1997-03-31 Multiplication circuit TW370739B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP07885496A JP3323054B2 (ja) 1996-04-01 1996-04-01 周波数逓倍回路

Publications (1)

Publication Number Publication Date
TW370739B true TW370739B (en) 1999-09-21

Family

ID=13673420

Family Applications (1)

Application Number Title Priority Date Filing Date
TW086104099A TW370739B (en) 1996-04-01 1997-03-31 Multiplication circuit

Country Status (6)

Country Link
US (1) US6005420A (zh)
EP (1) EP0800276B1 (zh)
JP (1) JP3323054B2 (zh)
KR (1) KR100251263B1 (zh)
DE (1) DE69700270T2 (zh)
TW (1) TW370739B (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5982213A (en) * 1997-11-14 1999-11-09 Texas Instruments Incorporated Digital phase lock loop
JP2000165905A (ja) * 1998-11-27 2000-06-16 Mitsubishi Electric Corp クロック発生回路
US6415008B1 (en) * 1998-12-15 2002-07-02 BéCHADE ROLAND ALBERT Digital signal multiplier
JP3630291B2 (ja) * 1999-03-01 2005-03-16 シャープ株式会社 タイミング発生回路
CA2270516C (en) * 1999-04-30 2009-11-17 Mosaid Technologies Incorporated Frequency-doubling delay locked loop
JP2000339692A (ja) * 1999-05-26 2000-12-08 Hitachi Ltd 情報の記録再生方法、及び情報の記録再生装置
JP4497708B2 (ja) * 2000-12-08 2010-07-07 三菱電機株式会社 半導体装置
JP3566686B2 (ja) * 2001-10-16 2004-09-15 Ｎｅｃマイクロシステム株式会社 逓倍クロック生成回路
JP3849485B2 (ja) * 2001-10-18 2006-11-22 セイコーエプソン株式会社 パルス処理回路および周波数逓倍回路
US6653876B2 (en) * 2002-04-23 2003-11-25 Broadcom Corporation Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)
US6642756B1 (en) * 2002-07-25 2003-11-04 Sun Microsystems, Inc. Frequency multiplier design
KR100493046B1 (ko) * 2003-02-04 2005-06-07 삼성전자주식회사 클럭의 듀티 사이클을 조정할 수 있는 주파수 체배기 및체배방법
DE102004021224B4 (de) * 2004-04-30 2006-11-09 Advanced Micro Devices, Inc., Sunnyvale Frequenzmultiplikatorvorstufe für gebrochen-N-phasenarretierte Schleifen
US8242814B2 (en) * 2004-09-17 2012-08-14 Nec Corporation Clock generating circuit and clock generating method
US7158443B2 (en) * 2005-06-01 2007-01-02 Micron Technology, Inc. Delay-lock loop and method adapting itself to operate over a wide frequency range
JP4245658B2 (ja) * 2005-08-02 2009-03-25 アールエフ マジック インコーポレイテッド 多重周波数源システムにおける位相プリングを緩和するシステム及び方法
KR101088248B1 (ko) 2006-03-03 2011-11-30 노돈석 마이크로파 장비의 주파수 체배기
US7675332B1 (en) * 2007-01-31 2010-03-09 Altera Corporation Fractional delay-locked loops
US7495484B1 (en) * 2007-07-30 2009-02-24 General Instrument Corporation Programmable frequency multiplier
KR101032891B1 (ko) * 2008-08-29 2011-05-06 주식회사 하이닉스반도체 클럭생성회로
CN102165692A (zh) * 2008-09-24 2011-08-24 株式会社爱德万测试 延迟电路和使用其的定时发生器以及测试装置
US8487678B2 (en) 2011-01-18 2013-07-16 Qualcomm Incorporated Half cycle delay locked loop
US8988121B2 (en) * 2013-05-20 2015-03-24 Qualcomm Incoporated Method and apparatus for generating a reference signal for a fractional-N frequency synthesizer
US10404316B1 (en) * 2018-10-02 2019-09-03 Realtek Semiconductor Corp. Wide-band WLAN transceiver and method thereof
CN113839619B (zh) * 2021-08-15 2023-09-26 杭州电子科技大学 一种高功率、高效率的片上硅基双模太赫兹信号源结构

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2502872B1 (fr) 1981-03-27 1988-06-17 Laures Antoine Organe de recuperation de porteuse pour signal a modulations mdp2 ou mdp4
US4806879A (en) * 1987-05-01 1989-02-21 Ecrm Incorporated Method and apparatus for synchronizing to a pulse train packet signal
US4956797A (en) * 1988-07-14 1990-09-11 Siemens Transmission Systems, Inc. Frequency multiplier
FR2658015B1 (fr) * 1990-02-06 1994-07-29 Bull Sa Circuit verrouille en phase et multiplieur de frequence en resultant.
US5107264A (en) * 1990-09-26 1992-04-21 International Business Machines Corporation Digital frequency multiplication and data serialization circuits
US5463337A (en) * 1993-11-30 1995-10-31 At&T Corp. Delay locked loop based clock synthesizer using a dynamically adjustable number of delay elements therein
JPH07202649A (ja) * 1993-12-27 1995-08-04 Toshiba Corp 逓倍回路
KR960009965B1 (ko) * 1994-04-14 1996-07-25 금성일렉트론 주식회사 주파수 배수 회로

Also Published As

Publication number Publication date
EP0800276A1 (en) 1997-10-08
DE69700270T2 (de) 1999-11-11
JPH09270702A (ja) 1997-10-14
EP0800276B1 (en) 1999-06-16
US6005420A (en) 1999-12-21
JP3323054B2 (ja) 2002-09-09
KR100251263B1 (ko) 2000-04-15
DE69700270D1 (de) 1999-07-22
KR970071989A (ko) 1997-11-07

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees