Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
  • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P10/00—Bonding of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
  • H10P95/50—Alloying conductive materials with semiconductor bodies

Definitions

• the present invention relates generally to semiconductor technology, and more specifically to suiciding in semiconductor devices.
• CMOS Complementary Metal Oxide Semiconductor
• CMOS transistor generally consist of a silicon substrate having shallow trench oxide isolation regions cordoning off transistor areas.
• the transistor areas contain polysilicon gates on silicon oxide gates, or gate oxides, over the silicon substrate.
• the silicon substrate on both sides of the polysilicon gate is slightly doped to become conductive.
• the lightly doped regions of the silicon substrate are referred to as “shallow source/drain junctions," which are separated by a channel region beneath the polysilicon gate.
• a curved silicon oxide or silicon nitride spacer, referred to as a "sidewall spacer" on the sides of the polysilicon gate allows deposition of additional doping to form more heavily doped regions of the shallow source/drain junctions, which are called "deep source/drain junctions".
• the shallow and deep source/drain junctions are collectively referred to as "S/D junctions.”
• the sidewall spacer also may be formed as a two-layer spacer comprising a first insulating layer, such as an oxide layer covered by a second insulating layer, such as a nitride layer. The two insulating layers then are processed to form a two-layer spacer.
• a silicon oxide dielectric layer is deposited to cover the polysilicon gate, the curved spacer, and the silicon substrate.
• openings are etched in the silicon oxide dielectric layer to the polysilicon gate and the source/drain junctions. The openings are filled with metal to form electrical contacts.
• the contacts are connected to additional levels of wiring in additional levels of dielectric material to the outside of the dielectric material.
• an input signal to the gate contact to the polysilicon gate controls the flow of electric current from one source/drain contact tlirough one source/drain junction through the channel to the other source/drain junction and to the other source/drain contact.
• Transistors are fabricated by thermally growing a gate oxide layer on the silicon substrate of a semiconductor wafer and forming a polysilicon layer over the gate oxide layer. The oxide layer and polysilicon layer are patterned and etched to form the gate oxides and polysilicon gates, respectively.
• the gate oxides and polysilicon gates in turn are used as masks to form the shallow source/drain regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate.
• the ion implantation is followed by a high-temperature anneal above 700°C to activate the implanted impurity atoms to form the shallow source/drain junctions.
• a silicon nitride layer is deposited and etched to form sidewall spacers around the side surfaces of the gate oxides and polysilicon gates.
• the sidewall spacers, the gate oxides, and the polysilicon gates are used as masks for the conventional source/drain regions by ion implantation of boron or phosphorus impurity atoms into the surface of the silicon substrate into and through the shallow source/drain junctions.
• the ion implantation is again followed by a high-temperature anneal above 700°C to activate the implanted impurity atoms to form the S/D junctions.
• a silicon oxide dielectric layer is deposited over the transistors and contact openings are etched down to the source/drain junctions and to the polysilicon gates.
• the contact openings are then filled with a conductive metal and interconnected by formation of conductive wires in other interlayer dielectric (ILD) layers.
• ILD interlayer dielectric
• transistors have decreased in size, it has been found that the electrical resistance between the metal contacts and the silicon substrate or (lie polysilicon has increased to the level where it negatively impacts the performance of the transistors.
• a transition material is formed between the metal contacts and the silicon substrate or the polysilicon.
• the best transition materials have been found to be cobalt silicide (CoSi 2 ) and titanium silicide (TiSi 2 ) although other materials also can be used.
• the suicides are formed by first applying a thin layer of the cobalt or titanium on the silicon substrate above the source/drain junctions and the polysilicon gates.
• the semiconductor wafer is subjected to one or more annealing steps at temperatures above 800°C and this causes the cobalt or titanium to selectively react with the silicon and the polysilicon to form the metal silicide.
• the process is generally referred to as "suiciding.” Since the shallow trench oxide and the sidewall spacers will not react to form a silicide, the suicides are aligned over the source/drain junctions and the polysilicon gates so the process is also referred to as "self-aligned suiciding,” or “saliciding.”
• suiciding and saliciding have not succeeded in solving all the problems related to connecting metal contacts to silicon.
• the present invention provides a method of forming an integrated circuit.
• a gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric.
• Source/drain junctions are formed in the semiconductor substrate.
• a sidewall spacer is formed around the gate using a low power plasma enhanced chemical vapor deposition (PECVD) process.
• PECVD low power plasma enhanced chemical vapor deposition
• a silicide is formed on the source/drain junctions and on the gate, and an interlayer dielectric is deposited above the semiconductor substrate. Contacts then are formed in the interlayer dielectric to the silicide.
• the PECVD process preferably is performed within a low bias power range of about 100 watts to about 200 watts.
• FIG. 1 is a view of a transistor in an intermediate stage of fabrication in accordance with the present invention
• FIG. 2 is the structure of FIG. 1 with a liner layer deposited thereon
• FIG. 3 is the structure of FIG. 2 during ion implantation to form shallow source/drain junctions
• FIG. 4 is the structure of FIG. 3 after formation of a sidewall spacer
• FIG. 5 is the structure of FIG. 4 during ion implantation to form deep source/drain junctions
• FIG. 6 is the structure of FIG.5 during the formation of silicide
• FIG. 7 is the structure of FIG. 6 after deposition of a dielectric layer over the silicide, the sidewall spacer, and shallow trench isolation
• FIG. 8 is the structure of FIG. 7 after formation of metal contacts
• FIG. 9 is a simplified flow chart of the method of manufacturing the silicide in accordance with the present invention.
• FIG. 1 therein is shown a transistor 100 in an intermediate stage of fabrication in accordance with the present invention.
• a gate dielectric layer such as silicon oxide
• a conductive gate layer such as polysilicon
• the semiconductor substrate 102 has been further patterned, etched, and filled with a silicon oxide material to form a shallow trench isolation (STI) 108.
• STI shallow trench isolation
• FIG. 2 therein is shown the structure of FIG. 1 having a liner layer 202 deposited thereon.
• the liner layer 202 generally of silicon oxide, covers the semiconductor substrate 102, the gate dielectric 104, the gate 106, and the STI 108.
• the liner layer 202 can be of an etch stop material or an implant-protection material.
• FIG. 3 therein is shown the structure of FIG. 2 during an ion implantation 302 to form shallow source/drain junctions 304 and 306.
• the gate 106 and the gate dielectric 104 act as masks for the formation of shallow source/drain junctions 304 and 306 by the ion implantation 302 of boron (B) or phosphorus (P) impurity atoms into the surface of the semiconductor substrate 102.
• the ion implantation 302 is followed by a high-temperature anneal above 700°C to activate the implanted impurity atoms to form the shallow source/drain junctions 304 and 306.
• FIG. 4 therein is shown the structure of FIG. 3 after formation of a curved sidewall spacer 402.
• the sidewall spacer can be an insulating material selected from the group of an oxide, a nitride, and combinations thereof.
• the liner layer 202 which protects from implant damage, has been removed and a sidewall spacer layer of an insulating material, such as a nitride or an oxide, has been deposited and etched to form the curved shape of the sidewall spacer 402.
• the sidewall spacer layer used to form the sidewall spacer 402 typically is deposited using a plasma enhanced chemical vapor deposition (PECVD) process.
• PECVD processes use a number of radio frequency powers to direct ions of the material being deposited at the target surface, such as the semiconductor substratel02. It has been discovered that operating PECVD processes at low bias power reduces, or eliminates, the stress between the material used to form the sidewall spacer 402 and the semiconductor substrate 102.
• the PECVD process is performed at low bias power. It has been discovered that a PECVD process preferably within a low bias power range of about 100 watts to about 200 watts reduces the stress between the sidewall spacer 402 and the semiconductor substrate 102. Thus, performance of the transistor 100 is improved. Referring now to FIG. 5, therein is shown the structure of FIG. 4 during an ion implantation 502 to form deep source/drain junctions 504 and 506.
• the sidewall spacer 402, the gate 106, and the STI 108 act as masks for the formation of the deep source/drain junctions 504 and 506 by the ion implantation 502 of boron or phosphorus impurity atoms into the surface of the semiconductor substrate 102 and into and through the shallow source/drain junctions 304 and 306, respectively.
• the ion implantation 502 is again followed by a high-temperature anneal above 700°C to activate the implanted impurity atoms to form the source/drain junctions 504 and 506.
• FIG. 6 therein is shown a deposition process 602 used in the formation of silicide layers 604, 606, and 608 in accordance with the present invention.
• the silicide layers 604 and 608 are formed with the surface of the semiconductor substrate 102 over the deep source/drain junctions 504 and 506, respectively, and the silicide 606 is formed on the gate 106.
• the deposition process there are three ways in which to form a silicide. In one technique, the deposition process
• the 602 deposits a pure metal on exposed silicon areas (both single crystalline and polycrystalline silicon). Thereafter, the metal is reacted with the silicon to form what is known as a first phase, metal-rich silicide. The non-reacted metal is then removed, and the pre-existing first phase product is then reacted again with the underlying silicon to form a second phase, silicon-rich silicide.
• the deposition process 602 involves co-evaporation of both metal and silicon onto the exposed silicon. Both metal and silicon are vaporized by, for example, an electron beam. The vapor is then drawn onto the wafer and across the silicon.
• the deposition process 602 involves co-sputtering both metal and silicon onto the silicon surface.
• Co-sputtering entails physically dislodging metal and silicon materials from a composite target or separate targets, and then directing the composite material onto the wafer.
• Conventional salicidation processes have become problematic with modern semiconductor devices that have shallow source/drain junctions, e.g., junction depths on the order of 1000 Angstroms (A). In particular, during such salicidation processes, some of the existing source/drain regions are consumed.
• cobalt is used as the refractory metal, it consumes about twice its thickness of silicon in the process of being converted to a metal silicide, e.g., a 100 A layer of cobalt consumes about 103 A of silicon.
• Such consumption acts to reduce the dopant present in the source/drain junctions and may adversely impact the electrical performance characteristics of the source/drain junctions, and ultimately, degrades the performance of the integrated circuit.
• the refractory metal is titanium
• titanium silicide forms between metal contacts because the sidewall spacer becomes smaller with smaller integrated circuits thereby allowing a capacitive-coupled or fully conductive path between the polysilicon gate and the source/drain junctions, and similarly, degrades the performance of the integrated circuit.
• the present invention may be used with various refractory metal suicides, it has been found that nickel silicide has many desirable characteristics. However, in working with nickel silicide, it has been found to be difficult to form robust nickel silicide.
• an ultra-uniform nickel can form extremely robust nickel silicide.
• an ultra- uniform silicide means a layer of silicide where there are no variations in thickness greater than about 3% of the overall thickness.
• One example of forming ultra-uniform nickel ultra-uniform silicides 604, 606, and 608, is by depositing the nickel on the exposed silicon areas by a very low power vapor deposition process, where the very low power means a power level below 500 watts direct current and preferably between about 400 and 300 watts direct current.
• an extra slow rate of metal deposition is preferred, which is defined to be below 7.0 A per second and preferably between about 6.8 and 6.0 A per second. Still further, it is preferable that the silicide be deposited under these power levels and deposition rates to an ultra-thin thickness of not more than 50 A thickness in order to provide an ultra-uniform, ultra-thin silicide.
• the deposited silicide metal is then converted to a silicide by an annealing process, such as a high- temperature anneal around 700°C.
• the silicide 604, 606, 608 preferably is formed of a metal selected from the group consisting of cobalt, titanium, nickel, arsenic doped nickel, an alloy thereof, a compound thereof, and a combination thereof.
• the dielectric layer 107 are of dielectric materials such as silicon oxide (SiO x ), tetraethylorthosilicate (TEOS), borophosphosilicate (BPSG) glass, etc.
• dielectric constant dielectric materials such as fluorinated tetraethylorthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bis-benzocyclobutene (BCB), tetramethylorthosilicate (TMOS), octamethyleyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilil borxle (SOB), diaceloxyditerliarybutosiloxane (DADBS), trimethylsilil phosphate (SOP), etc. with dielectric constants below 3.9 to 2.5.
• FTEOS fluorinated tetraethylorthosilicate
• HSQ hydrogen silsesquioxane
• BCB bis-benzocyclobutene
• TMOS tetramethylorthosilicate
• OMCOS octamethyleyclotetrasiloxane
• HMDS hex
• Ultra-low dielectric constant dielectric materials having dielectric constants below 2.5 and which are available, include commercially available Teflon-AF, Teflon microemulsion, polimide nanofoams, silica aerogels, silica xerogels, and mesoporous silica.
• Stop layers and capping layers are of materials such as silicon nitride (Si x N x ) or silicon oxynitride (SiON).
• the metal contacts 802, 804, and 806 are respectively electrically connected to the silicide layers 604, 606, and 608, and respectively to the deep source/drain junction 504, the gate 106, and the deep source/drain junction 506.
• the metal contacts 802, 804, and 806 are of metals such as tantalum (Ta), titanium (Ti), tungsten (W), alloys thereof, and compounds thereof.
• the metal contacts 802, 804, and 806 are of metals such as copper (Cu), gold (Au), silver (Ag), alloys thereof, and compounds thereof with one or more of the above elements with diffusion barriers around them. Referring now to FIG. 9, therein is shown a simplified flow chart of a method 900 in accordance with the present invention.
• the method 900 includes: providing a semiconductor substrate in a step 902; forming a gate dielectric on the semiconductor substrate in a step 904; forming a gate on the gate dielectric in a step 906; forming source/drain junctions in the semiconductor substrate in a step 908; forming a sidewall spacer around the gate using a low power plasma enhanced chemical vapor deposition process in a step 910; forming a silicide on the source/drain junctions and on the gate in a step 912; depositing an interlayer dielectric above the semiconductor substrate in a step 912; and forming contacts in the interlayer dielectric to the silicide in a step 914.

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• Insulated Gate Type Field-Effect Transistor (AREA)
• Electrodes Of Semiconductors (AREA)
• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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• 2004
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