JP5265872B2 - 集積回路技術における低応力の側壁スペーサ - Google Patents

集積回路技術における低応力の側壁スペーサ Download PDF

Info

Publication number
JP5265872B2
JP5265872B2 JP2006549314A JP2006549314A JP5265872B2 JP 5265872 B2 JP5265872 B2 JP 5265872B2 JP 2006549314 A JP2006549314 A JP 2006549314A JP 2006549314 A JP2006549314 A JP 2006549314A JP 5265872 B2 JP5265872 B2 JP 5265872B2
Authority
JP
Japan
Prior art keywords
silicide
forming
nickel
gate
watts
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006549314A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007518274A (ja
JP2007518274A5 (https=
Inventor
エヌジーオー ミン−バン
エス． チャン サイモン
アール． ベセル ポール
エル． キング ポール
トッド リャン エロール
ジェイ． チウ ロバート
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2007518274A publication Critical patent/JP2007518274A/ja
Publication of JP2007518274A5 publication Critical patent/JP2007518274A5/ja
Application granted granted Critical
Publication of JP5265872B2 publication Critical patent/JP5265872B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/50—Alloying conductive materials with semiconductor bodies

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2006549314A 2004-01-12 2004-12-21 集積回路技術における低応力の側壁スペーサ Expired - Fee Related JP5265872B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/756,023 US7005357B2 (en) 2004-01-12 2004-01-12 Low stress sidewall spacer in integrated circuit technology
US10/756,023 2004-01-12
PCT/US2004/043109 WO2005071729A1 (en) 2004-01-12 2004-12-21 Low stress sidewall spacer in integrated circuit technology

Publications (3)

Publication Number Publication Date
JP2007518274A JP2007518274A (ja) 2007-07-05
JP2007518274A5 JP2007518274A5 (https=) 2008-02-14
JP5265872B2 true JP5265872B2 (ja) 2013-08-14

Family

ID=34739734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006549314A Expired - Fee Related JP5265872B2 (ja) 2004-01-12 2004-12-21 集積回路技術における低応力の側壁スペーサ

Country Status (8)

Country Link
US (1) US7005357B2 (https=)
JP (1) JP5265872B2 (https=)
KR (1) KR20060123481A (https=)
CN (1) CN1902743A (https=)
DE (1) DE112004002638B4 (https=)
GB (1) GB2425405B (https=)
TW (1) TWI355733B (https=)
WO (1) WO2005071729A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132352B1 (en) * 2004-08-06 2006-11-07 Advanced Micro Devices, Inc. Method of eliminating source/drain junction spiking, and device produced thereby
EP1949416A2 (en) * 2005-09-23 2008-07-30 Nxp B.V. A method of fabricating a structure for a semiconductor device
US7465635B2 (en) * 2006-09-21 2008-12-16 Texas Instruments Incorporated Method for manufacturing a gate sidewall spacer using an energy beam treatment
US7741181B2 (en) * 2007-11-06 2010-06-22 International Business Machines Corporation Methods of forming mixed gate CMOS with single poly deposition

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766406A (ja) * 1993-08-25 1995-03-10 Oki Electric Ind Co Ltd サリサイド型ｍｏｓｆｅｔ及びその製造方法
JPH07254574A (ja) * 1994-03-16 1995-10-03 Sony Corp 電極形成方法
JP2809113B2 (ja) * 1994-09-29 1998-10-08 日本電気株式会社 半導体装置の製造方法
JPH08186085A (ja) * 1994-12-28 1996-07-16 Nec Corp 半導体装置の製造方法
US5814545A (en) * 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
JP3572561B2 (ja) * 1996-10-11 2004-10-06 富士通株式会社 半導体装置の製造方法
US5858846A (en) * 1997-08-04 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Salicide integration method
JP2000133802A (ja) * 1998-10-28 2000-05-12 Nec Corp 半導体装置とその製造方法
KR100313510B1 (ko) * 1999-04-02 2001-11-07 김영환 반도체 소자의 제조방법
US6368988B1 (en) * 1999-07-16 2002-04-09 Micron Technology, Inc. Combined gate cap or digit line and spacer deposition using HDP
US6040223A (en) * 1999-08-13 2000-03-21 Taiwan Semiconductor Manufacturing Company Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits
KR100407684B1 (ko) * 2000-06-28 2003-12-01 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6483154B1 (en) * 2000-10-05 2002-11-19 Advanced Micro Devices, Inc. Nitrogen oxide plasma treatment for reduced nickel silicide bridging
US6495460B1 (en) * 2001-07-11 2002-12-17 Advanced Micro Devices, Inc. Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface
US6664172B2 (en) * 2002-01-22 2003-12-16 United Microelectronics Corp. Method of forming a MOS transistor with improved threshold voltage stability
US7005376B2 (en) * 2003-07-07 2006-02-28 Advanced Micro Devices, Inc. Ultra-uniform silicides in integrated circuit technology

Also Published As

Publication number Publication date
TWI355733B (en) 2012-01-01
JP2007518274A (ja) 2007-07-05
US7005357B2 (en) 2006-02-28
US20050153496A1 (en) 2005-07-14
KR20060123481A (ko) 2006-12-01
GB2425405A (en) 2006-10-25
CN1902743A (zh) 2007-01-24
WO2005071729A1 (en) 2005-08-04
GB0615073D0 (en) 2006-09-06
GB2425405B (en) 2008-08-20
DE112004002638B4 (de) 2009-11-26
TW200527649A (en) 2005-08-16
DE112004002638T5 (de) 2007-02-01

Similar Documents

Publication Publication Date Title
US6835995B2 (en) Low dielectric constant material for integrated circuit fabrication
US6388296B1 (en) CMOS self-aligned strapped interconnection
US6972223B2 (en) Use of atomic oxygen process for improved barrier layer
US8236678B2 (en) Tunable spacers for improved gapfill
JPH11251457A (ja) 半導体デバイス，メモリ・セル，およびその形成方法
JPH08111527A (ja) 自己整合シリサイド領域を有する半導体デバイスの製造方法
US7843015B2 (en) Multi-silicide system in integrated circuit technology
US6534393B1 (en) Method for fabricating local metal interconnections with low contact resistance and gate electrodes with improved electrical conductivity
JP2007504667A (ja) 集積回路技術におけるシリサイド化スペーサ
JP5265872B2 (ja) 集積回路技術における低応力の側壁スペーサ
KR101093123B1 (ko) 집접 회로 기술에 있어서의 극도로 균일한 실리사이드
US7064067B1 (en) Reduction of lateral silicide growth in integrated circuit technology
US7015076B1 (en) Selectable open circuit and anti-fuse element, and fabrication method therefor
US7670915B1 (en) Contact liner in integrated circuit technology
US7023059B1 (en) Trenches to reduce lateral silicide growth in integrated circuit technology
US7049666B1 (en) Low power pre-silicide process in integrated circuit technology
US7151020B1 (en) Conversion of transition metal to silicide through back end processing in integrated circuit technology
CN1866539B (zh) 集成电路元件及其形成方法
KR20080049161A (ko) 스택형 반도체 장치의 제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071221

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071221

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100421

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110721

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110727

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20111026

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20111102

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20111124

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20111201

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111227

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120201

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120601

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120718

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20120810

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130502

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 5265872

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees