KR20060123481A - 집적회로 기술의 저응력 측벽 스페이서 - Google Patents

집적회로 기술의 저응력 측벽 스페이서 Download PDF

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Publication number
KR20060123481A
KR20060123481A KR1020067013975A KR20067013975A KR20060123481A KR 20060123481 A KR20060123481 A KR 20060123481A KR 1020067013975 A KR1020067013975 A KR 1020067013975A KR 20067013975 A KR20067013975 A KR 20067013975A KR 20060123481 A KR20060123481 A KR 20060123481A
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KR
South Korea
Prior art keywords
forming
silicides
gate
dielectric
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020067013975A
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English (en)
Korean (ko)
Inventor
민흐-반 엔고
시몬 에스. 찬
폴 알. 베세르
폴 엘. 킹
에롤 토드 라이언
로버트 제이. 치유
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20060123481A publication Critical patent/KR20060123481A/ko
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/50—Alloying conductive materials with semiconductor bodies

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020067013975A 2004-01-12 2004-12-21 집적회로 기술의 저응력 측벽 스페이서 Ceased KR20060123481A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/756,023 US7005357B2 (en) 2004-01-12 2004-01-12 Low stress sidewall spacer in integrated circuit technology
US10/756,023 2004-01-12

Publications (1)

Publication Number Publication Date
KR20060123481A true KR20060123481A (ko) 2006-12-01

Family

ID=34739734

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067013975A Ceased KR20060123481A (ko) 2004-01-12 2004-12-21 집적회로 기술의 저응력 측벽 스페이서

Country Status (8)

Country Link
US (1) US7005357B2 (https=)
JP (1) JP5265872B2 (https=)
KR (1) KR20060123481A (https=)
CN (1) CN1902743A (https=)
DE (1) DE112004002638B4 (https=)
GB (1) GB2425405B (https=)
TW (1) TWI355733B (https=)
WO (1) WO2005071729A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132352B1 (en) * 2004-08-06 2006-11-07 Advanced Micro Devices, Inc. Method of eliminating source/drain junction spiking, and device produced thereby
EP1949416A2 (en) * 2005-09-23 2008-07-30 Nxp B.V. A method of fabricating a structure for a semiconductor device
US7465635B2 (en) * 2006-09-21 2008-12-16 Texas Instruments Incorporated Method for manufacturing a gate sidewall spacer using an energy beam treatment
US7741181B2 (en) * 2007-11-06 2010-06-22 International Business Machines Corporation Methods of forming mixed gate CMOS with single poly deposition

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766406A (ja) * 1993-08-25 1995-03-10 Oki Electric Ind Co Ltd サリサイド型ｍｏｓｆｅｔ及びその製造方法
JPH07254574A (ja) * 1994-03-16 1995-10-03 Sony Corp 電極形成方法
JP2809113B2 (ja) * 1994-09-29 1998-10-08 日本電気株式会社 半導体装置の製造方法
JPH08186085A (ja) * 1994-12-28 1996-07-16 Nec Corp 半導体装置の製造方法
US5814545A (en) * 1995-10-02 1998-09-29 Motorola, Inc. Semiconductor device having a phosphorus doped PECVD film and a method of manufacture
JP3572561B2 (ja) * 1996-10-11 2004-10-06 富士通株式会社 半導体装置の製造方法
US5858846A (en) * 1997-08-04 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Salicide integration method
JP2000133802A (ja) * 1998-10-28 2000-05-12 Nec Corp 半導体装置とその製造方法
KR100313510B1 (ko) * 1999-04-02 2001-11-07 김영환 반도체 소자의 제조방법
US6368988B1 (en) * 1999-07-16 2002-04-09 Micron Technology, Inc. Combined gate cap or digit line and spacer deposition using HDP
US6040223A (en) * 1999-08-13 2000-03-21 Taiwan Semiconductor Manufacturing Company Method for making improved polysilicon FET gate electrodes having composite sidewall spacers using a trapezoidal-shaped insulating layer for more reliable integrated circuits
KR100407684B1 (ko) * 2000-06-28 2003-12-01 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6483154B1 (en) * 2000-10-05 2002-11-19 Advanced Micro Devices, Inc. Nitrogen oxide plasma treatment for reduced nickel silicide bridging
US6495460B1 (en) * 2001-07-11 2002-12-17 Advanced Micro Devices, Inc. Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface
US6664172B2 (en) * 2002-01-22 2003-12-16 United Microelectronics Corp. Method of forming a MOS transistor with improved threshold voltage stability
US7005376B2 (en) * 2003-07-07 2006-02-28 Advanced Micro Devices, Inc. Ultra-uniform silicides in integrated circuit technology

Also Published As

Publication number Publication date
TWI355733B (en) 2012-01-01
JP2007518274A (ja) 2007-07-05
US7005357B2 (en) 2006-02-28
US20050153496A1 (en) 2005-07-14
GB2425405A (en) 2006-10-25
CN1902743A (zh) 2007-01-24
WO2005071729A1 (en) 2005-08-04
GB0615073D0 (en) 2006-09-06
GB2425405B (en) 2008-08-20
DE112004002638B4 (de) 2009-11-26
JP5265872B2 (ja) 2013-08-14
TW200527649A (en) 2005-08-16
DE112004002638T5 (de) 2007-02-01

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