Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
  • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
  • G11C13/0009—RRAM elements whose operation depends upon chemical change
  • G11C13/0014—RRAM elements whose operation depends upon chemical change comprising cells based on organic memory material
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
  • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
  • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
  • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
  • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
  • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
  • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B20/00—Read-only memory [ROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B20/00—Read-only memory [ROM] devices
  • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
  • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
  • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
  • H10K19/80—Interconnections, e.g. terminals

Definitions

• the present invention relates to a nonvolatile memory device including a matrix wiring, a switching element, and a storage element.
• U. S. Patent No. 6,034,882 discloses a configuration in which an impedance is varied by applying to the storage element a write voltage inducing the breakdown of a dielectric contained in a storage element, whereby a memory effect is attained. If such a memory device is fabricated by using the above-mentioned organic semiconductor element, the fabrication is expected to be at a low cost.
• the present invention has been made to solve a problem concerning a configuration of the conventional techniques in that ⁇ t is difficult to construct a nonvolatile memory device capable of selecting a desired cell, on a smbstrate having an insulating surface made of glass, resin, or the like, in particular, on a substrate which is inexpensive but in turn cannot bear a high temperature process. It is therefore an object of the present invention to provide a nonvolatile memory devi.ce enabling a construction of an integrated cirrcuit on an inexpensive substrate such as a glass or resin substrate and allowing selection of a desired cell, by adopting an element configuration in which an organic material is used for a switching element and a storage element includes a dielectric.
• a nonvolatile memory device includes: a storage element; a switching element electrically connected to the storage element; and a plurality of lead wirings electrically connected to the switching element or the storage element, all of which are arranged on a substrate having an insulating surface, in which the switching element includes an organic semiconductor, and the storage element contains a dielectric material and stores information by selecting at least two states including a high impedance state and a low impedance state.
• the switching element which includes the organic semiconductor
• the nonvolatile memory device which has a sufficiently large current ratio between two states including "0" and "1" of a memory element, on an inexpensive substrate having an insulating surface made of glass, resin, or the like, by using a printing method.
• Fig. 1 is a circuit diagram illustrating a circuit configuration
• Fig. 2 is a graph showing current density/voltage characteristics of a memory element
• Fig. 3 is a histogram showing a breakdown voltage of the memory element
• Fig. 4 is a graph showing current density/voltage characteristics of storage elements each having an alumina film with a different thickness
• Fig. 5 is a graph showing a basic operation of a memory element in which an organic TFT and a storage element are connected to each other
• Fig. 6 is a cross-sectional view of a main part of a memory element and a transistor element according to a first embodiment of the present invention
• Fig. 1 is a circuit diagram illustrating a circuit configuration
• Fig. 2 is a graph showing current density/voltage characteristics of a memory element
• Fig. 3 is a histogram showing a breakdown voltage of the memory element
• Fig. 4 is a graph showing current density/voltage characteristics of storage elements each having an alumina film with
• FIG. 7 is a cross-sectional view of the main part of the memory element and the transistor element according to the first embodiment of the present invention
• Fig. 8 is a cross-sectional view of the main part of the memory element and the transistor element according to the first embodiment of the present invention
• Fig. 9 is a cross-sectional view of the main part of the memory element and the transistor element according to the first embodiment of the present invention
• Fig. 10 is a cross-sectional view of the main part of the memory element and the transistor element according to the first embodiment of the present invention
• Fig. 11 is a cross-sectional view of the main part of the memory element and the transistor element according to the first embodiment of the present invention
• Fig. 12 is a top view of the memory element and the transistor element according to the first embodiment of the present invention
• Fig. 13 is a circuit diagram illustrating a circuit configuration according to a second embodiment of the present invention.
• a nonvolatile memory device includes a storage element having a changeable impedance, in which a switching element includes an organic semiconductor and the storage element includes a dielectric.
• the basic operation of the nonvolatile memory device is to vary an impedance of the memory element at a read voltage when a write voltage higher than the read voltage is applied to the dielectric in the memory element.
• the switching element is preferably a transistor including an organic semiconductor. This makes it possible to construct a memory array on a glass or resin substrate which is hardly used in a TFT made of an inorganic semiconductor such as silicon and formed via a high temperature process or an etching process. Accordingly, selection of a desired memory cell becomes enabled.
• the transistor there are a field effect type transistor, a thin film type transistor, a junction type transistor, and so forth, but any of those is usable.
• the organic semiconductor includes a 'material of which Fermi level is present within its band gap and which has semiconductor properties.
• the switching element may be a diode including an organic semiconductor. -In this case, a memory device having a relatively simple matrix structure can be fabricated.
• the nonvolatile memory device according to the present invention includes a plurality of lead wirings electrically connected to the switching element or the storage element .
• the lead wirings have a matrix structure, and in particular the configuration preferably includes plate lines in addition to bit lines and word lines, in which one terminal of a transistor is connected to one of the bit lines, another terminal of the transistor is connected to one of the word lines, and still another terminal of the transistor is connected to one of the plate lines via the memory element.
• the plate lines are set to a ground potential, the operation becomes simple. Further, a potential other than the ground potential may be set so as to adjust the voltage applied to the storage element.
• the nonvolatile memory device according to the present invention does not require fabrication involving an etching process with the substrate made of single-crystalline silicon.
• the satisfactory element can be formed by using a substrate having an insulating surface. In particular, it is preferable to use an inexpensive substrate made of resin or glass .
• the nonvolatile memory device is formed on a resin substrate. This makes it possible to utilize the nonvolatile memory device for an IC card or an IC tag. Also, a flexible material such as polyimide is exploitable .
• An electric power source for such an IC card or IC tag may be a power source which externally supplies electricity to a non-built-in-type IC card or IC tag, or a battery built in a battery-built-type IC card or IC tag, and its voltage is preferably equal to or higher than the breakdown voltage of the dielectric.
• the above IC card or IC tag may be used as a nonvolatile memory device in association with a commuter pass, an identification card, or a package delivery, or may be attached to a cartridge for an electrophotographic image forming apparatus such as a laser beam printer or a copying machine (namely, a photosensitive drum or means for containing toner) or attached to a cartridge which contains ink for an ink jet printer using a piezoelectric system or a Bubble Jet (registered trademark) system.
• a laser beam printer or a copying machine namely, a photosensitive drum or means for containing toner
• a cartridge which contains ink for an ink jet printer using a piezoelectric system or a Bubble Jet (registered trademark) system Such a case is preferable because various pieces of information or a large quantity of information can be stored before product shipment or at the time of product use.
• Fig. 1 shows a configuration of a 16-bit memory device including bit lines BLl to BL4; word lines WLl to WL4 intersecting with the bit lines; and unit cells Cll to C44, wherein each unit cell includes one of organic thin film transistors (TFTs) Til to T44 arranged in matrix as the switching elements containing an organic semiconductor, and one of memory elements Rll to R44 as the storage elements.
• TFTs organic thin film transistors
• Each gate electrode of the organic TFTs Til to T44 is connected to a word line, each drain electrode is connected to a bit line, and each source electrode is connected to one terminal of one of the memory elements Rll to R44 where the other terminal thereof is connected to one of the plate lines PL1 to PL4.
• the memory element configuration is a configuration in which a dielectric material is interposed between the electrodes.
• An arrangement example of the dielectric includes formation of a dielectric thin film ttrough a sputtering method etc., or application of a liquid material such as spin on glass between the electrodes before being dried.
• the dielectric include: an inorganic dielectric such as alumina, tantalum oxide, or silicon oxide; a spin on glass material such as silsesquioxane; a polymeric material such as polymethylmethacrylate, polystyrene, or polyimide; and an organic dielectric such as a self-assembled molecule having a long-chain alkyl skeleton. Characteristics of a cell including a polyimide substrate as the resin substrate and a dielectric interposed between two electrodes made of copper and silver in a sandwiching manner will be described below as a specific example of an embodiment of the storage element.
• an inorganic dielectric such as alumina, tantalum oxide, or silicon oxide
• a spin on glass material such as silsesquioxane
• a polymeric material such as polymethylmethacrylate, polystyrene, or polyimide
• an organic dielectric such as a self-assembled molecule having a long-chain alkyl skeleton. Characteristics of
• the dielectric is composed of an alumina thin film having satisfactory insulating characteristics, which has been formed by a sputtering method under a room temperature condition.
• Fig. 2 is a graph of plotting applied voltage versus changed current with respect to the alumina thin film having a thickness of 14 nm interposed between the two electrodes made of copper and silver, as an example. Sweeping of the voltage applied between the electrodes is performed from 0 V to 10 V, but characteristics resulting from the first sweeping varies from those resulting from the second sweeping significantly. In the first sweeping, breakdown occurs at an applied voltage of about 5 V, which leads to a low resistance state because the current amount increases on a large scale. In the second sweeping as well, this low resistance state continues.
• Fig. 3 shows an example of a histogram of a voltage causing breakdown as a threshold voltage value changing the impedance of the memory element.
• the breakdown voltage has a distribution from 4 V to 6.5 V.
• the memory array circuit constructed on the resin substrate can be driven at a write voltage having a lower limit of 6.5 V and at a read voltage having an upper limit of 4 V. Further, it is possible to set a thickness of the insulating film in accordance with a predetermined write operation voltage and a predetermined read operation voltage.
• Fig. 4 is a graph of plotting applied voltage versus changed current when a thickness of the alumina film is set to 19 nm, 23 nm, and 33 nm, as an example. As is apparent from Fig. 4, as the film thickness is larger, the breakdown voltage is shifted on the higher voltage side, and as the film thickness is smaller, the breakdown voltage is shifted on the lower voltage side.
• the film thickness is not limited to the above example .
• a cell obtained by forming the switching element which is an organic TFT formed as a film by vacuum evaporation using pentacene as an organic semiconductor material in such a temperature range imparting no thermal damage to a resin substrate, and a memory element composed of a storage element having a dielectric made of alumina on a polyimide substrate
• Fig. 5 is a graph showing an example of a basic operation of the cell.
• the horizontal axis represents a voltage of the bit line connected to the drain electrode of the TFT, and the vertical axis represents a current of the bit line. This example is obtained when the organic TFT is turned on by setting a voltage of the word line connected to the gate electrode to -25 V.
• the current at ' - the first scan before breakdown is 2.9 nA and the current at the second scan after the breakdown is 293 nA.
• the current has the two states necessary for a memory operation.
• the organic TFT and the dielectric formed on the resin substrate exert the basic operation of the memory element .
• a method for driving the memory device of the present invention will be described by way of example .
• the read operation will be explained. Under the condition that each TFT acts as a p-channel TFT, as a reference potential ("Ref.” in Fig. 1), a voltage of -2 V is applied to a sense amplifier.
• C23 is selected and a voltacre not lower than 5 V is applied to R23, thereby resulting in the fact that the state of R23 is irreversibly shifted to a low- resistance state.
• information is written into C23.
• Such a nonvolatile memory device can be used as a memory for the conventional IC tag or IC card. In this way, it is possible to produce a low-priced IC tag or IC card.
• the device may be attached to a cartridge for an electrophotographic image forming apparatus such as a laser beam printer or a copying machine (i.e., a photosensitive drum or means for containing toner) or attached to a cartridge which contains ink for an ink jet printer using a piezoelectric system,) or a Bubble Jet (registered trademark) system.
• a laser beam printer or a copying machine i.e., a photosensitive drum or means for containing toner
• a Bubble Jet registered trademark
• Reference numeral 1 denotes a substrate
• 2 denotes a contact
• 3 denotes a word line lower electrode
• 4 denotes a word line
• 5 denotes a gate electrode
• 6 denotes a plate line electrode
• 7 denotes a bit line electrode
• 8 denotes a memory element lower electrode
• 9 denotes a gate insulating film
• 10 denotes a dielectric film
• 11 denotes a source electrode
• 12 denotes a drain electrode
• 13 denotes a memory element upper electrode
• 14 denotes an organic semiconductor layer
• 15 denotes a protective film
• 16 denotes a bit line
• 17 denotes a plate line.
• the word line electrode 3, the word line 4, the gate electrode 5, the plate line electrode 6, the bit line electrode 7, and the memory element lower electrode 8 are formed by etching a copper foil on both surfaces (front and rear faces) of the substrate 1 made of polyimide resin as shown in Fig. 6, the bit line 16 and the plate line 17 are formed as shown in Fig. 12, and the contact 2 is formed by embedding plating copper in a through hole, whereby a substrate part is prepared.
• the gate electrode 5 is connected to the word line 4
• the plate line electrode 6 is connected to the plate line 17, and the bit line electrode 7 is connected to the bit line 16.
• an alumina thin film is formed as the gate insulating film 9 by a sputtering method.
• the gate insulating film is selectively formed through a metal mask so as to cover the gate electrode 5.
• an alumina thin film is formed as the dielectric film 10 by the sputtering method.
• the dielectric film is selectively formed through a metal mask so as to cover the memory element lower electrode 8.
• silver electrodes are formed as the source electrode 11, the drain electrode 12, and the memory element upper electrode 13 by a screen printing method.
• the drain electrode 12 is connected to the bit line via the bit line electrode 7.
• the source electrode 11 is connected to the memory element lower electrode 8.
• the memory element upper electrode 13 is connected to the plate line 17 via the plate line electrode 6.
• the organic semiconductor layer 14 is selectively formed through a metal mask on a region sandwiched by the source electrode 11 and the drain electrode 12 and on a region including a part of the respective electrodes, that is, formed so as to cover a region between the electrodes by means of.
• a novolac resin is applied and cured as the protective film 15.
• the memory device including the organic TFT with an electrode arrangement called bottom contact type, and the memory element is formed on the resin substrate by the printing method.
• the same effects are also attained by using an organic TFT with an electrode arrangement called top contact type where the organic semiconductor layer 14 is selectively formed on the gate insulating film through a metal mask and thereafter the source electrode 11 and the drain electrode 12 are formed on the organic semiconductor layer, although not shown in the drawings.
• the bit line is connected to one terminal of the sense amplifier and outputs "0" when the bit line potential is lower than the reference potential comparing with the reference potential of the other terminal (low potential: a voltage close to the power source voltage) , and outputs "1" when the bit line potential is higher than the reference potential (high potential: a voltage close to the ground voltage) .
• a read operation voltage is -4 V and a write operation voltage is -10 V.
• a voltage of -2 V is applied to the sense amplifier as the reference potential ("Ref.” in Fig. 1).
• an operation of reading the information in the cell C23 is conducted.
• a voltage of -20 V is applied to the word line WL3, and the selected transistor T23 is turned on.
• a voltage of -4 V is applied to the bit line BL2.
• a diode can be used as the switching element, and a junction type transistor can be used as the switching element.
• a diode can be used as the switching element.
• Fig. 13 shows an example of the configuration of this embodiment. In this embodiment, each cell has a switching element and a storage element similarly to the first embodiment.
• Each cell in the first embodiment has a transistor element as the switching element, while each cell in the second embodiment has a diode element as the switching element .
• the nonvolatile memory device of this embodiment has a plurality of such cells in the row and column directions (from Cll to C44) .
• the cell Cll has a diode Dll and a memory element Mil.
• One end of each memory element is connected to the diode of each cell, and the other end of each memory element is commonly connected to a word line WL.
• word lines WL There are multiple word lines WL, and each of them is connected to a plurality of memory elements on a column-by- column base .
• One end of the diode that is not connected to the memory element is commonly connected to one of the bit lines BL .
• bit lines BL There are multiple bit lines BL and each of them is connected to one end of a plurality of diodes on a row-by-row base.
• the read operation will be described. For example, in selecting the cell C22, a constant voltage Vcc is applied to BL2 so that current flows to the grounded BL2 via the resistor R2. In this occasion, a voltage not lower than Vcc is applied to word lines WL other than WL2 so that no current flows into cells other than the selected one. At this moment, by comparing the potential of BL2 with the reference voltage Ref., it is possible to read informatio . Next, the write operation will be described.
• each cell has the switching element and the storage element.
• the storage element contains alumina as the dielectric formed by the sputtering method.
• polyimide which is a polymeric material is used as the dielectric. It is confirmed that the obtained memory device can be operated similarly to the first embodiment.

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• Semiconductor Memories (AREA)
• Thin Film Transistor (AREA)
• Read Only Memory (AREA)

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• 2003
  • 2003-12-18 JP JP2003421309A patent/JP2005183619A/ja not_active Withdrawn
• 2004
  • 2004-12-06 US US10/546,216 patent/US7359230B2/en not_active Expired - Fee Related
  • 2004-12-06 WO PCT/JP2004/018522 patent/WO2005060001A1/en not_active Ceased

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