WO2005055282A2 - Low loop height ball bonding method and apparatus - Google Patents
Low loop height ball bonding method and apparatus Download PDFInfo
- Publication number
- WO2005055282A2 WO2005055282A2 PCT/US2004/039676 US2004039676W WO2005055282A2 WO 2005055282 A2 WO2005055282 A2 WO 2005055282A2 US 2004039676 W US2004039676 W US 2004039676W WO 2005055282 A2 WO2005055282 A2 WO 2005055282A2
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- Prior art keywords
- wire
- bond
- capillary
- fold
- ball
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
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Definitions
- the invention pertains to wire bonding on semiconductor devices.
- the wire 17 is passed through a set of clamps 18 and
- wire "tail” 23 is protruding from the tip of the capillary 11 , as shown in Figure
- spark 16 termed an electric flame off (EFO) from an EFO wand 24.
- EFO electric flame off
- the capillary 11 is
- This bond typically is termed a ball bond or first
- the capillary 11 is then lowered to pinch the wire between the capillary and
- ultrasonic energy may be applied to bond the pinched portion of the wire to the lead finger 21. This bond is termed a stitch bond or second bond.
- connection 22 is termed a wire loop and is illustrated in Figure 11.
- the minimal loop height is normally over 150
- Loop height is defined as the maximum height of the wire above the
- bonding surface e.g., the top surface of the bond pad.
- the neck is the
- thinner packages are generally referred to in the trade as low profile packages.
- the desire to reduce the height of the package is the desire to reduce the height of the highest point of the wire loops, which, in many instances, is the limiting factor as to the height of an integrated circuit package.
- reverse looping a wire looping technique known as reverse looping was developed.
- the premise behind reverse looping is that, because the highest point of the wire loop is adjacent the ball bond, it would be desirable reverse the looping process so as to make the first, ball bond on the lead frame (or other substrate) and make the second, stitch bond on the bond pad of the die because the surface of the lead frame is lower than the surface of the die.
- the highest point of the wire loop is near the lower bonding surface, thus reducing the overall height.
- the stitch bond requires the capillary to come in contact with the bonding surface.
- the bond pads on a die usually are very small and, thus, it is difficult to make a stitch bond on a bond pad on a die without the capillary contacting and, hence, damaging surrounding circuitry on the die.
- the wire loops tends to sag to their lowest points close to the stitch bond.
- the stitch bond site is higher than the ball bond site, the wire might contact the edge or the top surface of the die. This could lead to electrical shorts or breakage of the wire.
- stitch bond 43 is formed on top of the first ball bond (or bump) 25.
- This reverse looping process can provide low loop heights for
- top of the die bond pad must be large enough to provide support for a stitch
- the diameter of the bump will increase in the lateral
- a bump is formed on the die
- the capillary undergoes a set of coordinated xyz
- bond site e.g., the lead frame or other substrate
- capillary is raised in the z direction a designated height (herein termed the
- the capillary may or may not be raised
- FIGS. 1 A through 11 are elevation views illustrating the steps
- Figures 2A through 2C are elevation views illustrating steps of a
- Figure 3 is a pictorial elevation view of a folded wire loop
- Figure 4 is a pictorial elevation view showing the various components
- FIGS. 5A through 5O are elevation views illustrating the steps
- Figure 6 is a pictorial elevation view showing the various components
- Figure 7 is a side view of a bump and fold formed using the
- Figures 8A and 8B are scanning electron micrographs of a
- Figure 3 is a side elevation pictorial of a folded forward wire
- FIG. 3 shows an
- integrated circuit die 51 including a bond pad 53 on its top surface and a lead
- the wire loop 45 is formed in accordance with the technique of the present invention may be considered to comprise five
- Figures 5A through 5O illustrate the position of the capillary of
- the vertical direction is termed the z direction and the
- Figure 5E shows the capillary position after this step.
- the direction of the fold offset is exactly opposite the xy direction toward the second bond site 65.
- the distance of this xy motion is herein
- the capillary 11 is raised again (in the positive z direction) a
- Figure 5H shows the position of the capillary 11 and the condition of
- the fold return motion is in the xy direction exactly opposite the
- the fold return motion preferably is a purely horizontal (i.e.,
- the fold return motion 78 may include a negative z component to return the capillary to the same height that
- the capillary returns to a height below the
- the fold return motion 78 may include a positive
- the fold return offset In other words, the fold return
- fold return motion 78 is less than the fold offset motion 76, the fold return
- fold return motion 78 is longer than the fold offset motion 76, the fold return
- the fold return motion 78 have the same xy (i.e., horizontal) magnitudes, then
- the fold return offset is zero.
- ultrasonic energy may be applied to facilitate bonding of the
- Figure 5J shows the process at this point, which is essentially the same position as shown in Figure 51 since the capillary
- FIG. 5K and 5L show the position of the capillary 11
- the coordinated xyz motion can be relatively simple, comprising
- the wire loop 59 is continuous with the bump 56, fold 57, and stitch
- Heat and/or ultrasonic energy may be
- Figure 5N illustrates the position of the capillary at this point in the process.
- clamps 18 are then closed and the capillary 11 is raised further to snap
- the looping technique of the present invention provides ultra-low loop heights because the wire exits the ball bond site pointing horizontally rather than vertically upward.
- the wire bonding machine is controlled by motion control
- the circuitry comprises a digital processing device such as a programmed general purpose computer, a digital signal processor, a state machine, a combinational logic circuit, a microprocessor, an application specific integrated circuit, or any other known digital processing means. If the circuitry comprises a computer, the invention
- Figure 6 shows exemplary parameters that were used to form the fold shown in Figure 7 and subsequently the loop profile shown in Figures 8A and 8B.
- the first three motions (separation height 75, fold offset 76 and fold factor 77) collectively determine the amount
- the fold return motion 78 determines the final shape of the
- the fold return motion 78 is specified by two parameters. Specifically, (1) the aforementioned fold return
- bump height normally should be a
- the bump height is -1.25 mil and the separation
- the final position of the capillary is about 0.25 mil above the bump 56. This provides just enough flattening of the wire to form
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006541443A JP2007512714A (ja) | 2003-11-26 | 2004-11-24 | 低いループ高さのボールボンディング方法およびその装置 |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US52530503P | 2003-11-26 | 2003-11-26 | |
| US60/525,305 | 2003-11-26 | ||
| US10/988,053 US7347352B2 (en) | 2003-11-26 | 2004-11-12 | Low loop height ball bonding method and apparatus |
| US10/988,053 | 2004-11-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO2005055282A2 true WO2005055282A2 (en) | 2005-06-16 |
| WO2005055282A3 WO2005055282A3 (en) | 2006-02-09 |
Family
ID=34595261
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2004/039676 Ceased WO2005055282A2 (en) | 2003-11-26 | 2004-11-24 | Low loop height ball bonding method and apparatus |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7347352B2 (enExample) |
| JP (1) | JP2007512714A (enExample) |
| SG (1) | SG123792A1 (enExample) |
| TW (1) | TWI367533B (enExample) |
| WO (1) | WO2005055282A2 (enExample) |
Cited By (1)
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|---|---|---|---|---|
| WO2007012187A1 (en) * | 2005-07-26 | 2007-02-01 | Microbonds Inc. | System and method for assembling packaged integrated circuits using insulated wire bond |
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| US7229906B2 (en) * | 2002-09-19 | 2007-06-12 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
| US7464854B2 (en) * | 2005-01-25 | 2008-12-16 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming a low profile wire loop |
| DE102006011352A1 (de) * | 2005-03-23 | 2006-10-05 | Unaxis International Trading Ltd. | Verfahren zur Herstellung einer Drahtverbindung |
| US8016182B2 (en) * | 2005-05-10 | 2011-09-13 | Kaijo Corporation | Wire loop, semiconductor device having same and wire bonding method |
| JP4530984B2 (ja) * | 2005-12-28 | 2010-08-25 | 株式会社新川 | ワイヤボンディング装置、ボンディング制御プログラム及びボンディング方法 |
| WO2007134317A1 (en) * | 2006-05-15 | 2007-11-22 | Texas Instruments Incorporated | Downhill wire bonding for semiconductor device |
| US20080286959A1 (en) * | 2007-05-14 | 2008-11-20 | Texas Instruments Incorporated | Downhill Wire Bonding for QFN L - Lead |
| US20100186991A1 (en) * | 2006-10-18 | 2010-07-29 | Kulicke And Soffa Industries, Inc. | conductive bumps, wire loops including the improved conductive bumps, and methods of forming the same |
| JP5481769B2 (ja) * | 2006-11-22 | 2014-04-23 | 日亜化学工業株式会社 | 半導体装置及びその製造方法 |
| US8637394B2 (en) * | 2007-07-05 | 2014-01-28 | Stats Chippac Ltd. | Integrated circuit package system with flex bump |
| US8048720B2 (en) * | 2008-01-30 | 2011-11-01 | Kulicke And Soffa Industries, Inc. | Wire loop and method of forming the wire loop |
| JP4625858B2 (ja) * | 2008-09-10 | 2011-02-02 | 株式会社カイジョー | ワイヤボンディング方法、ワイヤボンディング装置及びワイヤボンディング制御プログラム |
| JP4344002B1 (ja) | 2008-10-27 | 2009-10-14 | 株式会社新川 | ワイヤボンディング方法 |
| JP5062283B2 (ja) * | 2009-04-30 | 2012-10-31 | 日亜化学工業株式会社 | 半導体装置及びその製造方法 |
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| DE102009029040A1 (de) * | 2009-08-31 | 2011-03-03 | Robert Bosch Gmbh | Vorrichtung und Verfahren zur Herstellung einer Vorrichtung |
| JP2012004464A (ja) * | 2010-06-18 | 2012-01-05 | Toshiba Corp | 半導体装置、半導体装置の製造方法及び半導体装置の製造装置 |
| US20120032354A1 (en) * | 2010-08-06 | 2012-02-09 | National Semiconductor Corporation | Wirebonding method and device enabling high-speed reverse wedge bonding of wire bonds |
| US7918378B1 (en) | 2010-08-06 | 2011-04-05 | National Semiconductor Corporation | Wire bonding deflector for a wire bonder |
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| CN102487025B (zh) | 2010-12-08 | 2016-07-06 | 飞思卡尔半导体公司 | 用于长结合导线的支撑体 |
| US8609525B2 (en) * | 2011-03-21 | 2013-12-17 | Stats Chippac Ltd. | Integrated circuit packaging system with interconnects and method of manufacture thereof |
| MY181180A (en) * | 2011-09-09 | 2020-12-21 | Carsem M Sdn Bhd | Low loop wire bonding |
| TWI543284B (zh) * | 2014-02-10 | 2016-07-21 | 新川股份有限公司 | 半導體裝置的製造方法以及打線裝置 |
| US12057431B2 (en) * | 2020-12-18 | 2024-08-06 | Kulicke And Soffa Industries, Inc. | Methods of forming wire interconnect structures and related wire bonding tools |
| US12142595B2 (en) * | 2020-12-23 | 2024-11-12 | Skyworks Solutions, Inc. | Apparatus and methods for tool mark free stitch bonding |
| WO2023158625A1 (en) * | 2022-02-15 | 2023-08-24 | Kulicke And Soffa Industries, Inc. | Methods of determining a sequence for creating a plurality of wire loops in connection with a workpiece |
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| US5842628A (en) * | 1995-04-10 | 1998-12-01 | Fujitsu Limited | Wire bonding method, semiconductor device, capillary for wire bonding and ball bump forming method |
| JPH0951011A (ja) | 1995-08-10 | 1997-02-18 | Tanaka Denshi Kogyo Kk | 半導体チップのワイヤボンディング方法 |
| JP3370539B2 (ja) | 1997-01-13 | 2003-01-27 | 株式会社新川 | ワイヤボンディング方法 |
| JP3413340B2 (ja) * | 1997-03-17 | 2003-06-03 | 株式会社新川 | ワイヤボンディング方法 |
| JP3455092B2 (ja) * | 1997-10-27 | 2003-10-06 | 株式会社新川 | 半導体装置及びワイヤボンディング方法 |
| JP2000082717A (ja) * | 1998-09-07 | 2000-03-21 | Shinkawa Ltd | ワイヤボンディング方法 |
| JP3522123B2 (ja) * | 1998-09-30 | 2004-04-26 | 株式会社新川 | ワイヤボンディング方法 |
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| JP3457196B2 (ja) | 1998-12-22 | 2003-10-14 | 株式会社カイジョー | ボールボンディング方法 |
| JP3932235B2 (ja) | 1999-02-25 | 2007-06-20 | 株式会社カイジョー | ワイヤボンダ用ボール形成装置及びその方法 |
| JP3913134B2 (ja) * | 2002-08-08 | 2007-05-09 | 株式会社カイジョー | バンプの形成方法及びバンプ |
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| JP3765778B2 (ja) * | 2002-08-29 | 2006-04-12 | ローム株式会社 | ワイヤボンディング用キャピラリ及びこれを用いたワイヤボンディング方法 |
| US7229906B2 (en) * | 2002-09-19 | 2007-06-12 | Kulicke And Soffa Industries, Inc. | Method and apparatus for forming bumps for semiconductor interconnections using a wire bonding machine |
| JP2004172477A (ja) * | 2002-11-21 | 2004-06-17 | Kaijo Corp | ワイヤループ形状、そのワイヤループ形状を備えた半導体装置、ワイヤボンディング方法及び半導体製造装置 |
| US6815836B2 (en) * | 2003-03-24 | 2004-11-09 | Texas Instruments Incorporated | Wire bonding for thin semiconductor package |
| JP4021378B2 (ja) * | 2003-06-27 | 2007-12-12 | 株式会社新川 | ワイヤボンディング方法 |
| US7494042B2 (en) * | 2003-10-02 | 2009-02-24 | Asm Technology Singapore Pte. Ltd. | Method of forming low wire loops and wire loops formed using the method |
| US20060011710A1 (en) * | 2004-07-13 | 2006-01-19 | Asm Technology Singapore Pte Ltd | Formation of a wire bond with enhanced pull |
| US7188759B2 (en) * | 2004-09-08 | 2007-03-13 | Kulicke And Soffa Industries, Inc. | Methods for forming conductive bumps and wire loops |
| JP4298665B2 (ja) * | 2005-02-08 | 2009-07-22 | 株式会社新川 | ワイヤボンディング方法 |
-
2004
- 2004-11-12 US US10/988,053 patent/US7347352B2/en not_active Expired - Lifetime
- 2004-11-24 WO PCT/US2004/039676 patent/WO2005055282A2/en not_active Ceased
- 2004-11-24 SG SG200604112A patent/SG123792A1/en unknown
- 2004-11-24 JP JP2006541443A patent/JP2007512714A/ja active Pending
- 2004-11-26 TW TW093136568A patent/TWI367533B/zh not_active IP Right Cessation
-
2007
- 2007-11-20 US US11/942,997 patent/US7584881B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007012187A1 (en) * | 2005-07-26 | 2007-02-01 | Microbonds Inc. | System and method for assembling packaged integrated circuits using insulated wire bond |
Also Published As
| Publication number | Publication date |
|---|---|
| SG123792A1 (en) | 2006-07-26 |
| US7347352B2 (en) | 2008-03-25 |
| US7584881B2 (en) | 2009-09-08 |
| JP2007512714A (ja) | 2007-05-17 |
| TW200524068A (en) | 2005-07-16 |
| US20050109819A1 (en) | 2005-05-26 |
| TWI367533B (en) | 2012-07-01 |
| US20080111252A1 (en) | 2008-05-15 |
| WO2005055282A3 (en) | 2006-02-09 |
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