CN102412167B - 用于线接合的固定 - Google Patents

用于线接合的固定 Download PDF

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CN102412167B
CN102412167B CN201010292924.5A CN201010292924A CN102412167B CN 102412167 B CN102412167 B CN 102412167B CN 201010292924 A CN201010292924 A CN 201010292924A CN 102412167 B CN102412167 B CN 102412167B
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line
closing
reinforcing
described surface
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CN102412167A (zh
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黄美权
刘赫津
张汉民
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

一种电连接，包括第一连线，其具有针脚式接合至表面的一端，所述表面例如是引线框的引线指或者衬底的连接衬垫。第二连线的第一端在第一连线的第一侧上连接到所述表面，以及第二连线的第二端在第一连线的相反的第二侧上连接到所述表面。所述第二连线作为防止第一连线从所述表面剥离的固定。如果需要，可以增加第三连线，其类似于第二连线，作为防止第一连线从所述表面剥离的固定。

Description

用于线接合的固定
背景技术
本发明通常涉及半导体封装，以及更具体地涉及用于线接合的固定。
线接合通常涉及利用接合线将集成电路(IC)管芯上的接合衬垫与引线框的引线指(leadfinger)相连接。参考图1，示出了现有的线接合10，其中连线12的一端利用球焊连接到集成电路的接合衬垫14，以及连线12的第二端利用针脚式接合连接到引线框的引线指16(或连接到衬底的连接衬垫)。
如本领域技术人员所知的，例如，在受到外力冲击时，连线12并且具体的是所述针脚式接合易于损坏封装工艺期间的模塑化合物(或者使其开裂或者破裂)。对于更短或者更薄的连线来说，该问题更加严重。
由此，有利的是具有一种加固的并且不容易被外力损坏的线接合。
附图说明
当结合附图阅读时，将会更好地理解本发明的优选实施例的以下具体实施方式。通过举例的方式示出了本发明，并且本发明不限于附图，其中相同的参考标号表明相同的部件。将理解，附图不是按比例绘制的，并且已经为了便于理解本发明而进行了简化。
图1是现有的线接合的放大透视图；
图2是根据本发明实施例的加固的线接合的放大透视图；以及
图3是根据本发明另一实施例的加固的线接合的放大透视图。
具体实施方式
以下参考附图阐述的具体实施方式意在描述当前本发明的优选实施例，而并非意图表示本发明仅仅可以以这种形式实施。将要理解，可以通过意图被包括在本发明精神和保护范围内的不同的实施例来完成相同的或等效的功能。
本发明提供了一种将引线框的引线指连接到集成电路(IC)管芯上的接合衬垫的方法。该方法包括如下的步骤，将来自集成电路接合衬垫的第一接合线接合至引线框的引线指，并随后利用第二连线加固该线至引线指的连接。在本发明的另一实施例中，利用额外的第三连线加固所述线至引线指的连接。
本发明还提供了一种加固的针脚式接合，所述针脚式接合包括：被针脚式接合至连接衬垫的第一连线的一端；以及第二连线，配置在邻近于所述针脚式接合的第一连线之上，加固所述针脚式接合。在可选实施例中，邻近于第二连线，第三连线被配置在第一连线之上，用于提供额外的力以加固第一连线的针脚式接合。所述第三连线通常可以平行于第二连线、与第二连线成一定角度、或者在一个实施例中，可以与第二连线交叉。
现在参考图2，示出了用于线接合或者加固的针脚式接合的固定的放大透视图。在图2中，第一连线20具有接合至第一表面24的第一端22。如图所示，第一端22被球焊至第一表面24。第一连线20的第二端26连接到第二表面28。第一连线20相对于第二表面28成小于90°的角度。通常，利用针脚式接合形成该连接。第一连线20电气地连接第一和第二表面24和28。第一和第二表面24、28例如可以是集成电路的接合衬垫和引线框的引线指。在可选实施例中，第二表面28可以是印刷电路板(PCB)或者衬底的连接衬垫。第一连线20可以是任何导电的连线，例如金线或者铜线，可以是裸露的或者被包覆的。在所示的示例中，如通常在半导体封装中使用的，连线20包括1.3mil的金线。
第二连线30的第一端32在第一连线20的第一侧上连接到第二表面28，以及第二连线30的第二端34在第一连线20的相反的第二侧上连接到第二表面28。第二连线30由此在邻近于第一连线20第二端26处在第一连线20之上形成环扣。第二连线30在第一连线20受到外力时防止第一连线20从第二表面28剥离，所述外力例如是由于处理或者在其中塑模化合物被配置在连线20和第一和第二表面24和28之上的封装工艺期间导致的外力。就此而言，第二连线34可以与第一连线20在第二连线30与第一连线20交叉的位置处接触。
可以利用现有的线接合设备将第二连线30连接到第二表面28。此外，第二连线30优选与第一连线20相同。由此，如果第一连线20是1.3mil的金线，则第二连线30优选地也是1.3mil金线。在本发明的优选实施例中，在球焊之后进行针脚式接合，由此将第二连线30连接到第二表面28。
现在参考图3，示出了本发明的可选实施例的放大透视图。在本实施例中，其类似于图2所示的实施例，提供了第三连线36，其第一端38在第一连线20第一侧上连接到第二表面28以及其第二端40在第一连线20第二侧上连接到第二表面28。第三连线36也防止了第一连线20从第二表面28剥离。在所示出的实施例中，第三连线36平行于第二连线30并且与第二连线30间隔开，但这不是必须的。例如，第二和第三连线30、36可以非常靠近，由此使得二者之间的间距几乎难以察觉；另一方面，第二和第三连线30、36可以彼此间隔开第二表面28的尺寸所允许的最大距离。尽管在所示出的该实施例中第三连线36大体平行于第二连线30，但是第三连线36可以相对于第二连线30成某一角度配置，或者在一个实施例中，第三连线36可以与第二连线30交叉。类似第二连线30，第三连线36优选地利用当前可用的线接合设备被球焊并随后被针脚式接合至第二表面28。
如上文清楚地讨论的，本发明提供了一种加固至连接衬垫的针脚式接合的方法，其中连接衬垫可以是引线框的引线指或者例如PCB的衬底的连接衬垫。
尽管已经示出和描述了本发明的优选实施例，但是很显然本发明不仅仅局限于这些实施例。在不背离如权利要求书描述的本发明的精神和保护范围的情况下，许多的改型、变化、改变、替换和等价物对于本领域技术人员是明显的。

Claims (10)

1.一种加固至表面的接合线的方法，包括：
通过将第一连线连接到所述表面从而形成第一线接合，其中在所述第一连线和所述表面之间建立机械连接和电连接；
在所述第一连线一侧上将第二连线的第一端接合至相同的所述表面；以及
在所述第一连线的相反的第二侧上将所述第二连线的第二端接合到相同的所述表面，由此使得所述第二连线防止所述第一连线从所述表面剥离。
2.如权利要求1所述的加固至表面的接合线的方法，其中所述表面包括引线框的引线指。
3.如权利要求1所述的加固至表面的接合线的方法，其中所述表面包括衬底接合衬垫。
4.如权利要求1所述的加固至表面的接合线的方法，其中所述第一连线相对于所述表面成小于90度的角度。
5.如权利要求1所述的加固至表面的接合线的方法，其中所述第二连线与所述第一连线接触。
6.如权利要求1所述的加固至表面的接合线的方法，进一步包括：
在所述第一连线的一侧上将第三连线的第一端接合至相同的所述表面；以及
在所述第一连线的相反侧上将所述第三连线的第二端接合至相同的所述表面，由此使得除了所述第二连线之外，所述第三连线也将所述第一连线夹紧至所述表面。
7.一种加固至表面的接合线的方法，包括：
通过利用针脚式接合将第一连线连接至所述表面从而形成第一线接合；
在所述第一线接合的一侧上将第二连线的第一端接合至相同的所述表面；以及
在所述第一连线的相反的第二侧上将所述第二连线的第二端接合至相同的所述表面，由此使得所述第二连线防止所述第一连线从所述表面剥离，其中所述第一和第二连线利用线接合装置连接到所述表面。
8.一种电连接，包括：
第一连线，其具有针脚式接合到一表面的一端；以及
第二连线，其具有在所述第一连线的第一侧上连接到相同的所述表面的第一端，以及在所述第一连线的相反的第二侧上连接到相同的所述表面的第二端，其中所述第二连线防止所述第一连线从所述表面剥离。
9.如权利要求8所述的电连接，进一步包括：第三连线，其具有在所述第一连线的所述第一侧上连接到相同的所述表面的第一端，以及在所述第一连线的所述第二侧上连接到相同的所述表面的第二端，其中所述第三连线也防止所述第一连线从所述表面剥离。
10.如权利要求9所述的电连接，其中所述第三连线大体上平行于所述第二连线。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476506B1 (en) * 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
US6476503B1 (en) * 1999-08-12 2002-11-05 Fujitsu Limited Semiconductor device having columnar electrode and method of manufacturing same
CN101145527A (zh) * 2006-09-14 2008-03-19 株式会社瑞萨科技 半导体装置之制造方法及半导体装置

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5200362A (en) 1989-09-06 1993-04-06 Motorola, Inc. Method of attaching conductive traces to an encapsulated semiconductor die using a removable transfer film
US20040124545A1 (en) 1996-12-09 2004-07-01 Daniel Wang High density integrated circuits and the method of packaging the same
JP2001015541A (ja) * 1999-06-28 2001-01-19 Sumitomo Electric Ind Ltd 半導体装置および半導体装置の製造方法
US6348726B1 (en) 2001-01-18 2002-02-19 National Semiconductor Corporation Multi row leadless leadframe package
US7347352B2 (en) 2003-11-26 2008-03-25 Kulicke And Soffa Industries, Inc. Low loop height ball bonding method and apparatus
US6992377B2 (en) * 2004-02-26 2006-01-31 Freescale Semiconductor, Inc. Semiconductor package with crossing conductor assembly and method of manufacture
CN1964009A (zh) 2005-11-09 2007-05-16 飞思卡尔半导体公司 线环支架
JP2007214314A (ja) * 2006-02-09 2007-08-23 Shinkawa Ltd 半導体装置
CN101192588A (zh) 2006-11-17 2008-06-04 飞思卡尔半导体公司 引线接合及其形成方法
US7868431B2 (en) * 2007-11-23 2011-01-11 Alpha And Omega Semiconductor Incorporated Compact power semiconductor package and method with stacked inductor and integrated circuit die

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6476503B1 (en) * 1999-08-12 2002-11-05 Fujitsu Limited Semiconductor device having columnar electrode and method of manufacturing same
US6476506B1 (en) * 2001-09-28 2002-11-05 Motorola, Inc. Packaged semiconductor with multiple rows of bond pads and method therefor
CN101145527A (zh) * 2006-09-14 2008-03-19 株式会社瑞萨科技 半导体装置之制造方法及半导体装置

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