WO2005050733A1 - Structure de cablage pour onde haute-frequence, procede de fabrication de ladite structure et procede de mise en forme de forme d'onde de signal haute-frequence - Google Patents

Structure de cablage pour onde haute-frequence, procede de fabrication de ladite structure et procede de mise en forme de forme d'onde de signal haute-frequence Download PDF

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Publication number
WO2005050733A1
WO2005050733A1 PCT/JP2004/017001 JP2004017001W WO2005050733A1 WO 2005050733 A1 WO2005050733 A1 WO 2005050733A1 JP 2004017001 W JP2004017001 W JP 2004017001W WO 2005050733 A1 WO2005050733 A1 WO 2005050733A1
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WO
WIPO (PCT)
Prior art keywords
frequency
transmission line
segments
segment
wiring structure
Prior art date
Application number
PCT/JP2004/017001
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English (en)
Japanese (ja)
Inventor
Moritoshi Yasunaga
Ikuo Yoshihara
Original Assignee
Japan Science And Technology Agency
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Science And Technology Agency filed Critical Japan Science And Technology Agency
Publication of WO2005050733A1 publication Critical patent/WO2005050733A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths

Definitions

  • High-frequency wiring structure method for forming high-frequency wiring structure, and method for shaping high-frequency signal waveform
  • the present invention relates to a high-frequency wiring structure, a high-frequency mounting substrate using the high-frequency wiring structure, an integrated circuit and a high-frequency mounting substrate, a method of forming a high-frequency wiring structure, and a method of shaping a high-frequency signal waveform. is there.
  • FIG. 21 shows a problem of waveform distortion caused by impedance mismatch.
  • the signal (digital signal) sent from the VLSI is transmitted through the wiring with the characteristic impedance Z,
  • Radiation noise occurs.
  • the reflected noise propagates while reflecting on the wiring, which is superimposed on the digital signal and causes large waveform distortion.
  • Non-Patent Document 5 a technique has been proposed in which an integrated circuit that generates a signal for canceling a reflected wave is added to a transmission line.
  • Non-Patent Document 1 "High Speed Transmission Line Design in the Gigahertz Age” by Yuzo Usui, IEICE Technical Report F
  • Non-Patent Document 2 Hirokazu Toya, "Wiring Design Method Considering Signals as Electromagnetic Waves, Suitable for High-Speed Z-Micro Process," IEICE Trans. (C), Vol. J85-C No. 3, PP. 117-124, Issued in 2002
  • Non-Patent Document 3 "High-speed Digital System Design Method” by Norihiko Ueno and Yoshie Nakamura, Nikkei Business Publications, 2001
  • Non-Patent Document 4 Masao TAGUCHI, "High-Speed, Small-Amplitude I / O Interlace Circuits for Memory Bus Applicatio IEICE Trans. Electronics, Vol.E77-C, No. 12, pp. 1944-1950, 1994
  • Non-Patent Document 5 "Equalization technology for high-speed inter-chip signal transmission", written by Yasushi Tamura, Kotaro Goto, Misato Saito, Makoto Hariko, Shigetoshi Wakayama, Junni Ogawa, Yoshiharu Kato, Masao Taro and Ken Imamura, Shinnobu, Academic Theory (C-II), Vol. J82-C-II No. 5, PP. 239-246, 1999 and Information Processing Vol. 40, No. 8, pp. 795-800, 1999
  • An object of the present invention is to provide a high-frequency wiring structure capable of reducing waveform distortion of a high-frequency signal, a high-frequency mounting substrate using the high-frequency wiring structure, an integrated circuit, a high-frequency mounting substrate, and a high-frequency wiring structure. And a method for shaping a high-frequency signal.
  • Another object of the present invention is to provide a new wiring structure for a high-frequency mounting board on which a VLSI or the like is mounted, and a design method thereof.
  • the present invention proposes a transmission line structure, that is, a high-frequency wiring structure in which a wiring pattern is divided into a plurality of segments to adjust a global impedance and cancel a reflected wave, instead of a conventional local adjustment. I do.
  • this transmission line is divided into segments.
  • the present invention aims to improve a high-frequency wiring structure provided with a wiring pattern constituting a transmission line through which a high-frequency signal (a signal having a frequency of 200 MHz or more) is transmitted.
  • the wiring pattern is constituted by a plurality of segments having different characteristic impedances due to different shapes. Then, the characteristic impedance of each of the plurality of segments is determined so that a reflected wave that reduces the waveform distortion of the signal propagating through the transmission line is generated at the boundary between two adjacent segments.
  • the basic idea of the present invention is to reverse the idea of the conventional wiring design that prevents the generation of reflected waves, and to actively generate reflection at the boundary between two adjacent segments of the transmission line, Is to reduce the waveform distortion of the signal by superimposing them.
  • the technical idea of the present invention is that the waveform of the signal propagating through the transmission line is shaped by superimposing the characteristic impedance of each of the plurality of segments with the reflection noise generated at the boundary between the segments. It must be determined as follows. In this way, the waveform distortion can be reduced more reliably than in the conventional technique only by the shape of the wiring pattern without preparing a special integrated circuit or the like.
  • the high-frequency wiring structure of the present invention can of course be applied to a high-frequency mounting board provided on an insulating substrate, but the high-frequency wiring structure of the present invention can be applied to a wiring pattern inside an integrated circuit such as a microprocessor. Of course, it may be adopted. If the frequency of the signal is further increased, the problem of reflection naturally occurs even in a wiring pattern in an integrated circuit, but the present invention is also effective in an integrated circuit.
  • the present invention relates to a high-frequency device having a wiring pattern constituting a transmission line for transmitting a high-frequency signal of 200 MHz or more on a surface of an insulating substrate and mounting an integrated circuit electrically connected to the wiring pattern.
  • the wiring pattern When applied to a mounting board, the wiring pattern should consist of multiple segments with different characteristic impedances due to differences in shape, and the characteristic impedance of each of the multiple segments should be superimposed by the reflected noise generated by each segment. May be determined so that the waveform of the signal propagating through the transmission line is shaped.
  • the characteristic impedance of the segment can be set to a predetermined value by changing at least one of the width, length, and thickness of the segment.
  • the characteristic impedance of a segment is set by changing the width of the segment while keeping the length of the segment constant, it is relatively easy to set the characteristic impedance.
  • the method of the present invention is a method for forming a high-frequency wiring structure having a wiring pattern constituting a transmission line through which a high-frequency signal is transmitted, by a plurality of segments having different characteristic impedances due to different shapes.
  • a reflected wave that reduces the waveform distortion of a signal propagating through a transmission line is generated at a boundary between two adjacent segments by using an optimization algorithm such as a genetic algorithm (a plurality of segments).
  • the characteristic impedance of each segment is designed so that the waveform of the signal propagating through the transmission line is shaped by superimposing the reflected noise generated in each segment.
  • the optimization algorithm applicable in the present invention other known appropriate optimization algorithms can be used in addition to the genetic algorithm.
  • the present invention can also be specified as a method of shaping the waveform of a high-frequency signal by changing a high-frequency wiring structure including a wiring pattern forming a transmission line through which a high-frequency signal is transmitted.
  • the wiring pattern is composed of a plurality of segments having different characteristic impedances due to the difference in shape, and the characteristic impedance of each of the plurality of segments is propagated through the transmission line by superimposing the reflection noise generated in each segment.
  • the waveform of the high-frequency signal is determined to be shaped. Then, the shape of the plurality of segments may be designed using the aforementioned genetic algorithm.
  • FIG. 1 is a circuit diagram showing the concept of a segmented transmission line.
  • FIG. 2 is a diagram showing mapping of characteristic impedance and resistance of the segmented transmission line of FIG. 1 onto a chromosome.
  • FIG. 3 is a diagram showing an example of a segmented transmission line.
  • FIG. 4 is a diagram showing a configuration of a segmented transmission line design support system.
  • FIG. 5 is a diagram showing fitness values based on a difference between a waveform to be shaped and an ideal waveform.
  • FIG. 6 is a diagram showing a configuration of a memory module connected to clock wiring on a printed circuit board.
  • FIG. 7 is a diagram showing the circuit of FIG. 6.
  • FIG. 8 is a view showing an observed waveform in a basic matching wiring system at an observation point P1.
  • FIG. 9 is a view showing an observed waveform in a basic matching wiring system at an observation point P2.
  • FIG. 10 is a diagram showing an observation waveform at an observation point P1 in the segment division transmission system.
  • FIG. 11 is a diagram showing an observed waveform at an observation point P2 in the segment split transmission system.
  • FIG. 12 is a diagram showing an observed waveform at observation point 1 in a load trace system (conventional method).
  • FIG. 13 is a diagram showing an observed waveform at observation point 2 in a load trace system (conventional method).
  • FIG. 14 is a diagram used to explain a conventional impedance matching method (load trace method).
  • FIG. 15 is a diagram for explaining the design of a load trace for a memory module system.
  • FIG. 16 is a chart showing the results of Experiment 1.
  • FIG. 17 is a chart showing the results of Experiment 2.
  • FIG. 18 is a diagram showing a waveform at an observation point P1 of the basic matching wiring system.
  • FIG. 19 is a diagram showing a waveform at an observation point P1 in the segment split transmission system.
  • FIG. 20 is a chart showing the results of Experiment 3.
  • FIG. 21 is a diagram showing the relationship between wiring on a super-large-scale integrated circuit mounting board and reflected noise.
  • a wiring pattern constituting a transmission line for transmitting a high-frequency signal of 200 MHz or more is provided on the surface of an insulating substrate and electrically connected to the wiring pattern.
  • the wiring pattern on the high-frequency mounting substrate on which the integrated circuit to be mounted is mounted is divided into a plurality of segments SS. And each segment S—Independent characteristics for each S
  • a wave is generated.
  • these reflected waves generated at each boundary including the reflected waves generated by the capacitive load C, are superimposed on each other and are individually canceled so as to cancel each other.
  • the reflected wave does not occur!
  • the waveform distortion is reduced by the superposition.
  • each characteristic impedance ⁇ — ⁇ of the segmented transmission line is
  • the transmission line terminating resistance R and damping resistance R are also design parameters.
  • the thickness ⁇ and the insulator thickness D are generally constant (ie, ⁇ and D) for all wiring patterns on the substrate. So segment S
  • the characteristic impedance ⁇ is realized by changing the width W for each 0. Fig. 3 for high frequency mounting
  • FIG. 3 An example of a segmented transmission line for a microstrip line on a printed circuit board as a circuit board is shown.
  • the upper part shows a plan view of the wiring pattern
  • the lower part shows a cross-sectional view of each part individually.
  • the length of each segment is equal.
  • the length L of the segment may be variable, and the length may be different for each segment.
  • the length L of the segment since the propagation length of the reflected wave differs depending on the length L of each segment, the length L of the segment also needs to be determined by a genetic algorithm as a parameter similar to the characteristic impedance Z.
  • FIG. 4 shows the configuration of this system.
  • the created program for design supervision This program is called STL Designer, and this system is composed of this program and the existing electronic circuit simulator (SPICE).
  • SPICE electronic circuit simulator
  • the STL designer uses the flow control of the entire segmented transmission line (STL) design, optimization calculation by genetic algorithm, activation of the electronic circuit simulator (SPICE), and the OS [currently using Unix (registered trademark). Execute the interface with the shell.
  • the electronic circuit simulator (SPICE) has been widely used around the world since its development began in the late 1960s, and is described in "http: Z / bwrc.eecs.berkeley.edu / Classes / ⁇ cBook, SPI CEZ ”and“ Resve Saleh, Takahide Inoue and Yukihiko Ido, “Current Status and Prospects of Circuit Simulators—Implementation Issues Based on Expectations for Simulators and Overseas Research Trends” ), Vol. J74-A No. 8, PP. 1188-1196, 1991 ”[Detailed explanation! Also, many experimental results on transmission lines using an electronic circuit simulator (SPICE) have been reported so far, and their high reliability has been widely recognized.
  • the STL designer is a script written in the script language "perl”, and the electronic circuit simulator SPICE and the STL designer perform the following linked operations.
  • the STL designer performs GA calculation (genetic operation) on the parameters of the circuit model (characteristic impedance and terminating resistance of each segment of the segmented transmission line, etc.).
  • An electronic circuit simulator SPICE is used for fitness evaluation in this GA calculation (genetic operation).
  • the circuit description of the segmented transmission line including the input and output circuits is output as a file (circuit description file) in the fitness evaluation of the GA calculation.
  • the electronic circuit simulator (SPICE) reads the circuit description file, analyzes it, and outputs the analysis result as a signal waveform result file.
  • the STL designer reads the signal waveform result file, calculates fitness (fitness) from this, and continues to perform GA calculation (genetic operation).
  • the characteristic impedance (Z-Z) of the transmission line divided into segments can be directly mapped to individual genes.
  • a fitness function for fitness evaluation can be defined by “how close to an ideal transmission waveform”.
  • I (t) is an ideal propagation waveform (Ideal Wave Form) with perfect impedance matching
  • R (t) is a propagation waveform to be shaped by the method of the present invention (Wave Form Under Adjusting)
  • FIG. 5 shows the relationship between an ideal transmission waveform (Ideal Wave Form) and a transmission waveform to be shaped (Wave Form Under Adjusting).
  • Diff is equal to the absolute value of the difference between I (t) and R (t) indicated by the hatched portion in FIG.
  • a specific wiring system targeted is a clock supply wiring of a DIMM (Dual In-line Memory Module) used in a personal computer or the like.
  • Figure 6 Design The target wiring system is shown.
  • the DIMM is a memory module that is mounted on a printed circuit board and constitutes a main memory.
  • the ability to supply a wide memory bandwidth to the SCPU greatly affects system performance. Since the memory bandwidth is determined by the product of the transfer speed and the data width, it is necessary to supply a high-speed and high-quality clock signal to operate the DIMM at high speed. In order to transmit high-speed and high-quality signals on a substrate, it is necessary to realize an ideal transmission structure with less reflection.
  • the DIMM In the DIMM clock supply wiring system, the DIMM itself becomes an impedance mismatch point with respect to the transmission structure, causing waveform distortion. It is difficult for today's personal computers to supply such an ideal clock signal.
  • the clock frequency of the CPU reaches several GHz, but the performance has been improved.On the other hand, the clock signal speed on the board is several hundred MHz. It is staying at.
  • a clock signal whose clock driver (Clock Driver) power is also output passes through a damping resistor R and then is transmitted through a transmission line (see FIG. 6,
  • the characteristic impedance Z is usually about 70 ⁇ .
  • Z was set to 76 ⁇ from the measured value of the wiring system.
  • a clock signal pin (Clock In in the figure) of the DIMM is connected to this transmission line, and the clock signal is supplied to the DIMM from here.
  • the length of the transmission line was 10 cm. This length is in the range of a typical clock signal wiring length (about several cm to about 20 cm).
  • FIG. 7 shows a circuit diagram corresponding to FIG.
  • the transmission line is divided into several segments, each having a different characteristic impedance Z (in this figure, the Z force is also divided into 10 segments of Z).
  • the DIMM is equal to the load capacitance C at the position of its clock signal pin.
  • the design goal is to find the characteristic impedance Z of each segment that realizes an ideal clock signal at the clock signal input points (observation points) P1 and P2. Using a transmission line design support system.
  • FIG. 8 shows an observation waveform in the basic matching wiring system at the observation point P1
  • FIG. 9 shows an observation waveform in the basic matching wiring system at the observation point P2.
  • FIG. 10 shows an observation waveform at the observation point P1 in the segment division transmission system
  • FIG. 11 shows an observation waveform at the observation point P2 in the segment division transmission system.
  • Fig. 12 shows the observed waveform at observation point 1 in the load trace system (conventional method)
  • Fig. 13 shows the observed waveform at observation point 2 in the load trace system (conventional method).
  • the switching portion of the signal includes a high frequency component, a large reflection noise is generated due to the switching.
  • a very short rise time (20 ps) was set to evaluate the effect of the segmented transmission line on this signal switching, and the clock frequency was set as slow as 100 MHz.
  • the switching time of 20 ps is shorter than the current clock signal switching time.
  • 10 GHz class clock signals will be required in VLIS (ultra large scale integrated circuits).
  • GHz-class clock transmission is desired, which is a sufficiently realistic value to fulfill this requirement.
  • the amplitude of the signal was 3.3 [V].
  • FIG. 8 and FIG. 9 show waveforms observed at observation points P1 and P2 when a DIMM is connected to the basic matching wiring system, respectively.
  • the basic matching wiring system is an ideal transmission system with perfect impedance matching when there is no load (when a load such as a DIMM is not connected).
  • FIGS. 8 and 9 also show the waveforms (Ideal Wave Form in the figures) observed at the observation points PI and P2 when only the basic matching wiring system (no load) is used.
  • the clock signal propagates with an ideal waveform without any distortion.
  • FIG. 10 and FIG. 11 show observation waveforms at observation points PI and P2 by the segmented transmission line shown in FIG.
  • the ideal waveform (Ideal Wave Form) shown in Fig. 8 is also shown.
  • the power delay time when a slight transmission delay (Delay in the figure) and level oscillation are observed is about 200 ps (observation point P2), which is about 1Z5 of the delay time in Fig. 8.
  • almost ideal signal transmission, in which the level of vibration is large enough to cause malfunction is realized.
  • the number of GA individuals used for designing this segmented transmission line was 10, and the result of evolving about 300 generations was used.
  • the fitness value when connected is f
  • the fitness value obtained by the segmented transmission line is f
  • FIGS. 12 and 13 show the observed waveforms at the observation points PI and P2 when the load tracing method of the related art is used (ideal waveform (Ideal Wave Form) shown in FIG. 8 for comparison). Are also shown).
  • the load tracing method uses a load C connected to a transmission line (characteristic impedance Z) to locally change the characteristic impedance of the nearby wiring.
  • Table 1 shows the results of the segmented transmission line obtained by this design.
  • wire width (tran smission— line— width) W is the relational expression between characteristic impedance Z and wire shape
  • FIG. 18 shows the observed waveform (Wave Form Under Capacitance) when a DIMM is connected to the basic matching wiring system and the ideal waveform (Ideal Wave Form) when there is no DIMM. It can be seen that due to the effect of connecting the DIMM, large reflection noise is generated, and the switching part (rising and falling parts) of the rectangular wave is largely cut off and distorted like a sine waveform.
  • the characteristic impedance Z 'of the wiring is decomposed into a capacitance C' and an inductance L 'as follows.
  • t is a transmission delay time determined by the dielectric constant of the insulator of the wiring board.
  • load The characteristic impedance of the connected load trace with capacitance C can be calculated as pd L by measuring C, L, t and C, and since this value equals Z
  • the waveform distortion can be more reliably reduced as compared with the related art only by the shape of the wiring pattern without preparing a special integrated circuit or the like.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structure Of Printed Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne une nouvelle structure de câblage destinée à un substrat, pour une onde haute-fréquence, sur laquelle est montée une VLSI ou analogue. Le motif de câblage formant la ligne de transmission par l'intermédiaire de laquelle un signal haute-fréquence est transmis, est constituée d'une pluralité de segments S0 à S11 présentant différentes caractéristiques d'impédance dépendant de la différence de forme. Les impédances caractéristiques respectives Z0 à Z11 des segments sont déterminées de sorte qu'une onde de réflexion réduisant la distorsion du signal transmis par la ligne de transmission soit générée au niveau de la limite entre deux segments adjacents.
PCT/JP2004/017001 2003-11-19 2004-11-16 Structure de cablage pour onde haute-frequence, procede de fabrication de ladite structure et procede de mise en forme de forme d'onde de signal haute-frequence WO2005050733A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003390010A JP4972270B2 (ja) 2003-11-19 2003-11-19 高周波用配線構造及び高周波用配線構造の形成方法並びに高周波信号の波形整形方法
JP2003-390010 2003-11-19

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US10699056B1 (en) * 2019-01-21 2020-06-30 Samsung Electronics Co., Ltd. Computer-implemented method, processor-implemented system, and non-transitory computer-readable storage medium storing instructions for simulation of printed circuit board
CN118102600A (zh) * 2024-04-22 2024-05-28 成都光创联科技有限公司 高速光器件电路板的设计方法

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JP2007128339A (ja) * 2005-11-04 2007-05-24 Matsushita Electric Ind Co Ltd 半導体装置のパッケージ設計方法、これを実施するためのレイアウト設計ツール及びこれを用いた半導体訴追の製造方法
JP5211909B2 (ja) * 2008-07-22 2013-06-12 富士通株式会社 リードフレーム設計支援装置、リードフレーム設計支援方法およびリードフレーム設計支援プログラム
JP2011215681A (ja) * 2010-03-31 2011-10-27 Fujitsu Ltd 配線間隔検証プログラムおよび配線間隔検証装置
JP5703206B2 (ja) * 2011-12-19 2015-04-15 株式会社日立製作所 半導体装置、信号伝送システム及び信号伝送方法
JP5246899B1 (ja) * 2012-06-07 2013-07-24 国立大学法人 筑波大学 高周波用配線構造体、高周波用実装基板、高周波用配線構造体の製造方法および高周波信号の波形整形方法
JP5360786B1 (ja) * 2012-06-07 2013-12-04 国立大学法人 筑波大学 高周波用配線構造体、高周波用実装基板、高周波用配線構造体の製造方法および高周波信号の波形整形方法
JP5925352B2 (ja) * 2014-04-14 2016-05-25 キヤノン株式会社 プリント回路板及びプリント配線板
JP6267570B2 (ja) * 2014-04-23 2018-01-24 株式会社アドバンテスト 補償回路、情報処理装置、補償方法、およびプログラム
JP6357033B2 (ja) * 2014-06-30 2018-07-11 キヤノン株式会社 プリント回路板
JP2016219615A (ja) * 2015-05-21 2016-12-22 パナソニックＩｐマネジメント株式会社 プリント配線基板
CN112151087B (zh) * 2019-06-28 2023-11-24 深圳市金邦科技发展有限公司 一种阻抗变换网络及包括阻抗变换网络的内存模块

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JPH10275175A (ja) * 1997-02-03 1998-10-13 Fujitsu Ltd スペースに物を配置する配置装置および方法
JP2003134177A (ja) * 2001-10-25 2003-05-09 Nec Corp デジタル信号伝送回路の設計方法
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JPH09330350A (ja) * 1996-06-13 1997-12-22 Toshiba Corp 要素配置装置及び要素配置方法
JPH10275175A (ja) * 1997-02-03 1998-10-13 Fujitsu Ltd スペースに物を配置する配置装置および方法
JP2003134177A (ja) * 2001-10-25 2003-05-09 Nec Corp デジタル信号伝送回路の設計方法
JP2003281210A (ja) * 2002-03-26 2003-10-03 Hitachi Ltd レイアウト設計方法及びデータライブラリの提供方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10699056B1 (en) * 2019-01-21 2020-06-30 Samsung Electronics Co., Ltd. Computer-implemented method, processor-implemented system, and non-transitory computer-readable storage medium storing instructions for simulation of printed circuit board
CN118102600A (zh) * 2024-04-22 2024-05-28 成都光创联科技有限公司 高速光器件电路板的设计方法

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