WO2005034511A1 - 光検出装置 - Google Patents
光検出装置 Download PDFInfo
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- WO2005034511A1 WO2005034511A1 PCT/JP2004/014091 JP2004014091W WO2005034511A1 WO 2005034511 A1 WO2005034511 A1 WO 2005034511A1 JP 2004014091 W JP2004014091 W JP 2004014091W WO 2005034511 A1 WO2005034511 A1 WO 2005034511A1
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- 230000003071 parasitic effect Effects 0.000 claims abstract description 55
- 238000007599 discharging Methods 0.000 claims abstract description 15
- 238000006243 chemical reaction Methods 0.000 claims description 65
- 230000006835 compression Effects 0.000 claims description 22
- 238000007906 compression Methods 0.000 claims description 22
- 239000004065 semiconductor Substances 0.000 claims description 18
- 230000003321 amplification Effects 0.000 claims description 10
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 10
- 238000005513 bias potential Methods 0.000 claims description 9
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000004148 unit process Methods 0.000 claims description 7
- 230000035945 sensitivity Effects 0.000 abstract description 24
- 238000001514 detection method Methods 0.000 abstract description 21
- 229920006395 saturated elastomer Polymers 0.000 description 35
- 238000010586 diagram Methods 0.000 description 30
- 230000010354 integration Effects 0.000 description 29
- 238000003384 imaging method Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 230000000903 blocking effect Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 2
- 101000837456 Homo sapiens Transducin beta-like protein 3 Proteins 0.000 description 1
- 102100028683 Transducin beta-like protein 3 Human genes 0.000 description 1
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- 235000009508 confectionery Nutrition 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/70—Circuitry for compensating brightness variation in the scene
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/571—Control of the dynamic range involving a non-linear response
- H04N25/573—Control of the dynamic range involving a non-linear response the logarithmic type
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/571—Control of the dynamic range involving a non-linear response
- H04N25/575—Control of the dynamic range involving a non-linear response with a response composed of multiple slopes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
Definitions
- the present invention relates to a photodetector having an active pixel type pixel section including a photodiode.
- the active pixel type photodetector has an active pixel type pixel unit that includes a photodiode that generates an amount of electric charge according to the intensity of incident light. This charge-to-voltage conversion is performed through a source follower circuit that also has transistor power, and photodetection can be performed with high sensitivity and low noise.
- the output voltage value V has an upper limit of about several volts due to limitations of a usable power supply voltage range and circuit systems. For this reason, there is also an upper limit on the amount Q of charge that can be stored in the parasitic capacitance portion.
- Patent document 1 JP-A-11-274454
- the inventors have studied the conventional photodetector in detail and found the following problem.
- the conventional photodetector can perform photodetection with high sensitivity, there is a problem that the dynamic range of photodetection is narrow due to the restriction of the saturation charge amount.o
- the present invention has been made to solve the above-described problems, and provides a photodetector having a structure capable of performing photodetection with high sensitivity and a wide dynamic range. It is an object.
- the photodetector includes: (1) a photodiode that generates an amount of charge according to the intensity of incident light; and a photodiode that generates an amount of charge in accordance with the amount of charge stored in a parasitic capacitance portion formed at a gate terminal.
- Amplifying transistor that outputs the voltage value
- a transfer transistor that transfers the charge generated by the photodiode to the gate terminal of the amplifying transistor
- a discharging transistor that initializes the charge of the parasitic capacitance
- an amplifying transistor A pixel section including a selection transistor for selectively outputting an output voltage value;
- a first pixel data reading unit that reads a voltage value output from the selection transistor in the pixel unit and outputs a first voltage value corresponding to the voltage value; and (3) a discharge transistor connected to the pixel unit.
- the input terminal is connected to the third terminal of the connection switching unit, and the capacitance value is larger than the capacitance value of the parasitic capacitance unit.
- the second pixel data that includes a capacitive element having a capacitance, stores the charge flowing into the input terminal from the third terminal of the connection switching unit in the capacitive element, and outputs a second voltage value corresponding to the amount of the accumulated charge.
- a reading unit that includes a capacitive element having a capacitance, stores the charge flowing into the input terminal from the third terminal of the connection switching unit in the capacitive element, and outputs a second voltage value corresponding to the amount of the accumulated charge.
- the pixel output is output via the amplifying transistor and the selection transistor.
- the data is read by the data reading unit.
- a first voltage value corresponding to the read voltage value is output to the first pixel data reading unit.
- This first voltage value is a result of detecting the incident light intensity with high sensitivity when the parasitic capacitance portion of the pixel portion is not saturated, that is, when the intensity of the light incident on the pixel portion is relatively small. Is represented with high precision.
- the charge generated by the photodiode included in the pixel portion is output to the pixel portion via a discharging transistor, and is input to the second pixel data reading portion via connection switching means.
- the inflowing charge is accumulated in the capacitive element, and a second voltage value corresponding to the amount of the accumulated charge is output.
- the capacitance value of the capacitance element included in the second pixel data reading unit is larger than the capacitance value of the parasitic capacitance unit included in the pixel unit. From this, this second voltage value was detected when the parasitic capacitance portion of the pixel portion was saturated, that is, when the intensity of the light incident on the pixel portion was relatively large. Express results with high precision.
- the capacitance value of the capacitance element included in the second pixel data readout unit is 2 K times (where ⁇ is an integer of 1 or more) of the capacitance value of the parasitic capacitance unit. .
- the second voltage value to which the second pixel data reading section power is also output is equal to the first voltage value output from the first pixel data reading section. It can be 2 ⁇ times. Then, for example, it is determined whether or not the parasitic capacitance portion of the pixel portion is saturated, selection of any one of the first voltage value and the second voltage value, and selection of the first voltage value and the second voltage value. Post-processing such as AZD conversion of both or any one becomes easy.
- the photodiode included in the pixel portion has the second semiconductor region of the second conductivity type on the first semiconductor region of the first conductivity type, and the second semiconductor region A third semiconductor region of the first conductivity type is formed thereon, and the first semiconductor region and the second semiconductor region form a ⁇ junction, and the second semiconductor region and the third semiconductor region form a ⁇ junction. It is preferable that As described above, when the photodiode is a buried type, light detection with higher sensitivity can be performed.
- One of the first conductivity type and the second conductivity type is ⁇ type. Means P-type.
- the pixel portion further includes a blocking transistor provided between the photodiode and the transfer transistor and used in a saturation region. Also in this case, light detection with higher sensitivity can be performed.
- the second pixel data readout unit may have one capacitance element for all of the two-dimensionally arranged pixel parts, but has one capacitance element for each column. Is preferred. In the latter case, the charges generated in the photodiodes included in each pixel unit in one row are simultaneously output through the discharge transistors of the pixel unit, and are output through the connection switching means to the second pixel data readout unit. , And stored in a corresponding capacitive element provided for each column. Therefore, high-speed imaging can be performed.
- the second pixel data readout unit processes the output charge from the pixel unit in the row. It is suitable. Alternatively, it is preferable that the second pixel data readout unit processes the output charges of the pixel units in the other rows while the first pixel data readout unit processes the output voltage value from the pixel units in a certain row. is there. As described above, when the first pixel data readout unit and the second pixel data readout unit operate in parallel, imaging can be performed without lowering the frame rate.
- the photodetector inputs a first voltage value from which a first pixel data readout unit output is also output, performs AZD conversion, and outputs a first digital value according to the first voltage value.
- the second pixel data readout unit preferably further includes an AZD conversion unit that inputs the output second voltage value, performs AZD conversion, and outputs a second digital value according to the second voltage value.
- the first digital value and the second digital value output from the AZD converter are input, and any one of the first voltage value, the second voltage value, the first digital value, and the second digital value is set as the reference value. It is preferable to further include a selection output unit that selects and outputs one of the first digital value and the second digital value based on a result of comparing the magnitudes of the first and second digital values.
- the first voltage value output from the first pixel data readout unit is AZD-converted by the AZD conversion unit, and a first digital value corresponding to the first voltage value is output.
- the second voltage value output by the two-pixel data readout unit The output voltage is subjected to SAZD conversion, and a second digital value corresponding to the second voltage value is output. Then, based on the result of comparing the reference value with any one of the first voltage value, the second voltage value, the first digital value, and the second digital value, the first digital value and the second digital value are output by the selection output unit. One of the two digital values is selected and output.
- the photodetector according to the present invention may include a first voltage value output from the first pixel data readout unit and a second voltage value output from the second pixel data readout unit.
- the apparatus further includes a selection output unit that selects and outputs one of the first voltage value and the second voltage value based on a result of comparing the magnitude of any one of the voltage value and the second voltage value with the reference value. Is preferred. Further, it is preferable to further include an AZD conversion unit that inputs the voltage value output from the selection output unit, performs AZD conversion, and outputs a digital value corresponding to the voltage value.
- the selection output unit determines the first voltage value and the second voltage value based on the result of comparing one of the first voltage value and the second voltage value with the reference value. One of them is selected and output. Then, the voltage value output from the selection output unit is AZD-converted by the AZD conversion unit, and a digital value corresponding to this voltage value is output.
- the second pixel data readout unit further includes a logarithmic compression circuit provided in parallel with the capacitor, and the second pixel data readout unit flows into the input terminal from the third terminal of the connection switching unit. It is preferable that the input electric charge be input to a logarithmic compression circuit, and a third voltage value corresponding to the logarithmic value of the inflow amount of the input electric charge be output.
- the second pixel data readout unit does not only output the second voltage value corresponding to the amount of charge generated in the photodiode included in the pixel unit, but also controls the amount of inflow of the charge.
- a third voltage value according to the numerical value is output from the logarithmic compression circuit. Therefore, based on the first voltage value output from the first pixel data readout unit and the second voltage value and the third voltage value output from the second pixel data readout unit, light with high sensitivity and a wider dynamic range is obtained. Can be detected.
- the first voltage value output from the first pixel data readout unit is input and subjected to AZD conversion. 1 While outputting the first digital value corresponding to the voltage value, inputting the second voltage value and the third voltage value output from the second pixel data readout unit and performing AZD conversion, 2nd digital value And an AZD conversion unit that outputs a third digital value corresponding to the third voltage value. Also, the first digital value, the second digital value, and the third digital value output from the AZD conversion unit are input, and the first voltage value, the second voltage value, the third voltage value, the first digital value, and the second digital value are input.
- any one of the first digital value, the second digital value, and the third digital value based on a result of comparing the magnitude of the reference value with any one of the first digital value and the third digital value. It is preferable to further include a selection output unit for outputting.
- the first voltage value output from the first pixel data reading unit and the second voltage value and the third voltage value output from the second pixel data reading unit are input, and the first voltage value (2) Select one of the first, second, and third voltage values based on the result of comparing the magnitude of any one of the voltage value and the third voltage value with the reference value. It is preferable to further include a selection output unit that outputs the data. Further, it is preferable to further include an AZD conversion unit that inputs a voltage value output from the selection output unit, performs AZD conversion, and outputs a digital value corresponding to the voltage value.
- FIG. 1 is a diagram showing a schematic configuration of a first embodiment of a photodetector according to the present invention.
- FIG. 2 is a diagram illustrating a configuration of a light detection unit in the light detection device according to the first embodiment.
- FIG. 3 is a diagram illustrating a configuration of a first pixel data reading unit in the photodetector according to the first embodiment.
- FIG. 4 is a circuit diagram of each of a pixel unit P, a voltage holding unit H, and switches m and n n in the photodetector according to the first embodiment.
- FIG. 5 is a diagram showing a configuration of a second pixel data reading unit in the photodetector according to the first embodiment.
- FIG. 6 is a circuit diagram of each of a pixel unit P, an integrating circuit 31, and a switch m, n n switch sw in the photodetector according to the first embodiment.
- FIG. 7 is a diagram illustrating a configuration example of a data output unit in the photodetector according to the first embodiment.
- FIG. 8 is a diagram showing another configuration example of the data output unit in the photodetector according to the first embodiment.
- FIG. 9 is a diagram showing a cross-sectional structure of a pixel unit P in the photodetector according to the first example, where m, n
- FIG. 10 is a circuit m, n showing another configuration of the pixel unit P in the photodetector according to the first embodiment.
- FIG. 1 A first figure.
- FIG. 11 is a timing chart for explaining an operation example of the photodetector according to the first embodiment.
- FIG. 12 is a diagram showing a schematic configuration of a second embodiment of the photodetector according to the present invention.
- FIG. 13 is a diagram illustrating a configuration of a second pixel data reading unit in the photodetector according to the second embodiment.
- FIG. 14 is a circuit diagram of each of a pixel unit P, an integration circuit 31, a logarithmic m, nn compression circuit 32, and a switch SW in the photodetector according to the second embodiment.
- FIG. 16 is a diagram showing another configuration example of the data output unit in the photodetector according to the second embodiment.
- FIG. 17 is a timing chart for explaining an operation example of the photodetector according to the second embodiment.
- each of M and N is an integer of 2 or more, and unless otherwise specified, m is any integer of 1 to M, and n is any integer of 1 to N.
- FIG. 1 is a schematic configuration diagram of a photodetector 1 according to the first embodiment.
- FIG. 2 is a configuration diagram of the light detection unit 10 of the light detection device 1 according to the first embodiment.
- the light detecting device 1 shown in these figures has a light detecting unit 10, a first pixel data reading unit 20, a second pixel data reading unit 30, a data output unit 40, a timing control unit 50, and a switch SW-SW. . These are the common half
- the timing control section 50 controls the entire operation of the photodetector 1, but may be divided into a plurality of portions and arranged on a substrate so as to be separated from each other.
- the light detection unit 10 has M ⁇ N pixel units P two-dimensionally arranged in M rows and N columns.
- the pixel section P is located at the m-th row and the n-th column.
- Each pixel unit P has a common configuration
- Each wire L is connected to M in the n-th column.
- the pixel units ⁇ and ⁇ are commonly connected to their output terminals.
- the first pixel data readout unit 20 includes two lines L
- the first voltage value V representing the data is sequentially output. Each voltage value V enters the pixel section P.
- the first voltage value V is close to the pixel portion P.
- a charge is input, the charge is stored in a capacitor, and a second voltage value V according to the amount of charge stored in the capacitor is sequentially output.
- a second voltage value V is sequentially output.
- the capacitance value of the capacitance element is larger than the capacitance value of the parasitic capacitance portion included in the pixel portion P.
- Each voltage value V is a value corresponding to the intensity of light incident on the pixel portion P. Also, this
- the voltage value V is determined when the parasitic capacitance of the pixel portion P is saturated, that is, the pixel portion P
- the data output unit 40 includes a first voltage value V output from the first pixel data readout unit 20,
- the second voltage value V output from the second pixel data readout unit 30 is input, and predetermined processing is performed.
- Each digital value D corresponds to the first voltage value V and the
- One of the voltage values V is the value resulting from the AZD conversion and is incident on the pixel part P.
- m, nm Represents the intensity of the m, n light.
- the timing control unit 50 generates various control signals at a predetermined timing by, for example, a shift register circuit, and transmits these control signals to the light detection unit 10, the first pixel data reading unit 20, and the second pixel data reading unit 30. , Data output unit 40 and switch SW-SW
- wiring for transmitting a control signal is partially omitted.
- FIG. 3 is a configuration diagram of the first pixel data reading unit 20 of the photodetector 1 according to the first embodiment.
- the first pixel data reading unit 20 includes N voltage holding units H—H and two voltage follower circuits.
- Each voltage holding unit H has a common configuration.
- the voltage value output to line L can be input and held, and the
- the pressure value can be output. ⁇ ⁇ voltage holding parts ⁇ — ⁇
- Each of the two voltage follower circuits F 1 and F 2 has a common configuration
- the input and output terminals are directly connected to each other, Ideally, it is an amplifier circuit with a gain of 1 and a low output impedance.
- the voltage follower circuit F is configured such that the N voltage holding units H—H also output forces sequentially.
- the other voltage follower circuit F non-inverts the other voltage value V sequentially output from each of the N ⁇ , ⁇ 2 voltage holding units ⁇ — ⁇
- the subtraction circuit S has an amplifier and four resistors R-R. Amplifier inverting input
- the terminal is connected to the output terminal of the voltage follower circuit F via a resistor R.
- FIG. 4 shows the pixel unit ⁇ , the voltage holding unit ⁇ , and the switches m, n n of the photodetector 1 according to the first embodiment.
- Each pixel unit P includes a photodiode PD that generates an amount of electric charge according to the intensity of incident light,
- Amplifying transistor T which outputs a voltage value corresponding to the amount of charge stored in the parasitic capacitance formed at the gate terminal, and transfer of the charge generated by the photodiode PD to the gate terminal of the amplifying transistor T.
- the photodiode PD has its anode terminal at the ground potential.
- the amplifying transistor has a parasitic capacitance portion formed at its gate terminal and its drain terminal at a bias potential.
- the transfer transistor ⁇ has its drain terminal connected to an amplification transistor.
- the source terminal is connected to the power source terminal of the photodiode PD.
- the discharge transistor ⁇ has its source terminal connected to the amplification transistor ⁇ .
- the source terminal of the transistor T is connected to the source terminal of the amplifying transistor ⁇ ,
- the drain terminal is connected to the wiring L.
- a constant current source is connected to this line L.
- the constant current source may be provided to be connected to the wiring L for each column. Also, for example,
- a switch may be provided between each wiring L and the first pixel data readout unit 20 so that these switches are provided.
- only one constant current source may be provided on the wiring between these switches and the first pixel data readout unit 20.
- the transfer transistor T inputs a transfer control signal S to its gate terminal, and
- the discharge transistor T inputs the m-th row discharge control signal S to its gate terminal, and discharges the m-th row.
- the selection transistor T has an m-th
- the row selection control signal S is input, and the m-th row selection control signal S
- the voltage value output from the amplifying transistor T to the external wiring L is the voltage value output from the amplifying transistor T to the external wiring L.
- Each pixel unit ⁇ ⁇ ⁇ ⁇ configured in this manner is provided with a transfer control signal S
- n trans is at one level, the m-th row discharge control signal S goes high, and the bias potential V goes through the switch SW.
- the voltage value (dark signal component) output from the amplifying transistor ⁇ in the initialized state is output to the wiring L via the selection transistor ⁇ .
- the charge generated by the photodiode PD is input to the gate terminal of the amplifying transistor T, and the voltage value (bright signal component) output from the amplifying transistor T is changed according to the amount of the charge.
- the signal is output to the wiring L via the selection transistor T.
- the voltage holding unit H includes a first holding unit H and a second holding unit H.
- Each of the first holding unit H and ⁇ ⁇ ,, ⁇ , 2 ⁇ , and the second holding unit ⁇ ⁇ has the same configuration as each other, and ⁇ pixels ⁇ , 2 in the ⁇ -th column
- the stored voltage value can be output.
- the first holding unit ⁇ ⁇ includes a transistor ⁇ , a transistor ⁇ , and a capacitor C. Capacity ⁇ , ⁇ 11 12 1
- the source terminal is connected to the selection transistor ⁇ in the pixel section ⁇ ⁇ via the wiring L
- the drain terminal of the transistor T is connected to the voltage follower circuit F. in this way
- the first holding unit configured has a first input control ⁇ , ⁇ 11 input to the gate terminal of the transistor ⁇ .
- the second holding unit ⁇ ⁇ includes a transistor ⁇ , a transistor ⁇ , and a capacitor C. Capacity ⁇ , 2 21 22 2
- One end of the element C is set to the ground potential, and the other end of the capacitive element C is connected to the drain of the transistor ⁇ .
- the source terminal is connected to the selection transistor ⁇ in the pixel section ⁇ via the wiring L
- the drain terminal of the transistor T is connected to the voltage follower circuit F. in this way
- the second holding unit ⁇ configured has a second input control ⁇ , 2 21 input to the gate terminal of the transistor ⁇ .
- Each of the first holding unit H and the second holding unit H operates at a different timing from each other.
- the first holding unit n has n, ll, nm, n and a transfer control signal S at one level in the pixel unit ⁇ ⁇ connected via the wiring L, and outputs the m-th row discharge control signal S and the m-th Row trans reset, m
- the amplifying transistor T When the selection control signal S is at a low level or a high level, the amplifying transistor T also outputs select, m 1 Input and hold the input voltage value (dark signal component) V. On the other hand, the second holding portion H
- the first input control signal S, the second input control signal S, and the n-th column output control signal S s elect, m input, 1 input, 2
- FIG. 5 is a configuration diagram of the second pixel data reading unit 30 of the photodetector 1 according to the first embodiment.
- the second pixel data readout unit 30 includes N integration circuits 31-31 and N switch SWs.
- Each of the integrating circuits 31 has a common configuration, has a capacitive element for accumulating the electric charge flowing into the input terminal from the switch SW, and outputs a voltage value corresponding to the amount of electric charge accumulated in this capacitive element to the switch SW. Output to The second pixel data readout unit 30
- FIG. 6 shows the pixel section P, the integration circuit 31 and the switch S of the photodetector 1 according to the first embodiment.
- Circuit 31 and one switch SW are shown as representative.
- Each integration circuit 31 has an amplifier A, a capacitance element C, and a switch SW.
- Each of the capacitive element C and the switch SW is provided in parallel between the input terminal and the output terminal of the amplifier A.
- the capacitance of the capacitor C is determined by the gain of the amplifying transistor T in the pixel portion P.
- the integration circuit 31 initializes the capacitive element C when the switch SW is closed. When the switch SW is open, the integration circuit 31
- the charge flowing into the input terminal is stored in the capacitor c, and the charge stored in the capacitor c is Outputs the voltage value corresponding to the amount to the switch SW.
- control signals for controlling the opening and closing operations of the switches SW, SW, and SW are as follows.
- the switch SW is not electrically connected between the first terminal and the second terminal and between the first terminal and the third terminal.
- FIG. 7 is a diagram showing one configuration example of the data output unit 40 of the photodetector 1 according to the first embodiment.
- the data output section 40 shown in this figure is composed of AZD conversion circuits 41 and 41 and selective output.
- the AZD conversion circuit 41 receives the first voltage value V output from the first pixel data reading unit 20 and performs AZD conversion on the first voltage value V.
- the AZD conversion circuit 41 outputs l, m, n 2 output from the second pixel data readout unit 30.
- AZD conversion is performed by inputting the second voltage value V, and the second digital value corresponding to the second voltage value V
- the capacitance value of the capacitance element C of each integration circuit 31 is equal to the capacitance of the parasitic capacitance part of the pixel part P.
- a first digital value of the input voltage value is a certain value V der Rutoki to AZD conversion circuit 41, the input voltage value to the AZD conversion circuit 41 VZ2 K
- the second digital value is equal to each other.
- the selection output unit 42 receives the first digital value D and the second digital value D,
- the first digital value D and the reference value are not compared in magnitude, and the second digital value l, m, n
- m, nl, m, n2 may be compared with the reference value.
- the reference value is set to a value that can determine whether or not the force of the parasitic capacitance section of the pixel section P m, nm, n is saturated.
- the AZD conversion result of the first voltage value V) is output as a digital value D from the data output unit 40 as l, m, nm, n, so that photodetection with high sensitivity is possible.
- FIG. 8 is a diagram illustrating another configuration example of the data output unit 40 of the photodetector 1 according to the first embodiment.
- the data output unit 40 shown in this figure has a selection output unit 43 and an AZD conversion circuit 44.
- the selection output unit 43 is configured to output the first voltage value output from the first pixel data reading unit 20.
- V and the second voltage value V output from the second pixel data reading unit 30 are input, and the first voltages l, m, n 2, m, n
- One of the pressure values V is selected and output.
- the reference value is set to a saturation value of the first voltage value output from the first pixel data reading unit 20, or a value slightly smaller than the saturation value. That is, by comparing the first voltage value V with the reference l, m, n values, it is determined whether the parasitic capacitance portion of the pixel portion P is saturated m, n
- the selection output section 43 outputs the l, m, n
- the AZD conversion circuit 44 inputs the voltage value output from the selection output unit 43, performs AZD conversion, and outputs a digital value D according to the voltage value.
- the capacitance value of nn child C is 2 K times the capacitance value of the parasitic capacitance of the pixel portion P, A m, n
- the digital value obtained by the AZD conversion is output as a digital value D m, n, while the second voltage value V output from the second pixel data reading unit 30 is output.
- the discharging transistor T of the pixel section P is also output, and is read by the second pixel data 30.
- the AZD conversion result of the obtained second voltage value V is converted into a digital value D from the data output unit 40.
- the photodetector 1 can perform imaging with high sensitivity and a wide dynamic range.
- FIG. 9 is a configuration diagram of the pixel unit P of the photodetector 1 according to the first embodiment.
- m, n are the pixel unit P of the photodetector 1 according to the first embodiment.
- the photodiode PD and the transfer transistor T are cross-sectional views of the semiconductor.
- the photodiode PD is of a buried type, and includes a p region 101, an n-region 102 above the p region 101, and a p + region 103 above the n region 102. And is comprised.
- the p region 101 and the n ⁇ region 102 form a pn junction, and the n region 102 and the p + region 103 form a pn junction. Further, a part of the n region 102 reaches the semiconductor surface.
- the transfer transistor T is composed of an n region 104 on the p region 101 and a semiconductor
- the n region 104 is electrically connected to the gate terminal of the amplifying transistor T1, and is electrically connected to the source terminal of the discharging transistor T3.
- the p region 101 and the n region 104 form a pn junction, and the pixels m, n
- the photodiode PD when the photodiode PD is of a buried type, generation of a leak current is suppressed.
- the n- region 102 is completely depleted at the pn junction of the photodiode PD. Since the junction capacitance value of the photodiode PD can be made almost zero, the charge generated in the photodiode PD can be almost completely transferred to the parasitic capacitance portion. Therefore, when the photodiode PD is of a buried type, it is effective for improving the SZN ratio and increasing the sensitivity of light detection.
- FIG. 10 is a circuit diagram showing another configuration of the pixel unit P of the photodetector 1 according to the first embodiment.
- the pixel portion P shown in this figure has blocking m, n in addition to the configuration shown in FIGS. 4 and 6.
- FIG. 11 is a timing chart illustrating an operation example of the photodetector 1 according to the first embodiment. This figure shows the time l, n2, ⁇ for reading the data of each pixel unit P in the first row and each pixel unit P in the second row.
- the discharge control signal S changes to a high level at time t
- a bias potential V is supplied to each pixel portion P from 10 n 10 to time t.
- the second input control signal S is a constant input, 2 from time t to time t when the transfer control signal S is at a high level.
- the first voltage value V according to the light intensity is output from the first pixel data reading unit 20.
- the first voltage value V — V according to the intensity of the light incident thereon is sequentially output from the first pixel data reading unit 20. Note that the level of each voltage value V output during this period is
- This level corresponds to the intensity of light incident on the element ⁇ , and generally varies depending on the ⁇ value. That
- the transfer control signal S changes to high level at time t after time t, and changes to low level at time t after time t.
- the second row selection control signal S changes to high level at time t.
- the switch SW select, 220 n supplies the bias potential V to each pixel unit P from time t to time t.
- the second input control signal S is a constant input, 2 from time t to time t when the transfer control signal S is at a high level.
- the dark signal component and the bright signal component of the pixel unit P are output from the voltage holding unit H, and
- the difference between the signal component and the bright signal component is obtained by the subtraction circuit S and is incident on the pixel portion P.
- a first voltage value V corresponding to the intensity of the 2, n light is output from the first pixel data reading unit 20. This l, 2, n
- This level corresponds to the intensity of light incident on the element P, and generally varies depending on the n value. That
- the data m, n of the pixel portion P of each row is sequentially read out by the first pixel data reading portion 20.
- the first pixel data readout unit 20 sequentially enters the N pixel units P—P of each row for each of the first row and the Mth row, and m, lm, N
- the first voltage value V — V according to the intensity of the light is output sequentially. Also, the first stroke l, m, l l, m, N
- the second pixel data l, m, n In parallel with the reading of the first voltage value V by the raw data reading unit 20, the second pixel data l, m, n
- the reading of the second voltage value V by the reading unit 30 is performed as follows.
- the second pixel data reading unit 30 operates as follows. Period from time t to time t
- each switch SW 14 14 14, ⁇ is sequentially closed for a certain period of time. While the switch SW is closed, the integration circuit
- the second voltage value V according to the amount of charge stored in the capacitive element C of the second pixel 31 is equal to the second pixel data ⁇ 2,1, ⁇
- the second voltage value V according to the intensity of light incident on each of the N pixel units P — P in the row
- the second input control signal S is at a high level during the period from time t to time t
- each switch SW is closed, and the electric charge accumulated in the capacitance portion n2, n of the pixel portion P in the second row is moved to the capacitance element C of the integration circuit 31. From time t or n 24 to time t, each switch SW is sequentially closed for a certain period.
- the second voltage value V according to the amount is output from the second pixel data reading unit 30. Like this
- the second voltage value V—V according to the intensity of the emitted light is sequentially changed from the second pixel data readout unit 30.
- the m and n data are read out.
- the second pixel data readout unit 30 sequentially enters each of the N pixel units P—P in each row for each of the first row and the Mth row.
- the second voltage value V — V according to the light intensity is output sequentially.
- the data output unit 40 operates as follows. Period from time t to time t
- the voltage value V is sequentially input to the data output unit 40, and the second pixel data readout unit 3
- the second voltage value V of the pixel unit ⁇ of the first row read by 0 is output as data
- the first voltage value V or the second voltage value V is converted to AZD
- the resulting digital values D are sequentially output from the data output unit 40.
- the first pixel data reading unit 20 reads
- the first voltage value V of the pixel unit P in the second row is sequentially sent to the data output unit 40.
- the second voltage value V for 2, n is sequentially input to the data output unit 40, and the first voltage value V
- the second pixel data reading unit 30 It was to process the output charge from the pixel unit P or m, n in the row. However, during the period when the first pixel data reading unit 20 processes the output voltage value from the pixel unit P in a certain row, the second pixel data reading unit 30
- the second pixel data readout unit 30A outputs not only the second voltage value V but also the third voltage value V to the data output unit 40A.
- n m, n 3 is n m, n with respect to the amount of charge generated in the photodiode PD in the pixel portion P.
- the logarithmic compression circuit 32 is provided in parallel with the capacitive element C of the integration circuit 31.
- the logarithmic compression circuit 32 has a transistor T and a switch SW. The source terminal of transistor T is connected to switch S
- the logarithmic compression circuit 32 can input the electric charge flowing from the switch SW and output a third voltage value V according to the logarithmic value of the amount of the input electric charge.
- the row discharge control signal S is also at a low level.
- the switch SW connects the wiring L to the input terminal of the reset, mn 2, n width unit A, and the switch SW in the integration circuit 3 l n is opened, and the logarithmic compression circuit 32 is opened. Switch SW is closed.
- the inflow amount (that is, current) of the charge flowing into the logarithmic compression circuit 32 due to the incidence of light on the n 32 m, n photodiode PD in the pixel portion P is Ish
- the output from the logarithmic compression circuit 32 is The obtained third voltage value V n 3, m, n is represented by the following equation (1).
- k is the Boltzmann constant
- T is the absolute temperature
- q is the charge of the electron
- I is a constant.
- V (kT / q) ln (Ish / l)
- the output unit 30A transmits the second voltage value V and the third voltage value V to the data output unit 40A in common.
- FIG. 15 is a diagram showing one configuration example of the data output unit 40A of the photodetector 2 according to the second embodiment.
- the data output section 40A shown in this figure has substantially the same configuration as that shown in FIG. 7, and includes AZD conversion circuits 41, 41 and a selection output section.
- the second implementation includes AZD conversion circuits 41, 41 and a selection output section.
- the second digital value D or the third l, m, n 2, m, n digital value D may be compared with the reference value.
- I is a first reference value that can determine whether the parasitic capacitance portion of the pixel portion P is saturated or not, m, n
- the first digital value D (that is, Part P l, m, n
- the first transistor which is output and read out by the first pixel data 20 is selected.
- the AZD conversion result of the voltage value V) is output as a digital value D from the data output unit 40A as l, m, nm, n, so that photodetection with high sensitivity is possible.
- the second digital value D that is, the output of the discharge transistor T of the pixel portion P is output and the second pixel data
- the third digital value D that is, the output of the discharge transistor T of the pixel portion P
- the photodetector 2 according to the second embodiment can perform imaging with high sensitivity and a wider dynamic range.
- the second voltage value V or the third voltage value V may be compared with the reference value.
- the second pixel data 30A is output from the discharging transistor T of the pixel portion P and read out by the logarithmic compression circuit 32 m, n 3 n of the second pixel data 30A.
- the AZD conversion result of the voltage value V is
- FIG. 17 is a timing chart illustrating an operation example of the photodetector 2 according to the second embodiment. This figure shows a time range in which data of each pixel unit P in the first row is read. Shown in Figure 11
- the timing chart of the second embodiment shown in FIG. 17 shows that the switch SW of each logarithmic compression circuit 32 follows the opening and closing of the switch SW of each integration circuit 31.
- the switch SW is closed, and the charges generated by the photodiode PD of the pixel unit P in the first row are transferred to each pair ⁇ ⁇ , ⁇
- each of the switches SW n 17 18 1 is sequentially closed for a certain period. While the switch SW is closed, the logarithm
- the third voltage value V according to the logarithmic value of the amount of electric charge flowing into the compression circuit 32 is equal to the second pixel data ⁇ 3,1, ⁇
- the third pixel corresponding to the logarithmic value of the intensity of light incident on each of the N pixel units P — P in one row
- the voltage values V -V are sequentially output from the second pixel data readout unit 30 #.
- the data output unit 40 # reads the first pixel data from time t to time t.
- ⁇ ⁇ ⁇ ⁇ , ⁇ ⁇ , ⁇ , ⁇ 2, 1, ⁇ 3, 1, ⁇ are digital values D, which are the result of AZD conversion, are sequentially output from the data output unit 40A.
- the timing at which the third voltage value V is output depends on the first voltage value V and the third voltage value V.
- the data holding unit that holds 2,1, ⁇ 1,1 and the second voltage value V (or their AZD conversion result)
- the digital value D — D according to the intensity of light incident on each of the ⁇ pixel units ⁇ — ⁇ of each row is sequentially obtained for each of the first row and the first ⁇ row.
- lm, N m, lm, N Output sequentially from the output unit 40A.
- the parasitic capacitance of the pixel portion P is saturated m, n
- the result of the AZD conversion of the pressure value V is output as a digital value D.
- Pixel l, m, nm, n When the parasitic capacitance part of the part P is saturated, the capacitance element of the integration circuit 31 is saturated m, nn
- the device 2 can detect the incident light intensity with high sensitivity and a wider dynamic range.
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04788187.5A EP1677522B1 (en) | 2003-10-02 | 2004-09-27 | Photo detecting apparatus |
US10/574,104 US7800667B2 (en) | 2003-10-02 | 2004-09-27 | Photo-detecting apparatus |
KR1020067006154A KR101074551B1 (ko) | 2003-10-02 | 2004-09-27 | 광검출 장치 |
Applications Claiming Priority (2)
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JP2003-344895 | 2003-10-02 | ||
JP2003344895A JP4268492B2 (ja) | 2003-10-02 | 2003-10-02 | 光検出装置 |
Publications (1)
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WO2005034511A1 true WO2005034511A1 (ja) | 2005-04-14 |
Family
ID=34419401
Family Applications (1)
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PCT/JP2004/014091 WO2005034511A1 (ja) | 2003-10-02 | 2004-09-27 | 光検出装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US7800667B2 (ja) |
EP (1) | EP1677522B1 (ja) |
JP (1) | JP4268492B2 (ja) |
KR (1) | KR101074551B1 (ja) |
CN (1) | CN100401751C (ja) |
WO (1) | WO2005034511A1 (ja) |
Cited By (2)
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WO2006022163A1 (ja) * | 2004-08-26 | 2006-03-02 | Hamamatsu Photonics K.K. | 光検出装置 |
WO2007085942A2 (en) * | 2006-01-25 | 2007-08-02 | Melexis Nv | Image sensor with a photodiode readout circuit |
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JP4421353B2 (ja) * | 2004-04-01 | 2010-02-24 | 浜松ホトニクス株式会社 | 固体撮像装置 |
JP5269286B2 (ja) * | 2005-07-12 | 2013-08-21 | 浜松ホトニクス株式会社 | 光検出回路 |
JP4747781B2 (ja) | 2005-10-27 | 2011-08-17 | 船井電機株式会社 | 撮像装置 |
JP4683436B2 (ja) * | 2006-02-02 | 2011-05-18 | 国立大学法人 奈良先端科学技術大学院大学 | 光検出装置 |
JP4762030B2 (ja) * | 2006-03-31 | 2011-08-31 | 三洋電機株式会社 | 光検出装置 |
US7969490B2 (en) | 2006-08-25 | 2011-06-28 | Micron Technology, Inc. | Method, apparatus, and system providing an imager with pixels having extended dynamic range |
KR100808014B1 (ko) * | 2006-09-11 | 2008-02-28 | (주)실리콘화일 | 3개의 트랜지스터를 구비하는 단위픽셀 및 이를 구비하는픽셀 어레이 |
JP4825116B2 (ja) * | 2006-11-22 | 2011-11-30 | 浜松ホトニクス株式会社 | 固体撮像装置及び撮像方法 |
FR2929055B1 (fr) * | 2008-03-19 | 2010-05-28 | Commissariat Energie Atomique | Systeme de conversion de charges en tension et procede de pilotage d'un tel systeme |
US9131142B2 (en) | 2009-07-17 | 2015-09-08 | Nikon Corporation | Focusing device and camera |
FR2983296B1 (fr) * | 2011-11-29 | 2013-12-27 | Soc Fr Detecteurs Infrarouges Sofradir | Dispositif de detection de rayonnement a etendue d'illumination amelioree |
US9752929B2 (en) * | 2014-05-08 | 2017-09-05 | Pinnacle Imaging Corporation | Light-detecting device and method for converting optical radiation on switched conductivity diodes |
US9526468B2 (en) | 2014-09-09 | 2016-12-27 | General Electric Company | Multiple frame acquisition for exposure control in X-ray medical imagers |
JP6837639B2 (ja) * | 2017-02-16 | 2021-03-03 | 国立大学法人豊橋技術科学大学 | イオン濃度分布測定装置 |
WO2018187370A1 (en) * | 2017-04-04 | 2018-10-11 | Artilux Corporation | High-speed light sensing apparatus iii |
TWI753278B (zh) * | 2018-07-30 | 2022-01-21 | 新加坡商普里露尼庫斯新加坡私人有限公司 | 固態攝像裝置、固態攝像裝置之驅動方法、及電子機器 |
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- 2004-09-27 WO PCT/JP2004/014091 patent/WO2005034511A1/ja active Application Filing
- 2004-09-27 EP EP04788187.5A patent/EP1677522B1/en not_active Expired - Fee Related
- 2004-09-27 US US10/574,104 patent/US7800667B2/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
CN1864403A (zh) | 2006-11-15 |
KR101074551B1 (ko) | 2011-10-17 |
EP1677522A1 (en) | 2006-07-05 |
EP1677522B1 (en) | 2013-04-24 |
US20080036887A1 (en) | 2008-02-14 |
EP1677522A4 (en) | 2010-03-31 |
US7800667B2 (en) | 2010-09-21 |
CN100401751C (zh) | 2008-07-09 |
JP4268492B2 (ja) | 2009-05-27 |
JP2005117101A (ja) | 2005-04-28 |
KR20060095552A (ko) | 2006-08-31 |
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