WO2007085942A2 - Image sensor with a photodiode readout circuit - Google Patents

Image sensor with a photodiode readout circuit Download PDF

Info

Publication number
WO2007085942A2
WO2007085942A2 PCT/IB2007/000165 IB2007000165W WO2007085942A2 WO 2007085942 A2 WO2007085942 A2 WO 2007085942A2 IB 2007000165 W IB2007000165 W IB 2007000165W WO 2007085942 A2 WO2007085942 A2 WO 2007085942A2
Authority
WO
WIPO (PCT)
Prior art keywords
readout circuit
output
transistor
photodiode
readout
Prior art date
Application number
PCT/IB2007/000165
Other languages
French (fr)
Other versions
WO2007085942A3 (en
Inventor
Sam Maddalena
Original Assignee
Melexis Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0601485A external-priority patent/GB0601485D0/en
Priority claimed from GB0606911A external-priority patent/GB0606911D0/en
Application filed by Melexis Nv filed Critical Melexis Nv
Priority to EP07733879A priority Critical patent/EP1982513A2/en
Publication of WO2007085942A2 publication Critical patent/WO2007085942A2/en
Publication of WO2007085942A3 publication Critical patent/WO2007085942A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present invention relates to optical sensing means in general and in particular to readout architectures for photodiode based optical sensor means. More specifically, the present invention relates to a low silicon area and thus low cost method of reading out photodiodes by decoupling the parasitic photodiode capacitance from the dimensioning requirements of the rest of the readout architecture, allowing a good behaviour in terms of gain (high) and linearity (high), even when using large photodiodes.
  • a typical photodiode readout architecture comprises a Trans-Impedance amplifier or an Integrating amplifier.
  • the provision of an amplifier decouples the parasitic capacitance of the photodiode from the rest of the readout architecture. This enables high performances in terms of gain (high) and linearity (high) to be achieved but has the disadvantage of being relatively costly due to the relatively large area taken up by the circuitry.
  • a typical photodiode readout architecture comprises a small number of transistors, said transistors having small dimensions. This minimises the layout area and hence reduces the cost of the circuitry.
  • known architecture of this type omits any decoupling of the parasitic capacitance of the photodiode from the rest of the readout architecture, such circuits typically provide significantly lower performance compared to the larger readout architecture above in terms of gain (low) and linearity (low).
  • readout circuitry for a photodiode comprising: a cascode transistor positioned between the photodiode and the rest of the readout circuitry, the cascode transistor operable to decouple the parasitic capacitance of the photodiode from the rest of the readout circuitry, whilst allowing a signal indicative of the output of the photodiode to pass to the rest of the readout circuitry.
  • This provides a novel photodiode readout circuit architecture that combines the relatively high performance of a readout architecture based upon a trans- impedance amplifier or an integrating amplifier, with the small layout size (and hence low cost) of a transistor based readout architecture. Additionally, with suitable selection of the properties of the cascode transistor, the readout circuit architecture of the present invention may be used for readout of relatively large or relatively small photodiodes.
  • a constant bias may be applied to the gate of the cascode transistor.
  • the readout circuit may comprise an integrating capacitor connected to the cascode transistor via an integrating node.
  • the integrating capacitor is operable to integrate and store current received from the cascode transistor.
  • the integrating capacitor may be an active, passive, parasitic or real component as required or as desired.
  • the readout circuit may further comprise a buffering transistor.
  • the gate of the buffering transistor may be connected to the integrating node and to the integrating capacitor.
  • the buffering transistor may be connected to the output of the readout circuit via an output switch.
  • the output may be connected to an output constant current source. When the output switch is closed, the output signal may be readout.
  • the output switch may be controlled by external circuitry and is typically activated periodically.
  • the output switch may comprise any one of: an nMOS type transistor; a pMOS type transistor; or a combination of an nMOS type transistor and a pMOS type transistor in parallel.
  • the readout circuit may additionally be provided with a reset means operable to set the signal level at the integrating node (and hence at the integrating capacitor) at a known level.
  • the reset means may be a reset transistor, which may be an nMOS or pMOS type transistor as required or as desired.
  • other well known analogue design techniques may be used to further enhance the performance. Such techniques include negative feedback to enhance settling and linearity performance and pipeline techniques
  • the readout circuit may comprise a two stage readout circuit.
  • the first stage may comprise a readout circuit similar to that described above wherein the output switch is designated a track and hold switch and the second stage is connected to the first stage via said track and hold switch.
  • the track and hold switch When the track and hold switch is closed, a current may flow from the first stage to the second stage.
  • the track and hold switch may be controlled by a track and hold signal.
  • the track and hold signal may be controlled by external circuitry and is typically activated periodically.
  • the second stage may comprise a track and hold capacitor connected to the base of a second buffering transistor, the second buffering transistor connected to the output of the readout circuit via an output switch.
  • the track and hold capacitor is operable to integrate and store current transferred through the track and hold switch.
  • a current may flow from the buffering transistor to the output, this current being determined by the state of the track and hold capacitor.
  • the output may be connected to an output constant current source. Accordingly, the output signal may be readout as variations in the constant current signal.
  • the output switch may be controlled by external circuitry and is typically activated periodically.
  • the output switch and/or the track and hold switch may comprise any one of: an nMOS type transistor; a pMOS type transistor; or a combination of an nMOS type transistor and a pMOS type transistor in parallel.
  • said two stage readout circuit may be additionally provided with a stabilising means and/or a photodiode node reset means, if required or desired.
  • a sensing array comprising a plurality of photodiodes, each photodiode being connected to a readout circuit according to the first aspect of the present invention.
  • the sensing array of the second aspect of the present invention may incorporate any or all features of the first aspect of the present invention as desired or as appropriate.
  • the output switches relating to each photodiode in the array may be activated in sequence to obtain a readout from all photodiodes in the array.
  • An output constant current source is shared between one or more photodiodes.
  • Figure 2 is a timing diagram for the circuit of figure 1 ;
  • Figure 3 shows a small size transistor based photodiode readout circuit in accordance with a second embodiment of the present invention
  • Figure 4 shows a small size transistor based photodiode readout circuit in accordance with a third embodiment of the present invention
  • Figure 5 is a timing diagram for the circuit of figure 4.
  • Figure 6 shows a small size transistor based photodiode readout circuit in accordance with a fourth embodiment of the present invention.
  • a small size transistor based photodiode readout circuit 100 in accordance with the present invention comprises a cascode transistor
  • the cascode transistor Mc is connected via an integrating node to a reset transistor M R , an integrating capacitor C I N T and to a buffering transistor MB-
  • the integrating capacitor C 1 N T integrates the signal received from cascode transistor Mc via integrating node n ⁇ T-
  • the reset transistor is operable, when an appropriate signal is input to its gate via reset input RSTP to reset the signal level at the integrating node n ⁇ T to a known level and hence reset the integrating capacitor C I N T to a known level.
  • the integrating capacitor C I N T may be a passive, active, parasitic or real component as desired or as required.
  • the buffering transistor M B is connected to the readout circuit output via a switch Ms.
  • switch Ms When an appropriate signal is applied to switch Ms via input RO it is closed and a signal can pass from M B to the output, the signal being a function of the voltage on the integrating capacitor C IN T.
  • the switch Ms may comprise a transistor either of the nMOS type or the pMOS type or a combination both in parallel as required or as desired.
  • the cascode transistor Mc connected between the output of a photodiode D PH and the rest of said readout circuit 100 has a constant bias applied to its gate via the BIAS input.
  • the transistor Mc is operable to decouple the parasitic capacitance C PH (shown as a separate capacitor in figure 1) of the photodiode D PH from the rest of the readout circuit 100, and in particular the capacitance of the integrating capacitor C I N T -
  • the signal integrated by the integrating capacitor has a good linear relationship with the output of the photodiode D PH , and the output signal of the readout circuitry 100 has a relatively high linearity and relatively high gain, whilst the readout circuit 100 is provided within a relatively small area.
  • switch Ms is closed by a signal RO. This transfers the voltage stored on C 1NT to the output OUT.
  • figure 3 an alternative embodiment of a readout circuit 200 and typical signal levels during operation of the readout circuit 200 are shown.
  • the embodiment of figure 3 differs from that of figure 1 in the provision of an extra transistor M F to have a closed loop control of node np H , stabilising this node in the voltage domain (by negative feedback, as mentioned above).
  • this node is normally dependent on the parasitic capacitance of the photodiode D PH .
  • the provision of the transistor M F adds a measure of independence from the parasitic capacitance C PH and thus stabilises the behaviour of the node np H -
  • a M RN reset transistor could be used to reset the np H node to a known start-level.
  • FIGS 4 and 5 another alternative embodiment of a readout circuit 300 and typical signal levels during operation of the readout circuit 300 are shown, hi this embodiment, many of the features of first embodiment are retained and have the same function. Accordingly these features are referred to with the same reference and are not described further. Similarly, those signal levels that remain the same in each embodiment are not described.
  • the embodiment of figure 4 operates with a two stage readout operation, hi this embodiment, a sample and hold stage is added to the output of the circuit in figure 1 to pipeline the readout process.
  • the readout circuit 400 has a two-stage readout like the embodiment of figures 5 and 6 but additionally includes the extra transistor M F to stabilise the node np ⁇ at the output of the photodiode D PH (by negative feedback system as mentioned above).

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Amplifiers (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

A small size transistor based photodiode readout circuit 100 in accordance with the present invention comprises a cascode transistor MC connected to the output of a photodiode. The cascode transistor MC is connected via an integrating node to a reset transistor MR, an integrating capacitor CINT and to a buffering transistor MB. When an appropriate signal is applied to switch MS via input RO it is closed and a signal can pass from MB to the output, the signal being a function of the voltage on the integrating capacitor CINT. The cascode transistor MC connected between the output of a photodiode DPH and the rest of said readout circuit 100 is operable to decouple the parasitic capacitance CPH of the photodiode DPH from the rest of the readout circuit 100, and in particular the capacitance of the integrating capacitor CINT. As a result, the signal integrated by the integrating capacitor CINT has a good linear relationship with the output of the photodiode DPH, and the output signal of the readout circuitry 100 has a relatively high linearity and relatively high gain, whilst the readout circuit 100 is provided within a relatively small area.

Description

PHQTODIODE READOUT CIRCUIT
The present invention relates to optical sensing means in general and in particular to readout architectures for photodiode based optical sensor means. More specifically, the present invention relates to a low silicon area and thus low cost method of reading out photodiodes by decoupling the parasitic photodiode capacitance from the dimensioning requirements of the rest of the readout architecture, allowing a good behaviour in terms of gain (high) and linearity (high), even when using large photodiodes.
Two main types of readout circuit architectures for photodiodes are known. For "large" photodiodes (typically of area > 500um2, used e.g. in ID optical arrays), a typical photodiode readout architecture comprises a Trans-Impedance amplifier or an Integrating amplifier. The provision of an amplifier decouples the parasitic capacitance of the photodiode from the rest of the readout architecture. This enables high performances in terms of gain (high) and linearity (high) to be achieved but has the disadvantage of being relatively costly due to the relatively large area taken up by the circuitry.
For small photodiodes (typically of area < 500um2, used e.g. in 2D optical cameras), a typical photodiode readout architecture comprises a small number of transistors, said transistors having small dimensions. This minimises the layout area and hence reduces the cost of the circuitry. However, as known architecture of this type omits any decoupling of the parasitic capacitance of the photodiode from the rest of the readout architecture, such circuits typically provide significantly lower performance compared to the larger readout architecture above in terms of gain (low) and linearity (low).
It is therefore an object of the present invention to provide a relatively small (and hence relatively low cost) readout circuit for a photodiode with a relatively high performance in terms of gain and linearity.
According to a first aspect of the present invention there is provided readout circuitry for a photodiode comprising: a cascode transistor positioned between the photodiode and the rest of the readout circuitry, the cascode transistor operable to decouple the parasitic capacitance of the photodiode from the rest of the readout circuitry, whilst allowing a signal indicative of the output of the photodiode to pass to the rest of the readout circuitry.
This provides a novel photodiode readout circuit architecture that combines the relatively high performance of a readout architecture based upon a trans- impedance amplifier or an integrating amplifier, with the small layout size (and hence low cost) of a transistor based readout architecture. Additionally, with suitable selection of the properties of the cascode transistor, the readout circuit architecture of the present invention may be used for readout of relatively large or relatively small photodiodes.
A constant bias may be applied to the gate of the cascode transistor. The readout circuit may comprise an integrating capacitor connected to the cascode transistor via an integrating node. The integrating capacitor is operable to integrate and store current received from the cascode transistor. The integrating capacitor may be an active, passive, parasitic or real component as required or as desired.
The readout circuit may further comprise a buffering transistor. The gate of the buffering transistor may be connected to the integrating node and to the integrating capacitor. The buffering transistor may be connected to the output of the readout circuit via an output switch. The output may be connected to an output constant current source. When the output switch is closed, the output signal may be readout.
The output switch may be controlled by external circuitry and is typically activated periodically. The output switch may comprise any one of: an nMOS type transistor; a pMOS type transistor; or a combination of an nMOS type transistor and a pMOS type transistor in parallel.
The readout circuit may additionally be provided with a reset means operable to set the signal level at the integrating node (and hence at the integrating capacitor) at a known level. The reset means may be a reset transistor, which may be an nMOS or pMOS type transistor as required or as desired. In some embodiments, other well known analogue design techniques may be used to further enhance the performance. Such techniques include negative feedback to enhance settling and linearity performance and pipeline techniques
If desired, the readout circuit may comprise a two stage readout circuit. In such embodiments, the first stage may comprise a readout circuit similar to that described above wherein the output switch is designated a track and hold switch and the second stage is connected to the first stage via said track and hold switch.
When the track and hold switch is closed, a current may flow from the first stage to the second stage. The track and hold switch may be controlled by a track and hold signal. The track and hold signal may be controlled by external circuitry and is typically activated periodically.
The second stage may comprise a track and hold capacitor connected to the base of a second buffering transistor, the second buffering transistor connected to the output of the readout circuit via an output switch.
The track and hold capacitor, is operable to integrate and store current transferred through the track and hold switch. When the output switch is closed, a current may flow from the buffering transistor to the output, this current being determined by the state of the track and hold capacitor. The output may be connected to an output constant current source. Accordingly, the output signal may be readout as variations in the constant current signal. The output switch may be controlled by external circuitry and is typically activated periodically.
The output switch and/or the track and hold switch may comprise any one of: an nMOS type transistor; a pMOS type transistor; or a combination of an nMOS type transistor and a pMOS type transistor in parallel.
In some embodiments, said two stage readout circuit may be additionally provided with a stabilising means and/or a photodiode node reset means, if required or desired.
According to a second aspect of the present invention there is provided a sensing array comprising a plurality of photodiodes, each photodiode being connected to a readout circuit according to the first aspect of the present invention.
The sensing array of the second aspect of the present invention may incorporate any or all features of the first aspect of the present invention as desired or as appropriate.
The output switches relating to each photodiode in the array may be activated in sequence to obtain a readout from all photodiodes in the array. An output constant current source is shared between one or more photodiodes.
In order that the present invention may be more easily understood, it will now be described further below, by way of example only and with reference to the accompanying drawings, in which:- Figure 1 shows a small size transistor based photodiode readout circuit in accordance with a first embodiment of the present invention;
Figure 2 is a timing diagram for the circuit of figure 1 ;
Figure 3 shows a small size transistor based photodiode readout circuit in accordance with a second embodiment of the present invention;
Figure 4 shows a small size transistor based photodiode readout circuit in accordance with a third embodiment of the present invention;
Figure 5 is a timing diagram for the circuit of figure 4; and
Figure 6 shows a small size transistor based photodiode readout circuit in accordance with a fourth embodiment of the present invention.
Referring now to figure 1, a small size transistor based photodiode readout circuit 100 in accordance with the present invention comprises a cascode transistor
Mc connected to the output of a photodiode. The cascode transistor Mc is connected via an integrating node to a reset transistor MR, an integrating capacitor CINT and to a buffering transistor MB- The integrating capacitor C1NT integrates the signal received from cascode transistor Mc via integrating node n^T- The reset transistor is operable, when an appropriate signal is input to its gate via reset input RSTP to reset the signal level at the integrating node n^T to a known level and hence reset the integrating capacitor CINT to a known level. The integrating capacitor CINT may be a passive, active, parasitic or real component as desired or as required.
The buffering transistor MB is connected to the readout circuit output via a switch Ms. When an appropriate signal is applied to switch Ms via input RO it is closed and a signal can pass from MB to the output, the signal being a function of the voltage on the integrating capacitor CINT. The switch Ms may comprise a transistor either of the nMOS type or the pMOS type or a combination both in parallel as required or as desired.
The cascode transistor Mc connected between the output of a photodiode DPH and the rest of said readout circuit 100 has a constant bias applied to its gate via the BIAS input. The transistor Mc is operable to decouple the parasitic capacitance CPH (shown as a separate capacitor in figure 1) of the photodiode DPH from the rest of the readout circuit 100, and in particular the capacitance of the integrating capacitor CINT- As a result, the signal integrated by the integrating capacitor has a good linear relationship with the output of the photodiode DPH, and the output signal of the readout circuitry 100 has a relatively high linearity and relatively high gain, whilst the readout circuit 100 is provided within a relatively small area.
Referring now to figure 2, indicative signal levels during normal operation of the readout circuit are shown. Normal operation of the readout circuit is commenced by applying a low signal to RSTP (or a high level to a compelementary NMOS) and hence to the gate of reset transistor MR. This causes the signal level at niκτ to reset to a known level and hence the capacitor CINT to be reset to a known level. After reset, current generated in the photodiode DPH results in current flow at niNT which is integrated by CINT-
After a predetermined period, switch Ms is closed by a signal RO. This transfers the voltage stored on C1NT to the output OUT.
Turning now to figure 3 , an alternative embodiment of a readout circuit 200 and typical signal levels during operation of the readout circuit 200 are shown. In this embodiment, many of the features of first embodiment are retained and have the same function. The embodiment of figure 3 differs from that of figure 1 in the provision of an extra transistor MF to have a closed loop control of node npH, stabilising this node in the voltage domain (by negative feedback, as mentioned above).
The behaviour of this node is normally dependent on the parasitic capacitance of the photodiode DPH. The provision of the transistor MF adds a measure of independence from the parasitic capacitance CPH and thus stabilises the behaviour of the node npH-
As an extra option, a MRN reset transistor could be used to reset the npH node to a known start-level. Turning now to figures 4 and 5, another alternative embodiment of a readout circuit 300 and typical signal levels during operation of the readout circuit 300 are shown, hi this embodiment, many of the features of first embodiment are retained and have the same function. Accordingly these features are referred to with the same reference and are not described further. Similarly, those signal levels that remain the same in each embodiment are not described.
The embodiment of figure 4 operates with a two stage readout operation, hi this embodiment, a sample and hold stage is added to the output of the circuit in figure 1 to pipeline the readout process.
Turning now to figures 5 and 6, a further embodiment of a readout circuit 400 and typical signal levels during operation of the readout circuit 400 are shown. The readout circuit 400 has a two-stage readout like the embodiment of figures 5 and 6 but additionally includes the extra transistor MF to stabilise the node npπ at the output of the photodiode DPH (by negative feedback system as mentioned above).
It is of course to be understood that the invention is not to be restricted to the detailed of the above embodiments which are described by way of example only.

Claims

Claims
1. A readout circuit for a photodiode comprising: a cascode transistor positioned between the photodiode and the rest of the readout circuit, the cascode transistor operable to decouple the parasitic capacitance of the photodiode from the rest of the readout circuit, whilst allowing a signal indicative of the output of the photodiode to pass to the rest of the readout circuit.
2. A readout circuit as claimed in claim 1 wherein a constant bias is applied to the gate of the cascode transistor.
3. A readout circuit as claimed in any preceding claim wherein the readout circuit comprises an integrating capacitor connected to the cascode transistor via an integrating node.
4. A readout circuit as claimed in claim 3 wherein the integrating capacitor is operable to integrate and store current received from the cascode transistor.
5. A readout circuit as claimed in claim 4 wherein the integrating capacitor is an active component.
6. A readout circuit as claimed in claim 4 wherein the integrating capacitor is a passive component.
7. A readout circuit as claimed in claim 4 wherein the integrating capacitor is a parasitic component.
8. A readout circuit as claimed in claim 4 wherein the integrating capacitor is a real component.
9. A readout circuit as claimed in any preceding claim wherein the readout circuit further comprises a buffering transistor.
10. A readout circuit as claimed in claim 9 wherein the gate of the buffering transistor is connected to the integrating node and to the integrating capacitor.
11. A readout circuit as claimed in any preceding claim wherein the output is connected to an output constant current source.
12. A readout circuit as claimed in any one of claims 9 to 11 wherein the buffering transistor is connected to the output of the readout circuit via an output switch.
13. A readout circuit as claimed in claim 12 wherein when the output switch is closed, the output signal is readout.
14. A readout circuit as claimed in claim 12 or claim 13 wherein the output switch is controlled by external circuitry.
15. A readout circuit as claimed in any one of claims 12 to 14 wherein the output switch is activated periodically.
16. A readout circuit as claimed in any one of claims 12 to 15 wherein the output switch comprises any one of: an nMOS type transistor; a pMOS type transistor; or a combination of an nMOS type transistor and a pMOS type transistor in parallel.
17. A readout circuit as claimed in any preceding claim wherein the readout circuit is additionally be provided with a reset means operable to set the signal level at the integrating node at a known level.
18. A readout circuit as claimed in claim 17 wherein the reset means is a reset transistor.
19. A readout circuit as claimed in claim 18 wherein the reset transistor is an nMOS or pMOS type transistor.
20. A readout circuit as claimed in any preceding claim wherein the readout circuit comprises a two stage readout circuit.
21. A readout circuit as claimed in claim 20 wherein the first stage comprises a readout circuit as claimed in any preceding claim wherein the output switch is designated a track and hold switch and the second stage is connected to the first stage via said track and hold switch.
22. A readout circuit as claimed in claim 21 wherein when the track and hold switch is closed, a current flows from the first stage to the second stage.
23. A readout circuit as claimed in claim 21 or claim 22 wherein the track and hold switch is controlled by a track and hold signal.
24. A readout circuit as claimed in claim 23 wherein the track and hold signal is controlled by external circuitry.
25. A readout circuit as claimed in claim 23 or claim 24 wherein the track and hold signal is activated periodically.
26. A readout circuit as claimed in any one of claims 20 to 25 wherein the second stage comprises a track and hold capacitor connected to the base of a second buffering transistor, the second buffering transistor connected to the output of the readout circuit via an output switch.
27. A readout circuit as claimed in claim 26 wherein the track and hold capacitor, is operable to integrate and store current transferred through the track and hold switch.
28. A readout circuit as claimed in claim 26 or claim 27 wherein when the output switch is closed, a current flows from the buffering transistor to the output.
29. A readout circuit as claimed in any one of claims 26 to 28 wherein the output is connected to an output constant current source.
30. A readout circuit as claimed in any one of claims 26 to 29 wherein the output switch is controlled by external circuitry.
31. A readout circuit as claimed in any one of claims 26 to 30 wherein the output switch is activated periodically.
32. A readout circuit as claimed in any one of claims 26 to 31 wherein the output switch and/or the track and hold switch comprises any one of: an nMOS type transistor; a pMOS type transistor; or a combination of an nMOS type transistor and a pMOS type transistor in parallel.
33. A readout circuit as claimed in any one of claims 20 to 32 wherein said two stage readout circuit is provided with a stabilising means.
34. A readout circuit as claimed in any one of claims 20 to .33 wherein said two stage readout circuit is provided with a photodiode node reset means.
35. A sensing array comprising a plurality of photodiodes, each photodiode being connected to a readout circuit according to any preceding claim.
36. A sensing array as claimed in claim 35 wherein the output switches relating to each photodiode in the array are activated in sequence to obtain a readout from all photodiodes in the array.
37. A sensing array as claimed in claim 35 or claim 36 wherein an output constant current source is shared between one or more photodiodes.
PCT/IB2007/000165 2006-01-25 2007-01-25 Image sensor with a photodiode readout circuit WO2007085942A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP07733879A EP1982513A2 (en) 2006-01-25 2007-01-25 Image sensor with a photodiode readout circuit

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
GB0601485.6 2006-01-25
GB0601485A GB0601485D0 (en) 2006-01-25 2006-01-25 Photodiode readout circuit
GB0606911.6 2006-04-06
GB0606911A GB0606911D0 (en) 2006-04-06 2006-04-06 Photodiode readout circuit

Publications (2)

Publication Number Publication Date
WO2007085942A2 true WO2007085942A2 (en) 2007-08-02
WO2007085942A3 WO2007085942A3 (en) 2007-10-25

Family

ID=38190767

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2007/000165 WO2007085942A2 (en) 2006-01-25 2007-01-25 Image sensor with a photodiode readout circuit

Country Status (2)

Country Link
EP (1) EP1982513A2 (en)
WO (1) WO2007085942A2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2923915A1 (en) * 2007-11-16 2009-05-22 Thales Sa IR SENSOR INTERFERENCE AND DAMAGE SYSTEM
EP2160011A1 (en) * 2008-09-02 2010-03-03 Société Française de Détecteurs Infrarouges - SOFRADIR Device for reading electronic loads and detector comprising such devices
WO2017158483A1 (en) * 2016-03-14 2017-09-21 Insightness Ag A vision sensor, a method of vision sensing, and a depth sensor assembly
US10567679B2 (en) 2016-12-30 2020-02-18 Insightness Ag Dynamic vision sensor architecture

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872596A (en) * 1992-09-28 1999-02-16 Canon Kabushiki Kaisha Device for widening the dynamic range of solid-state image pickup elements
US6229134B1 (en) * 1998-10-13 2001-05-08 Photobit Corporation Using cascaded gain stages for high-gain and high-speed readout of pixel sensor data
US20030052349A1 (en) * 2001-09-14 2003-03-20 Hae-Seung Lee CMOS pixel design for minimization of defect-induced leakage current
US6873359B1 (en) * 2000-09-29 2005-03-29 Rockwell Science Center, Llc. Self-adjusting, adaptive, minimal noise input amplifier circuit
WO2005034511A1 (en) * 2003-10-02 2005-04-14 Hamamatsu Photonics K.K. Photo detecting apparatus

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5872596A (en) * 1992-09-28 1999-02-16 Canon Kabushiki Kaisha Device for widening the dynamic range of solid-state image pickup elements
US6229134B1 (en) * 1998-10-13 2001-05-08 Photobit Corporation Using cascaded gain stages for high-gain and high-speed readout of pixel sensor data
US6873359B1 (en) * 2000-09-29 2005-03-29 Rockwell Science Center, Llc. Self-adjusting, adaptive, minimal noise input amplifier circuit
US20030052349A1 (en) * 2001-09-14 2003-03-20 Hae-Seung Lee CMOS pixel design for minimization of defect-induced leakage current
WO2005034511A1 (en) * 2003-10-02 2005-04-14 Hamamatsu Photonics K.K. Photo detecting apparatus

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
BIGAS ET AL: "Review of CMOS image sensors" MICROELECTRONICS JOURNAL, MACKINTOSH PUBLICATIONS LTD. LUTON, GB, vol. 37, no. 5, 6 September 2005 (2005-09-06), pages 433-451, XP005324238 ISSN: 0026-2692 *
CHIH-CHENG HSIEH ET AL: "Focal-Plane-Arrays and CMOS Readout Techniques of Infrared Imaging Systems" IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 7, no. 4, August 1997 (1997-08), XP011014404 ISSN: 1051-8215 *
CHING-CHUN WANG ET AL: "The effect of hot carriers on the operation of CMOS active pixel sensors" INTERNATIONAL ELECTRON DEVICES MEETING 2001. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC. 2 - 5, 2001, NEW YORK, NY : IEEE, US, 2 December 2001 (2001-12-02), pages 2451-2454, XP010575190 ISBN: 0-7803-7050-3 *

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2923915A1 (en) * 2007-11-16 2009-05-22 Thales Sa IR SENSOR INTERFERENCE AND DAMAGE SYSTEM
WO2009063038A1 (en) * 2007-11-16 2009-05-22 Thales System for jamming and damaging an ir sensor
EP2160011A1 (en) * 2008-09-02 2010-03-03 Société Française de Détecteurs Infrarouges - SOFRADIR Device for reading electronic loads and detector comprising such devices
FR2935577A1 (en) * 2008-09-02 2010-03-05 Fr De Detecteurs Infrarouges S DEVICE FOR READING ELECTRONIC LOADS AND SENSOR COMPRISING SUCH DEVICES
WO2017158483A1 (en) * 2016-03-14 2017-09-21 Insightness Ag A vision sensor, a method of vision sensing, and a depth sensor assembly
US11463637B2 (en) 2016-03-14 2022-10-04 Sony Advanced Visual Sensing Ag Vision sensor, a method of vision sensing, and a depth sensor assembly
US11012646B2 (en) 2016-03-14 2021-05-18 Sony Advanced Visual Sensing Ag Vision sensor, a method of vision sensing, and a depth sensor assembly
US10652489B2 (en) 2016-03-14 2020-05-12 Insightness Ag Vision sensor, a method of vision sensing, and a depth sensor assembly
US10715750B2 (en) 2016-12-30 2020-07-14 Insightness Ag Data rate control for event-based vision sensor
US10602083B2 (en) 2016-12-30 2020-03-24 Insightness Ag Global shutter in pixel frame memory
US11076114B2 (en) 2016-12-30 2021-07-27 Sony Advanced Visual Sensing Ag Dynamic vision sensor architecture
US11336859B2 (en) 2016-12-30 2022-05-17 Sony Advanced Visual Sensing Ag Global shutter in pixel frame memory
US11431937B2 (en) 2016-12-30 2022-08-30 Sony Advanced Visual Sensing Ag Data rate control for event-based vision sensor
US10567679B2 (en) 2016-12-30 2020-02-18 Insightness Ag Dynamic vision sensor architecture
US11711631B2 (en) 2016-12-30 2023-07-25 Sony Advanced Visual Sensing Ag Dynamic vision sensor architecture
US11991466B2 (en) 2016-12-30 2024-05-21 Sony Advanced Visual Sensing Ag Data rate control for event-based vision sensor
US12010447B2 (en) 2016-12-30 2024-06-11 Sony Advanced Visual Sensing Ag Dynamic vision sensor architecture

Also Published As

Publication number Publication date
EP1982513A2 (en) 2008-10-22
WO2007085942A3 (en) 2007-10-25

Similar Documents

Publication Publication Date Title
US10904465B2 (en) Sample and hold based temporal contrast vision sensor
US7791380B2 (en) Current sampling method and circuit
EP0773669B1 (en) Circuit, pixel, device and method for reducing fixed pattern noise in solid state imaging devices
US7746170B2 (en) Class AB amplifier and imagers and systems using same
JP4031447B2 (en) Offset adjustable differential amplifier
US20080284501A1 (en) Reference bias circuit for compensating for process variation
CN108694962B (en) Amplifier and semiconductor device using the same
US7310252B2 (en) Closed-loop high voltage booster
US8210744B2 (en) Apparatus for detecting temperature using transistors
KR20090031982A (en) Semiconductor integrated circuit device
US20030164443A1 (en) Image sensor
US6580063B1 (en) Solid state imaging device having high output signal pain
EP0851670A2 (en) Photoelectric conversion apparatus
EP1982513A2 (en) Image sensor with a photodiode readout circuit
JP2007235718A (en) Signal amplifier
US6952227B2 (en) CMOS image sensor for providing wider dynamic range
US7245188B2 (en) Light receiving amplification circuit
US5101174A (en) Advanced charge detection amplifier for high performance image sensors
US7262638B2 (en) Current sense amplifier
JP5661224B2 (en) Readout device with array configuration
US11656124B1 (en) Sensing device
US7683671B2 (en) Method, apparatus, and system providing power supply independent imager output driver having a constant slew rate
US5945663A (en) Charge measurement circuit which includes a charge sensitive amplifier holding input to a constant voltage
US20050024150A1 (en) Monolithic amplifier with high-value, monolithically formed passive feedback resistor
US9787921B2 (en) Image sensing device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

WWE Wipo information: entry into national phase

Ref document number: 2007733879

Country of ref document: EP