EP2160011A1 - Device for reading electronic loads and detector comprising such devices - Google Patents

Device for reading electronic loads and detector comprising such devices Download PDF

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Publication number
EP2160011A1
EP2160011A1 EP20090305736 EP09305736A EP2160011A1 EP 2160011 A1 EP2160011 A1 EP 2160011A1 EP 20090305736 EP20090305736 EP 20090305736 EP 09305736 A EP09305736 A EP 09305736A EP 2160011 A1 EP2160011 A1 EP 2160011A1
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EP
European Patent Office
Prior art keywords
circuit
mos transistors
transistors
voltage
capacitor
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EP20090305736
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German (de)
French (fr)
Inventor
Michel Zecri
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Societe Francaise de Detecteurs Infrarouges SOFRADIR SAS
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Societe Francaise de Detecteurs Infrarouges SOFRADIR SAS
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N3/00—Scanning details of television systems; Combination thereof with generation of supply voltages
    • H04N3/10—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical
    • H04N3/14—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices
    • H04N3/15—Scanning details of television systems; Combination thereof with generation of supply voltages by means not exclusively optical-mechanical by means of electrically scanned solid-state devices for picture signal generation
    • H04N3/155—Control of the image-sensor operation, e.g. image processing within the image-sensor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors

Definitions

  • the present invention relates to the field of reading electronic charges created for example in elementary photodetectors of a detector, in particular photodiodes.
  • the figure 1 illustrates a circuit 10 for reading electric charges created in a photodiode 12 of a matrix detector under the effect of an infrared radiation "RE" incident thereon.
  • the read circuit 10 conventionally comprises an input stage 14 for storing the charges created in the photodiode 12 , and a read stage 16 of the stored charges.
  • the input stage 12 comprises a n-channel injection MOS transistor 18 and a storage capacitor 20 .
  • the source of the injection transistor 18 is connected to a terminal 22 of the photodiode 12
  • the second terminal 24 of the photodiode 12 is also connected to a constant potential, such as the ground for example.
  • the function of the injection transistor 18 is to bias the photodiode 12 and to transfer the charges created therein to the storage capacitor 20 , which is connected by a terminal 26 to the drain of the transistor 18 and by the other terminal 28 to the ground.
  • the input stage 12 also comprises a p-channel initialization MOS transistor 29, the drain of which is connected to the terminal 26 of the storage capacitor 20, and the source of which is connected to a constant potential "V +" equal to Vdda - Vsat, where "Vdda” is a predetermined constant power supply voltage of the reading circuit 10 and "Vsat” is the saturation voltage of the transistor 29.
  • the initialization transistor 29 has the function of discharging storage capacitor 20 prior to charge accumulation therein.
  • the read stage 16 comprises a switch 30 connected to the terminal 26 of the storage capacitor 20 , for example formed of an n-channel MOS transistor 32 and a p-channel MOS transistor 34, a capacitor of FIG. reading 36 connected by a terminal 38 to the switch 30 and the other terminal 40 to the ground, a p-channel initialization MOS transistor 42, whose source is connected to the constant potential "V +", and whose drain is connected to the terminal 38 of the read capacitor 36 , and a charge preamplifier 44.
  • a switch 30 connected to the terminal 26 of the storage capacitor 20 , for example formed of an n-channel MOS transistor 32 and a p-channel MOS transistor 34, a capacitor of FIG. reading 36 connected by a terminal 38 to the switch 30 and the other terminal 40 to the ground, a p-channel initialization MOS transistor 42, whose source is connected to the constant potential "V +", and whose drain is connected to the terminal 38 of the read capacitor 36 , and a charge preamplifier 44.
  • the preamplifier 44 comprises, for example, an operational amplifier 46 , a first n-channel MOS transistor 48 , whose gate is connected to the terminal 38 of a read capacitor 36 , and whose drain is connected to a first input terminal of FIG. the amplifier 46 , and a second n-channel MOS transistor 50 whose drain is connected to the source of said first transistor 48 and whose source is connected to the second input terminal of the amplifier 46, and whose gate receives an addressing signal "@" corresponding to the column of the matrix detector to which the photodiode 12 belongs.
  • the photodiode 12 is biased by the injection transistor 18 and the charges created in said photodiode are stored in the capacitor 20 , which has been previously discharged by means of the initialization transistor 29, the switch 30 being moreover open.
  • the switch 30 is closed.
  • the charges stored in the capacitor 20 are then transferred to the read capacitor 36, previously initialized by means of the transistor 42, and then amplified by the preamplifier 44 to be delivered for example on a bus.
  • an electronic charge reading circuit is associated with each photodiode of a matrix detector, so that said circuit is usually formed on a reduced surface, in particular for reasons of compactness.
  • the increase of the voltage across the capacitors involves subjecting the transistors 18, 29, 42, 48 and 50 to higher voltages.
  • the transistors are usually designed to operate at a predetermined maximum voltage, in order to guarantee the reliability of these components.
  • Increasing the voltage across the capacitors to increase the total storable charge therefore requires to subject the MOS transistors 18, 29, 42, 48, 50 to voltage constraints reducing their life, or even likely to destroy them.
  • the maximum operating voltage of the transistors 18, 29, 42, 48, 50 determines the maximum voltage applicable across the capacitors 20, 36.
  • the object of the present invention is to solve the aforementioned problem by proposing a device for reading electric charges of simple and compact design, to substantially increase the total charge storable in the capacitors without subjecting the transistors to strong constraints in terms of Of voltage.
  • the subject of the invention is a device for reading electronic charges, comprising an input for receiving electronic charges, at least one capacitor for storing electronic charges and at least one circuit based on MOS transistors whose the maximum operating voltage determines the maximum voltage across the at least one capacitor.
  • the or each circuit based on MOS transistors consists of cascoded transistors.
  • cascoded transistors are understood to mean transistors connected in series, the drain of one transistor being connected to the source of another transistor.
  • the MOS transistors of the electric charge reading device whose operating voltage limits the voltage applicable across the capacitors, are cascoded with at least one other MOS transistor.
  • each transistor sees at its terminals a lower voltage.
  • each of the transistors sees half of the total voltage applied to the assembly. Since the maximum operating voltage of such an arrangement is greater than the maximum voltage of a single transistor, it is possible to increase the voltage across the capacitors without subjecting the transistors to damaging voltage stresses.
  • the cascode arrangement of the transistors is thus used to lower the voltage across each transistor.
  • the circuit based on MOS transistors is an injection circuit intended for the polarization of a photodetector connected to the input and to the transfer of the electronic charges received on the input to the at least one capacitor, said injection circuit comprising two MOS transistors mounted in cascode.
  • the circuit based on MOS transistors is an initialization circuit of the at least one capacitor, said initialization circuit comprising two MOS transistors mounted cascode.
  • the circuit based on MOS transistors is a charge pre-amplifier comprising an input stage formed of cascode-mounted MOS transistors.
  • the subject of the invention is also a detector comprising a plurality of elementary photodetectors able to create electronic charges under the effect of incident radiation, the detector comprising, associated with each of the elementary photodetectors, a device according to that previously described for the reading of the charges created by the photodetector.
  • the present invention finds an advantageous application in the detectors usually comprising electronic charge reading circuits created in their elementary photodetectors.
  • the increase of the voltage across the capacitors makes it possible in particular to improve the dynamics of the detector, the signal-to-noise ratio thereof, while preserving a long life of the transistors.
  • the figure 2 illustrates the principle of the invention applied to the reading circuit of the state of the art described in connection with the figure 1 .
  • each MOS transistor 18, 29, 42, 48 and 50 of the figure 1 whose operating voltage limits the voltage applicable across the capacitors 20 and 36, is respectively replaced by a corresponding mounting 100-108 consisting of two cascoded MOS transistors 110-128 of the same kind, each of the assemblies 100-108 filling the same function that the transistor it replaces.
  • each of the transistors 110, 112 of the assembly 100 forming the injection circuit thus sees half the voltage applied between the terminals 22 and 26.
  • each of the transistors 114, 116 of the assembly 102 forming the initialization circuit of the storage capacitor 20 sees half of the voltage between the terminal 26 and the constant potential "V +".
  • the transistors 118, 120, 122, 124, 126, 128 see half of the voltage applied across their mounting 104, 106, 108 respectively.
  • the reading circuits described in relation to the Figures 1 and 2 are given as an illustration. It will of course be understood that the present invention applies to any type of device for reading electrical charges comprising capacitors and MOS transistors, the operating voltages of which are limited, and this whatever the operating mode of the reading circuit. , and in particular the operating modes "IWR" (simultaneous integration and reading), and “ITR” (integration then successive reading).
  • the invention can be applied only to the input stage 14 of the read circuit 10.

Abstract

The device (10) has an input for receiving electronic charges, and capacitors (20, 36) for storing the charges. Maximum operating voltage of metal oxide semiconductor transistor based circuits (100-108) determines maximum voltage at terminals of the capacitors. The transistor based circuits are respectively constituted of metal oxide semiconductor transistors (110-128) connected in a cascoded manner. An independent claim is also included for a detector comprising elementary photodetectors for creating electronic charges under an effect of incident radiation.

Description

DOMAINE DE L'INVENTIONFIELD OF THE INVENTION

La présente invention a trait au domaine de la lecture de charges électroniques créées par exemple dans des photodétecteurs élémentaires d'un détecteur, notamment des photodiodes.The present invention relates to the field of reading electronic charges created for example in elementary photodetectors of a detector, in particular photodiodes.

ETAT DE LA TECHNIQUESTATE OF THE ART

Il est connu d'utiliser des photodétecteurs élémentaires, notamment des photodiodes, pour détecter un rayonnement électromagnétique. Le rayonnement électromagnétique incident sur une photodiode crée en effet des charges électroniques dans celle-ci. Ces charges sont usuellement collectées et accumulées dans une capacité de stockage pour pouvoir être lues par la suite.It is known to use elementary photodetectors, especially photodiodes, for detecting electromagnetic radiation. The electromagnetic radiation incident on a photodiode indeed creates electronic charges in it. These charges are usually collected and accumulated in a storage capacity to be read later.

La figure 1 illustre un circuit de lecture 10 des charges électriques créées dans une photodiode 12 d'un détecteur matriciel sous l'effet d'un rayonnement infrarouge « RE » incident sur celle-ci. Le circuit de lecture 10 comporte classiquement un étage d'entrée 14 pour le stockage des charges créées dans la photodiode 12, et un étage de lecture 16 des charges stockées.The figure 1 illustrates a circuit 10 for reading electric charges created in a photodiode 12 of a matrix detector under the effect of an infrared radiation "RE" incident thereon. The read circuit 10 conventionally comprises an input stage 14 for storing the charges created in the photodiode 12 , and a read stage 16 of the stored charges.

L'étage d'entrée 12 comprend un transistor MOS à canal n d'injection 18 et un condensateur de stockage 20. La source du transistor d'injection 18 est connectée à une borne 22 de la photodiode 12, la seconde borne 24 de la photodiode 12 étant par ailleurs connectée à un potentiel constant, comme la masse par exemple. Comme cela est connu en soi, le transistor d'injection 18 a pour fonction de polariser la photodiode 12 et de transférer les charges créées dans celle-ci dans le condensateur de stockage 20, qui est connecté par une borne 26 au drain du transistor 18 et par l'autre borne 28 à la masse.The input stage 12 comprises a n-channel injection MOS transistor 18 and a storage capacitor 20 . The source of the injection transistor 18 is connected to a terminal 22 of the photodiode 12 , the second terminal 24 of the photodiode 12 is also connected to a constant potential, such as the ground for example. As is known per se, the function of the injection transistor 18 is to bias the photodiode 12 and to transfer the charges created therein to the storage capacitor 20 , which is connected by a terminal 26 to the drain of the transistor 18 and by the other terminal 28 to the ground.

L'étage d'entrée 12 comporte également un transistor MOS à canal p d'initialisation 29, dont le drain est connecté à la borne 26 du condensateur de stockage 20, et dont la source est connecté à un potentiel constant « V+ » égal à Vdda - Vsat, où « Vdda » est une tension constante prédéterminée d'alimentation du circuit de lecture 10 et « Vsat » est la tension de saturation du transistor 29. Comme cela est connu, le transistor d'initialisation 29 a pour fonction de décharger le condensateur de stockage 20 avant une accumulation de charges dans celui-ci.The input stage 12 also comprises a p-channel initialization MOS transistor 29, the drain of which is connected to the terminal 26 of the storage capacitor 20, and the source of which is connected to a constant potential "V +" equal to Vdda - Vsat, where "Vdda" is a predetermined constant power supply voltage of the reading circuit 10 and "Vsat" is the saturation voltage of the transistor 29. As known, the initialization transistor 29 has the function of discharging storage capacitor 20 prior to charge accumulation therein.

L'étage de lecture 16 comporte quant à lui un interrupteur 30 connecté à la borne 26 du condensateur de stockage 20, par exemple formé d'un transistor MOS à canal n 32 et d'un transistor MOS à canal p 34, un condensateur de lecture 36 connecté par une borne 38 à l'interrupteur 30 et par l'autre borne 40 à la masse, un transistor MOS à canal p d'initialisation 42, dont la source est connecté au potentiel constant « V+ », et dont le drain est connecté à la borne 38 du condensateur de lecture 36, et un préamplificateur de charge 44. The read stage 16 comprises a switch 30 connected to the terminal 26 of the storage capacitor 20 , for example formed of an n-channel MOS transistor 32 and a p-channel MOS transistor 34, a capacitor of FIG. reading 36 connected by a terminal 38 to the switch 30 and the other terminal 40 to the ground, a p-channel initialization MOS transistor 42, whose source is connected to the constant potential "V +", and whose drain is connected to the terminal 38 of the read capacitor 36 , and a charge preamplifier 44.

Le préamplificateur 44 comprend par exemple un amplificateur opérationnel 46, un premier transistor MOS à canal n 48, dont la grille est connectée à la borne 38 du condensateur de lecture 36, et dont le drain est connecté à une première borne d'entrée de l'amplificateur 46, et un second transistor MOS à canal n 50 dont le drain est connecté à la source dudit premier transistor 48 et dont la source est connectée à la seconde borne d'entrée de l'amplificateur 46, et dont la grille reçoit un signal d'adressage « @ » correspondant à la colonne du détecteur matriciel à laquelle la photodiode 12 appartient.The preamplifier 44 comprises, for example, an operational amplifier 46 , a first n-channel MOS transistor 48 , whose gate is connected to the terminal 38 of a read capacitor 36 , and whose drain is connected to a first input terminal of FIG. the amplifier 46 , and a second n-channel MOS transistor 50 whose drain is connected to the source of said first transistor 48 and whose source is connected to the second input terminal of the amplifier 46, and whose gate receives an addressing signal "@" corresponding to the column of the matrix detector to which the photodiode 12 belongs.

En fonctionnement, la photodiode 12 est polarisée par le transistor d'injection 18 et les charges créées dans ladite photodiode sont stockées dans le condensateur 20, qui a été préalablement déchargé au moyen du transistor d'initialisation 29, l'interrupteur 30 étant par ailleurs ouvert.In operation, the photodiode 12 is biased by the injection transistor 18 and the charges created in said photodiode are stored in the capacitor 20 , which has been previously discharged by means of the initialization transistor 29, the switch 30 being moreover open.

Une fois la durée d'exposition prédéterminée écoulée, l'interrupteur 30 est fermé. Les charges stockées dans le condensateur 20 sont alors transférées au condensateur de lecture 36, préalablement initialisé au moyen du transistor 42, puis amplifiées par le préamplificateur 44 pour être délivrées par exemple sur un bus.Once the predetermined exposure time has elapsed, the switch 30 is closed. The charges stored in the capacitor 20 are then transferred to the read capacitor 36, previously initialized by means of the transistor 42, and then amplified by the preamplifier 44 to be delivered for example on a bus.

La charge électrique totale Q stockable dans chacun des condensateurs de stockage et de lecture 20, 36 est déterminée selon la relation Q = CV, où C est la capacité du condensateur et V la tension aux bornes de celui-ci, ici sensiblement égale à « Vdda-Vsat ».The total electric charge Q storable in each of the storage and read capacitors 20, 36 is determined according to the relation Q = CV, where C is the capacity of the capacitor and V the voltage across it, here substantially equal to Vdda-Vsat ".

Pour augmenter la charge totale stockage Q, afin par exemple d'augmenter la dynamique du détecteur ou améliorer le rapport signal sur bruit de celui-ci, il est donc nécessaire d'augmenter la capacité C des condensateurs 20, 36 et/ou la tension V aux bornes de ceux-ci.To increase the total storage charge Q, for example to increase the dynamics of the detector or improve the signal-to-noise ratio thereof, it is therefore necessary to increase the capacitance C of the capacitors 20, 36 and / or the voltage V at the terminals of these.

Or, comme cela est connu en soi, un circuit de lecture de charges électroniques est associé à chaque photodiode d'un détecteur matriciel, de sorte que ledit circuit est usuellement formé sur une surface réduite, notamment pour des raisons de compacité. La capacité C d'un condensateur dépendant de la surface allouée à celui-ci, l'augmentation de la capacité va donc à l'encontre du critère de compacité.However, as is known per se, an electronic charge reading circuit is associated with each photodiode of a matrix detector, so that said circuit is usually formed on a reduced surface, in particular for reasons of compactness. The capacitance C of a capacitor depending on the area allocated thereto, the increase in capacity therefore goes against the criterion of compactness.

Par ailleurs, l'augmentation de la tension aux bornes des condensateurs implique de soumettre les transistors 18, 29, 42, 48 et 50 à des tensions plus élevées. Or, les transistors sont usuellement conçus pour fonctionner sous une tension maximale prédéfinie, afin de garantir la fiabilité de ces composants. Augmenter la tension aux bornes des condensateurs pour augmenter la charge totale stockable impose donc de soumettre les transistors MOS 18, 29, 42, 48, 50 à des contraintes de tension réduisant leur durée de vie, voire susceptible de les détruire. De fait, la tension maximale de fonctionnement des transistors 18, 29, 42, 48, 50 détermine la tension maximale applicable aux bornes des condensateurs 20, 36. Moreover, the increase of the voltage across the capacitors involves subjecting the transistors 18, 29, 42, 48 and 50 to higher voltages. However, the transistors are usually designed to operate at a predetermined maximum voltage, in order to guarantee the reliability of these components. Increasing the voltage across the capacitors to increase the total storable charge therefore requires to subject the MOS transistors 18, 29, 42, 48, 50 to voltage constraints reducing their life, or even likely to destroy them. In fact, the maximum operating voltage of the transistors 18, 29, 42, 48, 50 determines the maximum voltage applicable across the capacitors 20, 36.

EXPOSE DE L'INVENTIONSUMMARY OF THE INVENTION

Le but de la présente invention est de résoudre le problème susmentionné en proposant un dispositif pour la lecture de charges électriques de conception simple et compact, permettant d'augmenter sensiblement la charge totale stockable dans les condensateurs sans soumettre les transistors à de fortes contraintes en termes de tension.The object of the present invention is to solve the aforementioned problem by proposing a device for reading electric charges of simple and compact design, to substantially increase the total charge storable in the capacitors without subjecting the transistors to strong constraints in terms of Of voltage.

A cet effet, l'invention a pour objet un dispositif pour la lecture de charges électroniques, comportant une entrée pour la réception des charges électroniques, au moins un condensateur pour le stockage des charges électroniques et au moins un circuit à base de transistors MOS dont la tension maximale de fonctionnement détermine la tension maximale aux bornes du au moins un condensateur.For this purpose, the subject of the invention is a device for reading electronic charges, comprising an input for receiving electronic charges, at least one capacitor for storing electronic charges and at least one circuit based on MOS transistors whose the maximum operating voltage determines the maximum voltage across the at least one capacitor.

Selon l'invention, le ou chaque circuit à base de transistors MOS est constitué de transistors cascodés.According to the invention, the or each circuit based on MOS transistors consists of cascoded transistors.

Comme cela est connu en soi, par transistors « cascodés », on entend des transistors connectés en série, le drain d'un transistor étant connecté à la source d'un autre transistor.As is known per se, "cascoded" transistors are understood to mean transistors connected in series, the drain of one transistor being connected to the source of another transistor.

En d'autres termes, les transistors MOS du dispositif de lecture de charges électriques, dont la tension de fonctionnement limite la tension applicable aux bornes des condensateurs, sont cascodés avec au moins un autre transistor MOS.In other words, the MOS transistors of the electric charge reading device, whose operating voltage limits the voltage applicable across the capacitors, are cascoded with at least one other MOS transistor.

Ainsi, chaque transistor voit à ses bornes une tension moindre. Par exemple, pour un montage de deux transistors montés en cascode, chacun des transistors voit la moitié de la tension totale appliquée au montage. La tension maximale de fonctionnement d'un tel montage étant supérieure à la tension maximale d'un transistor seul, il est possible d'augmenter la tension aux bornes des condensateurs sans soumettre les transistors à des contraintes de tension dommageables.Thus, each transistor sees at its terminals a lower voltage. For example, for mounting two transistors cascode mounted, each of the transistors sees half of the total voltage applied to the assembly. Since the maximum operating voltage of such an arrangement is greater than the maximum voltage of a single transistor, it is possible to increase the voltage across the capacitors without subjecting the transistors to damaging voltage stresses.

L'agencement en cascode des transistors est donc utilisé pour abaisser la tension aux bornes de chaque transistor.The cascode arrangement of the transistors is thus used to lower the voltage across each transistor.

Selon un mode de réalisation particulier de l'invention, le circuit à base de transistors MOS est un circuit d'injection destiné à la polarisation d'un photodétecteur connecté à l'entrée et au transfert des charges électroniques reçues sur l'entrée vers le au moins un condensateur, ledit circuit d'injection comportant deux transistors MOS montés en cascode.According to a particular embodiment of the invention, the circuit based on MOS transistors is an injection circuit intended for the polarization of a photodetector connected to the input and to the transfer of the electronic charges received on the input to the at least one capacitor, said injection circuit comprising two MOS transistors mounted in cascode.

Selon un mode de réalisation particulier de l'invention, le circuit à base de transistors MOS est un circuit d'initialisation du au moins un condensateur, ledit circuit d'initialisation comportant deux transistors MOS montés en cascode.According to a particular embodiment of the invention, the circuit based on MOS transistors is an initialization circuit of the at least one capacitor, said initialization circuit comprising two MOS transistors mounted cascode.

Selon un mode de réalisation particulier de l'invention, le circuit à base de transistors MOS est un préamplificateur de charges comportant un étage d'entrée formé de transistors MOS montés en cascode.According to a particular embodiment of the invention, the circuit based on MOS transistors is a charge pre-amplifier comprising an input stage formed of cascode-mounted MOS transistors.

L'invention a également pour objet un détecteur comportant une pluralité de photodétecteurs élémentaires aptes à créer des charges électroniques sous l'effet d'un rayonnement incident, le détecteur comportant, associé à chacun des photodétecteurs élémentaires, un dispositif conforme à celui précédemment décrit pour la lecture des charges créées par le photodétecteur.The subject of the invention is also a detector comprising a plurality of elementary photodetectors able to create electronic charges under the effect of incident radiation, the detector comprising, associated with each of the elementary photodetectors, a device according to that previously described for the reading of the charges created by the photodetector.

En d'autres termes, la présente invention trouve une application avantageuse dans les détecteurs comportant usuellement des circuits de lecture de charges électroniques créées dans leurs photodétecteurs élémentaires. L'augmentation de la tension aux bornes des condensateurs permet notamment d'améliorer la dynamique du détecteur, le rapport signal sur bruit de celui-ci, tout en préservant une grande durée de vie des transistors.In other words, the present invention finds an advantageous application in the detectors usually comprising electronic charge reading circuits created in their elementary photodetectors. The increase of the voltage across the capacitors makes it possible in particular to improve the dynamics of the detector, the signal-to-noise ratio thereof, while preserving a long life of the transistors.

BREVE DESCRIPTION DES FIGURESBRIEF DESCRIPTION OF THE FIGURES

L'invention sera mieux comprise à la lecture de la description qui va suivre, donnée uniquement à titre d'exemple, et réalisée en relation avec les dessins annexés dans lesquels des références identiques désignent des éléments identiques ou analogues, et dans lesquels :

  • la figure 1 est une vue schématique d'un circuit de lecture de l'état antérieur de la technique associé à une photodiode, ce circuit ayant été décrit dans le préambule ; et
  • la figure 2 est une vue schématique d'un circuit de lecture selon l'invention.
The invention will be better understood on reading the description which will follow, given solely by way of example, and made with reference to the appended drawings in which identical references designate identical or similar elements, and in which:
  • the figure 1 is a schematic view of a readout circuit of the prior art associated with a photodiode, this circuit having been described in the preamble; and
  • the figure 2 is a schematic view of a read circuit according to the invention.

DESCRIPTION DETAILLEE DE L'INVENTIONDETAILED DESCRIPTION OF THE INVENTION

La figure 2 illustre le principe de l'invention appliqué au circuit de lecture de l'état de la technique décrit en relation avec la figure 1.The figure 2 illustrates the principle of the invention applied to the reading circuit of the state of the art described in connection with the figure 1 .

Selon l'invention, chaque transistor MOS 18, 29, 42, 48 et 50 de la figure 1, dont la tension de fonctionnement limite la tension applicable aux bornes des condensateurs 20 et 36, est remplacé respectivement par un montage 100-108 correspondant constitué de deux transistors MOS cascodés 110-128 de même nature, chacun des montages 100-108 remplissant la même fonction que le transistor qu'il remplace.According to the invention, each MOS transistor 18, 29, 42, 48 and 50 of the figure 1 , whose operating voltage limits the voltage applicable across the capacitors 20 and 36, is respectively replaced by a corresponding mounting 100-108 consisting of two cascoded MOS transistors 110-128 of the same kind, each of the assemblies 100-108 filling the same function that the transistor it replaces.

Grâce à l'agencement en cascode, chacun des transistors 110, 112 du montage 100 formant le circuit d'injection, voit ainsi la moitié de la tension appliquée entre les bornes 22 et 26. De même, chacun des transistors 114, 116 du montage 102 formant circuit d'initialisation du condensateur de stockage 20, voit la moitié de la tension entre la borne 26 et le potentiel constant « V+ ».Thanks to the cascode arrangement, each of the transistors 110, 112 of the assembly 100 forming the injection circuit, thus sees half the voltage applied between the terminals 22 and 26. Similarly, each of the transistors 114, 116 of the assembly 102 forming the initialization circuit of the storage capacitor 20, sees half of the voltage between the terminal 26 and the constant potential "V +".

De manière analogue, les transistors 118, 120, 122, 124, 126, 128 voient la moitié de la tension appliquée aux bornes de leur montage 104, 106, 108 respectif.Similarly, the transistors 118, 120, 122, 124, 126, 128 see half of the voltage applied across their mounting 104, 106, 108 respectively.

Il est ainsi possible d'augmenter la tension d'alimentation « Vdda » du circuit de lecture 10, et par conséquent la tension appliquée aux bornes des condensateurs 20 et 36 sans que la tension résultante aux bornes des transistors 110-128 ne dépasse la tension maximale de fonctionnement de ceux-ci. Par exemple, une augmentation de 100 pourcents de la tension d'alimentation « Vdda » est possible.It is thus possible to increase the supply voltage "Vdda" of the reading circuit 10, and therefore the voltage applied across the capacitors 20 and 36 without the resulting voltage across the transistors 110-128 exceeds the voltage maximum operation of these. For example, a 100 percent increase in supply voltage "Vdda" is possible.

Ce faisant, en raison de cette augmentation de la tension aux bornes des condensateurs, il devient possible d'augmenter la capacité de stockage des charges dans chacune de celles-ci, en application de la relation Q = CV.In doing so, because of this increase in the voltage across the capacitors, it becomes possible to increase the storage capacity of the charges in each of them, in application of the relationship Q = CV.

Bien évidemment, les circuits de lecture décrits en relation avec les figures 1 et 2 sont donnés à titre d'illustration. On comprendra bien évidemment que la présente invention s'applique à tout type de dispositif de lecture de charges électriques comprenant des condensateurs et des transistors MOS, dont les tensions de fonctionnement sont limitées, et cela quel que soit le mode de fonctionnement du circuit de lecture, et notamment les modes de fonctionnement « IWR » (intégration et lecture simultanées), et « ITR » (intégration puis lecture successive).Of course, the reading circuits described in relation to the Figures 1 and 2 are given as an illustration. It will of course be understood that the present invention applies to any type of device for reading electrical charges comprising capacitors and MOS transistors, the operating voltages of which are limited, and this whatever the operating mode of the reading circuit. , and in particular the operating modes "IWR" (simultaneous integration and reading), and "ITR" (integration then successive reading).

De même, l'invention peut s'appliquer uniquement à l'étage d'entrée 14 du circuit de lecture 10. Similarly, the invention can be applied only to the input stage 14 of the read circuit 10.

De même, il est possible d'utiliser plus de deux transistors cascodés pour chaque montage en fonction des besoins spécifiques de chaque application.Similarly, it is possible to use more than two cascoded transistors for each assembly according to the specific needs of each application.

Claims (5)

Dispositif (10) pour la lecture de charges électroniques, comportant une entrée pour la réception des charges électroniques, au moins un condensateur (20, 36) pour le stockage des charges électroniques et au moins un circuit à base de transistors MOS (100-106), dont la tension maximale de fonctionnement détermine la tension maximale aux bornes du au moins un condensateur (20, 36), caractérisé en ce que le ou chaque circuit à base de transistors MOS (100-106) est constitué de transistors montés en cascode (110-128).Device (10) for reading electronic charges, comprising an input for receiving the electronic charges, at least one capacitor (20, 36) for storing the electronic charges and at least one circuit based on MOS transistors (100-106 ), whose maximum operating voltage determines the maximum voltage across the at least one capacitor (20, 36), characterized in that the or each MOS transistor-based circuit (100-106) consists of cascode-mounted transistors (110-128). Dispositif selon la revendication 1, caractérisé en ce que le circuit à base de transistors MOS est un circuit d'injection (100) destiné à la polarisation d'un photodétecteur (12) connecté à l'entrée et au transfert des charges électroniques reçues sur l'entrée vers le au moins un condensateur (20), ledit circuit d'injection (100) comportant deux transistors MOS montés en cascode (110, 112).Device according to Claim 1, characterized in that the circuit based on MOS transistors is an injection circuit (100) intended for the polarization of a photodetector (12) connected to the input and to the transfer of the electronic charges received on the input to the at least one capacitor (20), said injection circuit (100) having two cascode-mounted MOS transistors (110, 112). Dispositif selon la revendication 1, caractérisé en ce le circuit à base de transistors MOS est un circuit d'initialisation (102) du au moins un condensateur (20), ledit circuit d'initialisation (102) comportant deux transistors MOS montés en cascode (114, 116).Device according to claim 1, characterized in that the circuit based on MOS transistors is an initialization circuit (102) of the at least one capacitor (20), said initialization circuit (102) comprising two cascode-mounted MOS transistors ( 114, 116). Dispositif selon la revendication 1, caractérisé en ce le circuit à base de transistors MOS est un préamplificateur de charges (44) comportant un étage d'entrée formé de transistors MOS montés en cascode (122-128).Device according to claim 1, characterized in that the circuit based on MOS transistors is a charge preamplifier (44) having an input stage formed of cascode MOS transistors (122-128). Détecteur comportant une pluralité de photodétecteurs élémentaires aptes à créer des charges électroniques sous l'effet d'un rayonnement incident, le détecteur comportant, associé à chacun des photodétecteurs, un dispositif conforme à l'une quelconque des revendications précédentes pour la lecture des charges créées par le photodétecteur.Detector comprising a plurality of elementary photodetectors able to create electronic charges under the effect of incident radiation, the detector comprising, associated with each of the photodetectors, a device according to any one of the preceding claims for reading the charges created by the photodetector.
EP20090305736 2008-09-02 2009-08-06 Device for reading electronic loads and detector comprising such devices Pending EP2160011A1 (en)

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FR0855884A FR2935577B1 (en) 2008-09-02 2008-09-02 DEVICE FOR READING ELECTRONIC LOADS AND SENSOR COMPRISING SUCH DEVICES

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Citations (5)

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Publication number Priority date Publication date Assignee Title
US4317055A (en) * 1978-05-24 1982-02-23 Hitachi, Ltd. High-voltage circuit for insulated gate field-effect transistor
US5486790A (en) * 1994-02-10 1996-01-23 Philips Electronics North America Corporation Multistage amplifier with hybrid nested miller compensation
US20030142549A1 (en) * 2002-01-29 2003-07-31 Michael Rowlandson Non-volatile memory element having a cascoded transistor scheme to reduce oxide field stress
US6690000B1 (en) * 1998-12-02 2004-02-10 Nec Corporation Image sensor
WO2007085942A2 (en) * 2006-01-25 2007-08-02 Melexis Nv Image sensor with a photodiode readout circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4317055A (en) * 1978-05-24 1982-02-23 Hitachi, Ltd. High-voltage circuit for insulated gate field-effect transistor
US5486790A (en) * 1994-02-10 1996-01-23 Philips Electronics North America Corporation Multistage amplifier with hybrid nested miller compensation
US6690000B1 (en) * 1998-12-02 2004-02-10 Nec Corporation Image sensor
US20030142549A1 (en) * 2002-01-29 2003-07-31 Michael Rowlandson Non-volatile memory element having a cascoded transistor scheme to reduce oxide field stress
WO2007085942A2 (en) * 2006-01-25 2007-08-02 Melexis Nv Image sensor with a photodiode readout circuit

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FR2935577B1 (en) 2010-10-08
CN101666678A (en) 2010-03-10
FR2935577A1 (en) 2010-03-05
IL200196A0 (en) 2010-04-29

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