Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D10/00—Bipolar junction transistors [BJT]
  • H10D10/80—Heterojunction BJTs
  • H10D10/821—Vertical heterojunction BJTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/80—FETs having rectifying junction gate electrodes
  • H10D30/801—FETs having heterojunction gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/05—Manufacture or treatment characterised by using material-based technologies using Group III-V technology
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
  • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

Definitions

• This invention relates generally to semiconductor components, and relates more particularly to transistor integration in semiconductor components.
• a majority of the existing techniques require at least two distinct epitaxial growth steps with intervening wafer processing, making them prohibitively expensive for cost- sensitive applications. Furthermore, ion implantation is not practical for forming reliable p-n junctions in GaAs because gallium and arsenic vacancies and interstitials created by such ion implantation cannot be completely removed by a subsequent anneal, leaving high concentrations of deep-level traps in the GaAs.
• Other existing integration techniques require significant wafer processing prior to an epitaxial growth step or steps, or are practical only for p-n-p bipolar transistors and n-channel junction field effect transistors. Such techniques are expensive, poorly reproducible, and incompatible with large segments of the transistor market.
• FIG. 1 is a cross-sectional view of a portion of a semiconductor component at a particular point in a manufacturing process according to an embodiment of the invention
• FIG. 2 is a cross-sectional view of the semiconductor component of FIG. 1 at a later point in the manufacturing process according to an embodiment of the invention
• FIG. 3 is a cross-sectional view of the semiconductor component of FIG. 2 at a later point in the manufacturing process according to an embodiment of the invention
• FIG. 4 is' a cross-sectional view of the semiconductor component of FIG.
• FIG. 5 is a cross-sectional view of the semiconductor component of FIG. 4 at a later point in the manufacturing process according to an embodiment of the invention
• FIG. 6 is a cross-sectional view of the semiconductor component of FIG. 5 at a later point in the manufacturing process according to an embodiment of the invention
• FIG. 7 is a cross-sectional view of the semiconductor component of FIG. 6 at a later point in the manufacturing process according to an embodiment of the invention
• FIG. 8 is a cross-sectional view of a semiconductor component according to a different embodiment of the invention
• FIG. 9 is a flow chart illustrating a method of manufacturing a semiconductor component according to an embodiment of the invention.
• FIG. 10 is a diagram illustrating a circuit comprising a semiconductor component according to an embodiment of the invention.
• the drawing figures illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the invention.
• elements in the drawing figures are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention.
• the same reference numerals in different figures denote the same elements.
• the terms "first,” “second,” “third,” “fourth,” and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
• Coupled is defined as directly or indirectly connected in an electrical or non-electrical manner.
• a semiconductor component comprises: a semiconductor substrate; an epitaxial semiconductor layer above the semiconductor substrate; a bipolar transistor in the epitaxial semiconductor layer; and a field effect transistor in the epitaxial semiconductor layer.
• a portion of the epitaxial semiconductor layer forms a base of the bipolar transistor and a gate of the field effect transistor, and the portion of the epitaxial semiconductor layer has a first substantially uniform doping concentration.
• FIG. 1 is a cross-sectional view of a portion of a semiconductor component 100 at a particular point in a manufacturing process according to an embodiment of the invention.
• Semiconductor component 100 comprises a semiconductor substrate 110 and an epitaxial semiconductor layer 120 above semiconductor substrate 110.
• semiconductor substrate 110 can comprise a UI-V semiconductor, such as GaAs, indium phosphide (InP), gallium nitride (GaN), and the like.
• a direction substantially parallel to a surface of semiconductor substrate 110 is a horizontal direction.
• Epitaxial semiconductor layer 120 comprises many different portions, including a semiconductor layer 121, a semiconductor layer 122 over semiconductor layer 121, a semiconductor layer 123 over semiconductor layer 122, a semiconductor layer 124 over semiconductor layer 123, and a semiconductor layer 125 over semiconductor layer 124.
• the formation of semiconductor component 100, including the formation of epitaxial semiconductor layer 120, will be further discussed below.
• semiconductor layer can mean a single semiconductor layer or a composite semiconductor layer comprised of two or more semiconductor layers.
• Semiconductor layer 123 has a doping concentration greater than or equal to 5xl0 18 atoms per cubic centimeter, and a thickness between approximately 30 and 150 nanometers. In a particular embodiment, semiconductor layer 123 has a doping concentration between approximately 4xl0 19 and 5xl0 19 atoms per cubic centimeter and a thickness between approximately 60 and 100 nanometers.
• Semiconductor layer 124 has a doping concentration between approximately 5xl0 16 and 5xl0 18 atoms per cubic centimeter, and a thickness between approximately 30 and 300 nanometers.
• semiconductor layer 124 has a doping concentration between approximately lxlO 17 and lxlO 18 atoms per cubic centimeter.
• semiconductor layers 121, 122, 123, 124, and 125 can comprise, respectively, GaAs, GaAs, GaAs, indium gallium phosphide (L GaP), and indium gallium arsenide (InGaAs) overlying GaAs.
• semiconductor layer 124 can comprise GaAs overlying InGaP.
• FIG. 2 is a cross-sectional view of semiconductor component 100 at a later point in the manufacturing process according to an embodiment of the invention. As illustrated in FIG. 2, semiconductor component 100 further comprises a metal layer 201.
• Metal layer 201 comprises a metal region 210, a metal region 220, and a metal region 230. The purpose for and fabrication of metal layer 201, including metal regions 210, 220, and 230, will be further explained below.
• metal layer 201 can comprise an alloy of titanium, tungsten, and nitrogen.
• FIG. 3 is a cross-sectional view of semiconductor component 100 at a later point in the manufacturing process according to an embodiment of the invention. As illustrated in FIG. 3, semiconductor component 100 further comprises an ohmic contact 310, an ohmic contact 320, and an ohmic contact 330. Ohmic contacts 310, 320, and 330 are formed from semiconductor layer 125, in a manner that will be further discussed below.
• semiconductor layer 125 may be referred to as an ohmic contact region.
• FIG. 4 is a cross-sectional view of semiconductor component 100 at a later point in the manufacturing process according to an embodiment of the invention. As illustrated in FIG. 4, semiconductor component 100 further comprises a region 410 and a region 420. Regions 410 and 420 are formed from at least a portion of semiconductor layer 124, in a manner that will be further discussed below.
• FIG. 5 is a cross-sectional view of semiconductor component 100 at a later point in the manufacturing process according to an embodiment of the invention. As illustrated in FIG. 5, semiconductor component 100 further comprises a metal layer 501. Metal layer 501 comprises metal regions 510 and a metal region 520.
• metal layer 501 comprises titanium, platinum, and gold.
• metal layer 501 comprises a four-layer stack of, from bottom to top, platinum, titanium, platinum, and gold.
• FIG. 6 is a cross-sectional view of semiconductor component 100 at a later point in the manufacturing process according to an embodiment of the invention. As illustrated in FIG. 6, semiconductor component 100 further comprises a metal region 610. The purpose for and fabrication of metal region 610 will be further explained below. In one embodiment, metal region 610 is an alloy of nickel, germanium, and gold. Semiconductor component 100 still further comprises a region 620 and a region 630.
• Regions 620 and 630 are formed from at least a portion of semiconductor layer 124.
• FIG. 7 is a cross-sectional view of semiconductor component 100 at a later point in the manufacturing process according to an embodiment of the invention. As illustrated in FIG. 7, semiconductor component 100 further comprises a gap 710. The purpose for and fabrication of gap 710 will be further explained below.
• Semiconductor component 100 still further comprises a region 720, a region 730, a bipolar transistor 770 in region 720 and a field effect transistor 780 in region 730.
• Bipolar transistor 770 and field effect transistor 780 are formed in epitaxial semiconductor layer 120.
• bipolar transistor 770 is a heterojunction bipolar transistor (HBT).
• field effect transistor 780 is a junction field effect transistor (JFET).
• JFET junction field effect transistor
• Semiconductor layer 121 forms a sub-collector layer of bipolar transistor 770
• semiconductor layer 122 forms a collector layer of bipolar transistor 770.
• Semiconductor layer 123 forms a base of bipolar transistor 770 and a gate of field effect transistor 780.
• at least the portion of semiconductor layer 123 used to form the base of bipolar transistor 770 has substantially the same doping concentration in the horizontal direction as the portion of semiconductor layer 123 used to form the gate of field effect transistor 780.
• substantially the same doping concentration means there is no intentional variation of the doping concentration in the horizontal direction within the limits of the epitaxial growth procedure.
• Semiconductor layer 124 forms an emitter of bipolar transistor 770 and a channel of field effect transistor 780.
• at least the portion of semiconductor layer 124 used to form the emitter of bipolar transistor 770 has substantially the same doping concentration in the horizontal direction as the portion of semiconductor layer 124 used to form the channel of field effect transistor 780, which may be the same as or different than the aforementioned doping concentration of semiconductor layer 123.
• substantially the same doping concentration means there is no intentional variation of the doping concentration in the horizontal direction within the limits of the epitaxial growth procedure.
• Regions 410 and 420 are portions of an upper semiconductor layer of semiconductor layer 124, and regions 620 and 630 are portions of a lower semiconductor layer of semiconductor layer 124 below the upper semiconductor layer.
• portions of regions 620 and 410 in region 720 form an active area of bipolar transistor 770, and portions of regions 630 and 420 in region 730 form a channel of field effect transistor 780.
• the lower semiconductor layer and the upper semiconductor layer of semiconductor layer 124 form a heterojunction structure. Regions 620 and 630 have substantially similar doping concentrations, and regions 410 and 420 have substantially similar doping concentrations.
• the upper semiconductor layer comprises
• AlGaAs aluminum gallium arsenide
• the lower semiconductor layer comprises InGaP, or vice versa.
• the upper semiconductor layer comprises GaAs
• the lower semiconductor layer comprises InGaP
• the thickness of the lower semiconductor layer is greater than the thickness of the upper semiconductor layer.
• all or a portion of the lower semiconductor layer is removed in the vicinity of metal regions 510 and 520.
• Metal region 210 forms an emitter electrode of bipolar transistor 770.
• Metal regions 220 and 230 form source/drain electrodes of field effect transistor 780.
• Portions of semiconductor layer 125 form ohmic contact layers of bipolar transistor 770 and of field effect transistor 780.
• ohmic contact 310 can form an ohmic contact to the emitter electrode of bipolar transistor 770.
• ohmic contacts 320 and 330 can form ohmic contacts to the source/drain electrodes of field effect transistor 780.
• Metal regions 510 form a base electrode of bipolar transistor 770.
• Metal region 520 forms a gate electrode of field effect transistor 780.
• Metal region 610 forms a collector electrode of bipolar transistor 770.
• FIG. 8 is a cross-sectional view of a semiconductor component 800 according to an embodiment of the invention.
• Semiconductor component 800 is similar in many respects to semiconductor component 100, and elements of semiconductor component 800 that are also in semiconductor component 100 are indicated with the same reference numerals used in FIGs.
• semiconductor component 800 comprises a semiconductor layer 824 between semiconductor layer 123 and semiconductor layer 125, all of which are still portions of epitaxial semiconductor layer 120.
• Semiconductor layer 824 comprises a lower semiconductor layer 830 adjacent to semiconductor layer 123, a middle semiconductor layer 840 above lower semiconductor layer 830, and an upper semiconductor layer 850 above middle semiconductor layer 840 and adjacent to semiconductor layer 125.
• Lower semiconductor layer 830, middle semiconductor layer 840, and upper semiconductor layer 850 form a heterojunction structure.
• upper semiconductor layer 850 is at least as thick as the combined thicknesses of middle semiconductor layer 840 and lower semiconductor layer 830.
• Semiconductor component 800 further comprises a bipolar transistor 870 in region 720 and a field effect transistor 880 in region 730.
• Bipolar transistor 870 and field effect transistor 880 are formed in epitaxial semiconductor layer 120.
• bipolar transistor 870 is an HBT.
• field effect transistor 880 is a JFET.
• Portions of lower semiconductor layer 830, middle semiconductor layer 840, and upper semiconductor layer 850 in region 720 form an active area of bipolar transistor 870.
• Portions of lower semiconductor layer 830, middle semiconductor layer 840, and upper semiconductor layer 850 in region 730 form a channel of field effect transistor 880.
• the portion of lower semiconductor layer 830 forming the active area has a doping concentration that is substantially similar in the horizontal direction to the doping concentration of the portion of lower semiconductor layer 830 forming the channel.
• the portion of middle semiconductor layer 840 forming the active area has a doping concentration in the horizontal direction that is substantially similar to, or the same as, the doping concentration of the portion of middle semiconductor layer 840 forming the channel
• the portion of upper semiconductor layer 850 forming the active area has a doping concentration in the horizontal direction that is substantially similar to, or the same as, the doping concentration of the portion of upper semiconductor layer 850 forming the channel.
• semiconductor layer 824 comprises GaAs, InGaP, and AlGaAs
• lower semiconductor layer 830 comprises InGaP or AlGaAs
• middle semiconductor layer 840 is made up of a different material than the material that makes up lower semiconductor layer 830
• upper semiconductor layer 850 is made up of a different material than the material that makes up middle semiconductor layer 840.
• lower semiconductor layer 830 and upper semiconductor layer 850 comprise InGaP
• middle semiconductor layer 840 comprises GaAs
• the thickness of middle semiconductor layer 840 is less than the thickness of upper and lower semiconductor layers 850 and 830.
• lower semiconductor layer 830 and upper semiconductor layer 850 comprise AlGaAs.
• FIG. 9 is a flow chart illustrating a method 900 of manufacturing a semiconductor component according to an embodiment of the invention.
• the semiconductor component comprises a plurality of layers. If the doping concentrations and thicknesses of certain ones of the plurality of layers are appropriately chosen, method 900 can require only a single mask in addition to the masks required in a standard bipolar transistor manufacturing process to integrate the field effect transistor into the semiconductor component.
• a channel of a field effect transistor can be chosen such that the field effect transistor has a pinch-off voltage greater than zero, with sufficiently low sub-threshold current at zero volts.
• a step 901 of method 900 is to provide a semiconductor substrate.
• the semiconductor substrate can be similar to semiconductor substrate 110, first shown in FIG. 1.
• a step 902 of method 900 is to provide an epitaxial semiconductor layer above the semiconductor substrate.
• the epitaxial semiconductor layer can be similar to epitaxial semiconductor layer 120, first shown in FIG. 1.
• step 902 comprises providing a first semiconductor layer, providing a second semiconductor layer over the first semiconductor layer, providing a third semiconductor layer over the second semiconductor layer, providing a fourth semiconductor layer over the third semiconductor layer, providing a fifth semiconductor layer over the fourth semiconductor layer, and providing a sixth semiconductor layer over the fifth semiconductor layer.
• the first, second, and third semiconductor layers can be similar to, respectively, semiconductor layer 121, semiconductor layer 122, and semiconductor layer 123, first shown in FIG. 1.
• the fourth semiconductor layer can be similar to regions 620 and 630, first shown in FIG. 6, or to semiconductor layer 830, first shown in FIG. 8, and the fifth semiconductor layer can be similar to regions 410 and 420, first shown in FIG. 4, or to semiconductor layers 840 and 850, first shown in FIG. 8. Accordingly, the fourth and fifth semiconductor layers together can be similar to semiconductor layer 124, first shown in FIG. 1.
• the sixth semiconductor layer can be similar to semiconductor layer 125, first shown in FIG. 1.
• Step 902 can further comprise forming each one of the first, second, third, fourth, fifth, and sixth semiconductor layers before patterning any of the first, second, third, fourth, fifth, and sixth semiconductor layers.
• a step 903 of method 900 is to deposit and pattern a first metal layer above the epitaxial semiconductor layer.
• the first metal layer can be similar to metal layer 201, first shown in FIG. 2.
• the depositing and patterning processes used in step 903 and subsequent steps are well known in the art, and can include an etch process, a lift-off process, and the like.
• performing step 903 can form metal regions 210, 220, and 230, first shown in FIG. 2.
• a step 904 of method 900 is to etch a portion of the sixth semiconductor layer to expose a portion of the fifth semiconductor layer.
• performing step 904 can form ohmic contacts 310, 320, and 330, first shown in FIG. 3.
• step 904 comprises selectively etching a portion of the sixth semiconductor layer.
• the properties of the fifth and sixth semiconductor layers are sufficiently different that an etch process can selectively remove the portion of the sixth semiconductor layer without significantly affecting the fifth semiconductor layer.
• the thickness and doping concentration of the fifth semiconductor layer can be chosen to provide desired electrical properties for the semiconductor component or portion thereof.
• steps 905 and/or 907, described below, or another etch step can also comprise a selective etch.
• a step 905 of method 900 is to etch the portion of the fifth semiconductor layer to expose a portion of the fourth semiconductor layer.
• performing step 905 can form regions 410 and 420, first shown in FIG. 4.
• a step 906 of method 900 is to deposit and pattern a second metal layer above the portion of the fourth semiconductor layer.
• the second metal layer can be similar to metal layer 501, first shown in FIG. 5.
• performing step 906 forms metal regions 510 and 520, first shown in FIG. 5.
• a step 907 of method 900 is to etch a portion of the portion of the fourth semiconductor layer, a portion of the third semiconductor layer, and a portion of the second semiconductor layer to expose a portion of the first semiconductor layer.
• step 907 can be performed before step 906.
• step 906 is modified in that step 906 deposits and patterns the second metal layer above the third semiconductor layer rather than above the portion of the fourth semiconductor layer.
• a step 908 of method 900 is to deposit and pattern a third metal layer above the portion of the first semiconductor layer.
• performing step 908 forms metal region 610, first shown in FIG. 6.
• a step 909 of method 900 is to use a portion of the epitaxial semiconductor layer to form a base of a bipolar transistor.
• the portion of the epitaxial semiconductor layer can be similar to semiconductor layer 123, first shown in FIG. 1.
• the bipolar transistor can be similar to bipolar transistor 770 in FIG. 7.
• the bipolar transistor can be similar to bipolar transistor 870 in FIG. 8.
• a step 910 of method 900 is to use the portion of the epitaxial semiconductor layer to form a gate of a field effect transistor.
• the field effect transistor can be similar to field effect transistor 780 in FIG. 7.
• the field effect transistor can be similar to field effect transistor 880 in FIG. 8.
• a step 911 of method 900 is to alloy the aforementioned metal regions, which form the base, collector, emitter, gate, source, and drain electrodes.
• a step 912 of method 900 is to electrically isolate the bipolar transistor from the field effect transistor.
• step 912 can be accomplished by etching away a portion of the portion of the first semiconductor layer, and, in at least one embodiment, also etching away a portion of the semiconductor substrate. Performing step 912 in this fashion forms gap 710, first shown in FIG. 7.
• step 912 can be accomplished by implanting a dopant having a conductivity type opposite the conductivity type of the first semiconductor layer or the semiconductor substrate, or by implanting a non-dopant, such as oxygen, argon, or the like.
• step 912 can be accomplished by performing both the etch step and one or both implant steps described above. In one embodiment, step 912 can be performed before steps 909, 910, and 911.
• a step 913 of method 900 is to use a different portion of the epitaxial semiconductor layer to form an emitter of the bipolar transistor.
• the different portion of the epitaxial semiconductor layer can comprise the fourth semiconductor layer and the fifth semiconductor layer, and can be similar to semiconductor layer 124, first shown in FIG. 1, or to semiconductor layer 824, first shown in FIG. 8.
• a step 914 of method 900 is to use the different portion of the epitaxial semiconductor layer to form a channel of the field effect transistor.
• Semiconductor component 100 and semiconductor component 800 are two embodiments of a field effect transistor that has been integrated into a bipolar transistor platform according to embodiments of the invention. As explained above, for certain applications it is desirable to integrate a JFET into a GaAs HBT technology.
• bias circuit in an HBT power amplifier such as is commonly used in mobile telephones.
• One embodiment of such a bias circuit is shown in FIG. 10.
• the most commonly used bias circuits require two transistors in series.
• the voltage drop associated with using two GaAs HBT emitter-base junctions in series is too large to be practical with the low reference voltage available in mobile telephones.
• Existing products address the excessive voltage drop issue by using a low-control-voltage transistor from a different process technology.
• this approach requires an additional die, increasing both the size and the cost of the power amplifier module.
• this approach increases the size of each GaAs die, because the additional bond pads needed to interface with the off-chip bias circuit are larger than the bias circuit itself.
• FIG. 10 is a diagram illustrating a bias circuit 1000 comprising a semiconductor component according to an embodiment of the invention, h one embodiment, bias circuit 1000 is a power amplifier bias circuit such as is commonly used in mobile telephones.
• Bias circuit 1000 comprises a bipolar transistor 1070 and a field effect transistor 1080.
• bipolar transistor 1070 can be similar to bipolar transistor 770 in FIG. 7 or to bipolar transistor 870 in FIG.
• Bias circuit 1000 further comprises a reference voltage pin 1010, and a supply voltage pin 1020, a supply voltage pin 1030.
• An arrow 1040 indicates a direction of a bias current.
• An arrow 1050 indicates a direction of a current equal to the bias current multiplied by a scale factor.

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• Bipolar Transistors (AREA)
• Junction Field-Effect Transistors (AREA)
• Bipolar Integrated Circuits (AREA)

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• 2003
  • 2003-08-29 US US10/651,544 patent/US6919590B2/en not_active Expired - Lifetime
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