WO2004112129A1 - Dispositif electronique - Google Patents

Dispositif electronique Download PDF

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Publication number
WO2004112129A1
WO2004112129A1 PCT/JP2004/008458 JP2004008458W WO2004112129A1 WO 2004112129 A1 WO2004112129 A1 WO 2004112129A1 JP 2004008458 W JP2004008458 W JP 2004008458W WO 2004112129 A1 WO2004112129 A1 WO 2004112129A1
Authority
WO
WIPO (PCT)
Prior art keywords
electronic device
circuit board
housing
electronic
substrate
Prior art date
Application number
PCT/JP2004/008458
Other languages
English (en)
Japanese (ja)
Inventor
Takehide Yokozuka
Masahide Harada
Shiro Yamashita
Kaoru Uchiyama
Syuuji Eguchi
Masahiko Asano
Koji Sato
Isamu Yoshida
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO2004112129A1 publication Critical patent/WO2004112129A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09054—Raised area or protrusion of metal substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink

Definitions

  • the present invention relates to an electronic device that requires a high heat dissipation structure, such as a electronic unit.
  • the two boards, the motherboard and the interposer board are sandwiched between the electronic component that is a heat source and the housing that is the heat radiation destination, the electronic components are mounted on a conventional motherboard.
  • the heat radiation is lower than that of the structure in which the device is directly mounted.
  • a metal core substrate in which a wiring layer and an insulating layer are formed on both sides of a metal plate as a core material is used for an interposer substrate.
  • the resin layer on both sides of the interposer substrate and a part of the wiring layer are removed, and the semiconductor device as an electronic component is directly mounted on the upper surface of the core material in a face-up manner, and the lower surface of the core material and the upper surface of the motherboard are removed.
  • the sides are connected by soldering and plating (Patent Document 1, FIG. 34).
  • a housing and an electronic board adhered to the housing are provided.
  • the electronic board includes a first circuit board (interposer board) on which electronic components are mounted, and the first circuit board.
  • the first circuit board and the second circuit board are provided. Can be arranged at the center of the second circuit board. That is, since the heat radiating member can be arranged directly below the electronic component as the heat radiating source, the heat radiating property is improved.
  • FIG. 2 is a perspective view of an ECU module.
  • FIG. 6 is a cross-sectional view of the electronic device.
  • FIG. 7 is a diagram showing a manufacturing process.
  • FIG. 8 is a cross-sectional view of the electronic device.
  • FIG. 9 is a cross-sectional view of the electronic device.
  • the ECU module is an aluminum housing on which a connector for inputting and outputting signals to and from the outside is formed.
  • FIG. 1 is a cross-sectional view of FIG.
  • the heat generated by the semiconductor device 1 causes the interposer substrate 11 to be confined.
  • Heat can be dissipated to the case with high heat conductivity through a short heat dissipation path formed of a material with high heat conductivity. For this reason, the heat dissipation of the electronic device can be improved.
  • a 5 mm square semiconductor device 1 is placed face-up on the surface of the interposer substrate 11 and die-bonded with solder or silver paste 5. After die bonding, the terminals of the semiconductor device 1 and the pads of the interposer substrate 11 are electrically connected by the bonding wires 3. Next, the electronic components 9 are mounted. Note that this connection method is appropriately selected according to the type of electronic component.
  • the semiconductor package 41 and the electronic component 21 are mounted in a predetermined position on the motherboard 15 in alignment with each other. At 240 ° C, the solder is melted for about 5 minutes, and reflow connection is performed (Fig. 3 ( c)). The size of the through hole was 7 mm square. Since the aluminum projection 29 is provided in the through hole 43 of the mother board 15, by making the opening larger than the size of the aluminum projection 29, the positioning accuracy of the board with respect to the housing 27 is improved. This is effective in alleviating the conditions described above and forming a space for storing an excess of the adhesive 31 for bonding the package 41 and the aluminum projection 29.
  • the interposer substrate is fixed to the housing via a member molded separately from the motherboard.
  • the above-described members are more thermally conductive than the resin layer of the motherboard. It is preferable to use one having a large conductivity.
  • a separately molded aluminum metal block 33 is bonded to the aluminum housing 27 using a silicone adhesive 35 containing a metal filler.
  • the substrate constituting the package is a metal core substrate 37.
  • the insulating resin on the front and back of the metal core substrate 37 is partially removed, and the high-heat-generating chip 1 is bonded face-up with silver paste 5 to the exposed part of the core metal 39, and packaged with chip 1 by wire bonding 3
  • the bonding pads on the board (interposer board) are electrically connected.
  • Other parts can also be mounted on the package substrate as needed and molded with resin 7 to improve handling.
  • the protruding portion 33 of the aluminum housing 27 is adhered to the exposed portion of the core metal on the back surface of the package with a silicone-based silver paste 31.
  • the connection from the high heat generating chip to the aluminum housing 27 having a large heat capacity can be connected without the insulating resin layer of the circuit board having low thermal conductivity, the heat radiation can be extremely enhanced. Also, By making at least one of the adhesive portions 31 and 35 an adhesive containing a non-conductive filler or an adhesive without a filler, it is also possible to maintain the insulation between the core metal 39 and the aluminum housing 27.
  • FIG. 6 is different from the above-described embodiment in that the connection between the core metal 39 and the aluminum protrusion 33 is performed by the solder ball 45.
  • the manufacturing process can be simplified by connecting the heat radiating part with solder balls. Although the total connection area that contributes to heat dissipation is reduced, the thermal conductivity of the solder itself is about 10 times greater than that of silver paste, so it is possible to keep the heat dissipation lower than in the previous embodiment. If the entire silver paste connection portion in the above-mentioned embodiment is connected by solder instead of the solder ball, the heat dissipation can be further improved.
  • a metal core substrate 37 is used as a package substrate.
  • the metal core substrate 37 is manufactured by a known method. However, it is necessary to remove the insulating resin portion of the metal core substrate 37, and this is performed by carbon dioxide laser processing. After the desmear treatment, a high heat-generating electronic component 1 of approximately 5 mm square is die-bonded to the surface of the core metal 39 face-up with solder or silver paste 5. Electrical connection is made by wire bonding 3. Mold with resin 7 to further improve handling and reliability. Pads for solder BGA connection are formed on the back of the package substrate.
  • These pads have a diameter of 0.6 mm and a pitch of 127 mm, for example, and are formed by nickel plating and further gold plating.
  • the BGA pad is not formed on the entire back surface of the substrate 37, and a part of a 5 mm square area for heat radiation is left.
  • An insulating resin removing portion (borebore portion) 46 having a diameter of 0.6 mm and a pitch of 1.27 mm is formed in the heat radiation area.
  • the counterbore portion 46 is formed by the same method as that of the chip mounting portion, that is, laser processing. Making the counterbore diameter about the same size as the other BGA pads allows the same solder ball size to be supplied, thus facilitating process control.
  • a protrusion 33 having a 5 mm square and a height of 1.7 mm is formed at a desired position on the ECU aluminum housing 27.
  • This projection 33 is formed by the method as in the above-described embodiment.
  • a metallization 38 for solder connection that is, a nickel metal with a thickness of 5 microns, and even a 0.5 micron To form a gold plating.
  • These metallizations 38 may be formed by any method as long as they react with the solder.
  • a silicone adhesive 25 is applied to the substrate mounting portion of the aluminum housing 27 having the projections, and the perforated substrate 15 is mounted and cured at 150 ° C. for one hour. From the hole 43 of the substrate 15, the protruding portion 33 formed on the aluminum housing 27 protrudes from the surface of the substrate 15 by about 0.2 mm.
  • the package and other electronic components 21 are aligned and mounted at predetermined positions on the substrate 15, and the solder is melted at 240 ° C for about 5 minutes, and all solder joints are simultaneously reflow-connected. I do.
  • FIG. 8 shows the structure of another electronic device.
  • a minute gap is generated on the connection surface of the interposer substrate 11 due to the interposition of the adhesive 31 made of a resin adhesive or solder between the projection 29 and the interposer substrate 11.
  • the gap can be reduced by pressing the projections 100 against the interposer substrate 11 while securing the adhesive force in the grooves, thereby improving heat dissipation. be able to.
  • a difference from the electronic device of FIG. 4 is that minute grooves or protrusions 101 and 102 are provided on the upper surface and the lower surface of the metal block 33 ′.
  • the present invention is applicable to an electronic device that requires a high heat radiation structure typified by an engine control unit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Power Engineering (AREA)
  • Combinations Of Printed Boards (AREA)
  • Mounting Of Printed Circuit Boards And The Like (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un objet permettant d'améliorer les propriétés de rayonnement thermique d'un dispositif électronique, notamment au moyen d'un substrat intercalaire. Cette construction est utilisée pour un dispositif électronique possédant une boîte et un substrat électronique. Le substrat électronique comprend un premier circuit imprimé sur lequel des parties électroniques sont montées, et un second circuit imprimé relié électriquement au premier. Le second circuit imprimé du substrat électronique est fixé à la boîte dans un espace au niveau duquel les premier et second circuits imprimés ne sont pas superposés.
PCT/JP2004/008458 2003-06-16 2004-06-16 Dispositif electronique WO2004112129A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003-170185 2003-06-16
JP2003170185A JP4218434B2 (ja) 2003-06-16 2003-06-16 電子装置

Publications (1)

Publication Number Publication Date
WO2004112129A1 true WO2004112129A1 (fr) 2004-12-23

Family

ID=33549413

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2004/008458 WO2004112129A1 (fr) 2003-06-16 2004-06-16 Dispositif electronique

Country Status (2)

Country Link
JP (1) JP4218434B2 (fr)
WO (1) WO2004112129A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007045520A2 (fr) * 2005-10-18 2007-04-26 Vdo Automotive Ag Composant de circuit integre dote d'un systeme de refroidissement
WO2009052761A1 (fr) * 2007-10-19 2009-04-30 Huawei Technologies Co., Ltd. Dispositif à carte de circuit imprimé et procédé de fabrication associé
WO2009079512A2 (fr) * 2007-12-17 2009-06-25 Tanima Holdings, Llc Dissipation thermique à liaison double
EP2146374A1 (fr) * 2008-07-02 2010-01-20 Thales Holdings UK Plc Ensemble de carte de circuit imprimé
CN103140102A (zh) * 2011-11-22 2013-06-05 富士通株式会社 确定电路基板的加固位置的方法及基板组件
US20180206324A1 (en) * 2015-07-24 2018-07-19 Nec Corporation Mounting structure, method for manufacturing mounting structure, and radio device
CN110088895A (zh) * 2016-12-28 2019-08-02 拓自达电线株式会社 散热基材、散热电路结构体及其制造方法
US20200137926A1 (en) * 2018-10-26 2020-04-30 Magna Electronics Inc. Vehicular sensing device with cooling feature
WO2022244494A1 (fr) * 2021-05-21 2022-11-24 キヤノン株式会社 Instrument électronique et dispositif d'imagerie

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Publication number Priority date Publication date Assignee Title
JP4871676B2 (ja) * 2006-08-30 2012-02-08 日立オートモティブシステムズ株式会社 電子回路装置
JPWO2010050087A1 (ja) * 2008-10-31 2012-03-29 パナソニック株式会社 積層型半導体装置及びその製造方法
JP5218657B2 (ja) * 2009-06-15 2013-06-26 富士通オプティカルコンポーネンツ株式会社 光モジュール
JP2012227422A (ja) * 2011-04-21 2012-11-15 Hitachi Chem Co Ltd 金属筐体一体型の回路基板の製造方法
DE102012216148A1 (de) * 2012-09-12 2014-04-03 Robert Bosch Gmbh Schaltungsanordnung mit Schaltungsträgern
JP6015508B2 (ja) * 2013-03-18 2016-10-26 富士通株式会社 高周波モジュール
JP2016207785A (ja) * 2015-04-20 2016-12-08 株式会社東芝 半導体装置
JP6501606B2 (ja) * 2015-05-19 2019-04-17 ルネサスエレクトロニクス株式会社 半導体装置
EP3531806B1 (fr) * 2018-02-26 2020-03-25 ZKW Group GmbH Ensemble de cartes de circuits imprimés pour composants électroniques à haute performance
KR102377811B1 (ko) 2019-08-09 2022-03-22 삼성전기주식회사 전자 소자 모듈 및 그 제조 방법
JP2023006236A (ja) * 2021-06-30 2023-01-18 株式会社オートネットワーク技術研究所 回路構成体及び電気接続箱

Citations (4)

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Publication number Priority date Publication date Assignee Title
JPH02168658A (ja) * 1988-09-26 1990-06-28 Hitachi Ltd 電子デバイスの冷却装置
JPH05136585A (ja) * 1991-11-12 1993-06-01 Fujitsu Ltd 発熱体の放熱構造
JP2002222897A (ja) * 2001-01-29 2002-08-09 Hitachi Metals Ltd 半導体用パッケージ
JP2003046022A (ja) * 2001-05-22 2003-02-14 Hitachi Ltd 電子装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02168658A (ja) * 1988-09-26 1990-06-28 Hitachi Ltd 電子デバイスの冷却装置
JPH05136585A (ja) * 1991-11-12 1993-06-01 Fujitsu Ltd 発熱体の放熱構造
JP2002222897A (ja) * 2001-01-29 2002-08-09 Hitachi Metals Ltd 半導体用パッケージ
JP2003046022A (ja) * 2001-05-22 2003-02-14 Hitachi Ltd 電子装置

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007045520A2 (fr) * 2005-10-18 2007-04-26 Vdo Automotive Ag Composant de circuit integre dote d'un systeme de refroidissement
WO2007045520A3 (fr) * 2005-10-18 2007-10-18 Siemens Ag Composant de circuit integre dote d'un systeme de refroidissement
WO2009052761A1 (fr) * 2007-10-19 2009-04-30 Huawei Technologies Co., Ltd. Dispositif à carte de circuit imprimé et procédé de fabrication associé
WO2009079512A2 (fr) * 2007-12-17 2009-06-25 Tanima Holdings, Llc Dissipation thermique à liaison double
WO2009079512A3 (fr) * 2007-12-17 2010-01-07 Tanima Holdings, Llc Dissipation thermique à liaison double
TWI461143B (zh) * 2007-12-17 2014-11-11 Tanima Holdings Llc 雙重接合之散熱裝置、系統及方法
US7706144B2 (en) 2007-12-17 2010-04-27 Lynch Thomas W Heat dissipation system and related method
US8018722B2 (en) 2007-12-17 2011-09-13 Tanima Holdings, Llc Double bonded heat dissipation
US8278559B2 (en) 2008-07-02 2012-10-02 Thales Holdings Uk Plc Printed circuit board assembly
EP2146374A1 (fr) * 2008-07-02 2010-01-20 Thales Holdings UK Plc Ensemble de carte de circuit imprimé
CN103140102A (zh) * 2011-11-22 2013-06-05 富士通株式会社 确定电路基板的加固位置的方法及基板组件
CN103140102B (zh) * 2011-11-22 2016-01-20 富士通株式会社 确定电路基板的加固位置的方法及基板组件
US20180206324A1 (en) * 2015-07-24 2018-07-19 Nec Corporation Mounting structure, method for manufacturing mounting structure, and radio device
US10506702B2 (en) * 2015-07-24 2019-12-10 Nec Corporation Mounting structure, method for manufacturing mounting structure, and radio device
CN110088895A (zh) * 2016-12-28 2019-08-02 拓自达电线株式会社 散热基材、散热电路结构体及其制造方法
CN110088895B (zh) * 2016-12-28 2023-05-23 拓自达电线株式会社 散热基材、散热电路结构体及其制造方法
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