WO2004090969A1 - 炭化珪素半導体装置およびその製造方法 - Google Patents
炭化珪素半導体装置およびその製造方法 Download PDFInfo
- Publication number
- WO2004090969A1 WO2004090969A1 PCT/JP2004/004023 JP2004004023W WO2004090969A1 WO 2004090969 A1 WO2004090969 A1 WO 2004090969A1 JP 2004004023 W JP2004004023 W JP 2004004023W WO 2004090969 A1 WO2004090969 A1 WO 2004090969A1
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- WIPO (PCT)
- Prior art keywords
- silicon carbide
- semiconductor device
- silicon
- film
- carbide semiconductor
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01366—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the semiconductor being silicon carbide
Definitions
- the present invention relates to a silicon carbide semiconductor device fabricated on a silicon carbide (SiC) semiconductor substrate, and more particularly to a silicon carbide semiconductor device having a metal-insulating film-semiconductor (MIS) structure (field effect transistor (MI SFET)). And its manufacturing method.
- MIS metal-insulating film-semiconductor
- silicon carbide (SiC) Compared to silicon (Si), silicon carbide (SiC) has excellent physical properties such as (1) wide band gap, (2) high dielectric breakdown strength, and (3) high electron saturation drift velocity. You. Therefore, by using silicon carbide (SiC) as a substrate material, a power semiconductor element having a high withstand voltage and a low resistance exceeding the limit of silicon (Si) can be manufactured.
- silicon carbide As well as silicon (Si), a feature that can be formed of silicon oxide (Si0 2) which is an insulator by thermal oxidation.
- the realization of the MISFET silicon carbide substrate material high long-term reliability of silicon oxide to be used as the gate oxide film (Si0 2) must be guaranteed.
- the total breakdown charge (Q BD ) is widely used. This value indicates the total amount of electric charge flowing through the silicon oxide film until the silicon oxide film reaches dielectric breakdown.
- Non-Patent Document 1 J, Anthony et al. "Materials Science and Engineering B61-62, 460 (1999)] Disclosure of the invention
- the present invention improves the dielectric breakdown of a silicon oxide film formed on a silicon carbide substrate, and provides a metal-insulating film-semiconductor (MIS) comprising a silicon carbide (SiC) semiconductor substrate having excellent characteristics. It is an object to obtain a silicon carbide semiconductor device having a structure.
- the present invention provides a method for forming a silicon oxide film by a thermal oxidation method on a silicon carbide substrate having a low concentration of an impurity element inevitably contained in the substrate, in other words, an impurity element which is not an intentionally doped impurity. It has been found that the formation of a gate insulating film is effective in improving the withstand voltage and long-term reliability of the silicon oxide film.
- the silicon carbide semiconductor device according to the present invention has an n-type carbide having a p-type impurity element and a metal element having a concentration of 3xl0 14 cm- 3 or less, respectively. It has a silicon region.
- the silicon carbide semiconductor device has a metal-insulating-film-semiconductor (MIS) structure, and the p-type impurity element and the metal element have a concentration of 3 ⁇ 10 14 cm ⁇ 3 or less under the gate insulating film.
- the p-type impurity element and the metal element are at least one or two or more of I of Al, B, Ti, Cr, Fe, and Ni, and the total concentration is 5.OxlO 15 cm “ 3 or less.
- the silicon carbide semiconductor device of the present invention has a DM0SFET, Lateral Resurf M0SFET or UMOSFET.
- the MIS structure of a silicon carbide semiconductor device is usually formed on a silicon carbide layer that is epitaxially grown on a silicon carbide substrate.
- a method of manufacturing a silicon carbide semiconductor device according to the present invention is a method of manufacturing a silicon carbide semiconductor device using a silicon carbide substrate having a silicon carbide layer epitaxially grown on an uppermost layer, wherein the method is intentionally performed during epitaxial growth.
- the silicon carbide layer is epitaxially grown so that the concentration of each of the impurities other than the doped impurity is 3 ⁇ 10 14 cm ⁇ 3 or less.
- a method of manufacturing a silicon carbide semiconductor device according to the invention using a carbonization silicon substrate having n-type silicon carbide region each concentration is less than 3xlO w cm_ 3 of p-type impurity element and the metal element, a metal - insulator
- a method for manufacturing a silicon carbide semiconductor device for forming a gate insulating film having a film-semiconductor (MIS) structure comprising: forming an oxide film in a portion of the gate insulating film that is in contact with a silicon carbide substrate in the air It is formed by heating in an oxygen atmosphere or a steam atmosphere.
- MIS film-semiconductor
- a silicon oxide film formed by chemical vapor deposition a silicon nitride film formed by chemical vapor deposition, or a silicon oxynitride film formed by thermally oxidizing a silicon nitride film formed by chemical vapor deposition. Any one or more of them may be formed.
- FIG. 1 is a schematic cross-sectional view of the MIS structure used for TDDB measurement.
- FIG. 2 is a diagram showing the QBD dependence of the Weibull plate as a function of the cumulative defect rate P of the silicon oxide film measured by TDDB.
- a silicon carbide semiconductor device having a metal-insulating film-semiconductor (MIS) structure has a structure in which each of the impurity elements that are unintentionally mixed into the silicon carbide (SiC) substrate under the gate insulating film, by setting the concentration and 3xlO l cin- 3 below, or by using a silicon carbide substrate concentration of each of the p-type non-pure product elements and metal elements having an n-type silicon carbide region is 3xl0 14 cm- 3 or less This significantly improves the dielectric strength and long-term reliability of the silicon oxide film, which is a major feature of the present invention.
- MIS metal-insulating film-semiconductor
- the impurity element Al, B, Ti, Cr , Fe 5 Ni and the like, which easily mixed into the silicon carbide (SiC) substrate, and they are contained in excess of 3X10 14 CBT 3 withstand voltage ⁇ And long-term reliability. That is, when the above-described impurity element, particularly a metal element, is taken into the silicon oxide film, it acts as a charge trap center, so that electrons injected into the silicon oxide film when stress is applied, or This is because holes generated by impact ionization are trapped, the local electric field in the silicon oxide film is rapidly changed, and the dielectric breakdown life is deteriorated. Therefore, it is extremely important to reduce the impurity element concentration. Such knowledge was first recognized by the present inventors. In particular, the total concentration of these impurity elements is desirably 5.0xl0 15 cm- 3 or less.
- the present invention uses a silicon carbide (SiC) substrate containing a small amount of impurity elements that are inevitably mixed as a starting material, and forms an oxide film serving as a gate insulating film in a portion in contact with the silicon carbide substrate in the air,
- the semiconductor device is formed by heating in an atmosphere or a steam atmosphere to constitute a semiconductor device.
- any one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or two or more of them can be formed thereon.
- These single-layer or multiple-layer films can be obtained by chemical vapor deposition and / or thermal oxidation of a silicon nitride film by chemical vapor deposition.
- a silicon carbide (SiC) substrate having excellent characteristics can be used, and a silicon carbide semiconductor device having a gate insulating film having a high withstand voltage and long-term reliability can be manufactured.
- These silicon carbide semiconductor devices having the MIS structure can be used as silicon carbide semiconductor devices for DM0SFET, Lateral Resurf MOSFET, and UM0SFET. Examples and comparative examples
- SiC silicon carbide
- two types of silicon carbide (SiC) having different impurity concentrations as described below were used.
- SIMS secondary ion mass spectrometry
- this substrate has the lower impurity concentration in the silicon carbide (SiC) substrate, the A substrate (Example) and the higher impurity concentration in the B substrate Plate (Comparative Example).
- a thick insulating film 2 is formed on each silicon carbide (SiC) substrate 1, a window is opened in this, a normal RCA cleaning is performed, then a sacrificial oxide film is formed and removed with hydrofluoric acid. did. Then, in an oxygen atmosphere at 1000 ° C or more at atmospheric pressure was formed in 50 dishes silicon oxide (Si0 2) film 3 of silicon carbide (SiC) substrates.
- the sample was heat treated at 1100 ° C. for 30 minutes in a nitrogen gas flow rate of 1 liter / min.
- an A1 electrode 4 and an ohmic electrode 5 for forming an ohmic contact with the substrate were formed on the silicon oxide film 3, thereby producing an M0S structure sample.
- This sample was connected to a TDDB measurement device 6, and a time-dependent dielectric breakdown (TDDB) measurement was performed in a vacuum-evacuated metal measurement chamber while light was cut off.
- TDDB time-dependent dielectric breakdown
- the horizontal axis represents D that has passed through the silicon oxide film by the time the dielectric breakdown of the silicon oxide film occurred, and the vertical axis represents a Weibull distribution plot as a function of the cumulative defect rate p.
- dielectric breakdown of the silicon oxide film starts to occur at the same level in both types of silicon carbide substrates.
- the subsequent dielectric breakdown of the silicon oxide film showed a better value for Q B1) on the A substrate than on the B substrate.
- the B substrate of the comparative example is 0.03 C / cm 2 , whereas The substrate is 0.16 C / cm 2, which is about an order of magnitude higher. .
- an impurity element when taken into a silicon oxide film, it acts as a charge trapping center, and thus is generated by electrons injected into the silicon oxide film when a stress is applied or by impact ionization.
- the trapping holes are trapped, locally accelerating the change in the internal electric field of the silicon oxide film, and causing a deterioration in the dielectric breakdown life.
- Table 1 shows the secondary ions Shows the concentrations of Ti, Al and B impurity elements in silicon carbide (SiC) substrates (A substrate, B substrate) measured by mass spectrometry (SIMS).
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005505190A JPWO2004090969A1 (ja) | 2003-03-24 | 2004-03-24 | 炭化珪素半導体装置およびその製造方法 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003080052 | 2003-03-24 | ||
| JP2003-080052 | 2003-03-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2004090969A1 true WO2004090969A1 (ja) | 2004-10-21 |
Family
ID=33156606
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/JP2004/004023 Ceased WO2004090969A1 (ja) | 2003-03-24 | 2004-03-24 | 炭化珪素半導体装置およびその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPWO2004090969A1 (ja) |
| WO (1) | WO2004090969A1 (ja) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010123794A (ja) * | 2008-11-20 | 2010-06-03 | Toyota Motor Corp | p型SiC半導体 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1167757A (ja) * | 1997-08-13 | 1999-03-09 | Agency Of Ind Science & Technol | 酸化薄膜形成方法 |
| JP2001291869A (ja) * | 2000-04-06 | 2001-10-19 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| JP2003086518A (ja) * | 2001-09-10 | 2003-03-20 | Toshiba Corp | 炭化珪素膜のcvd方法、cvd装置及びcvd装置用サセプター |
-
2004
- 2004-03-24 JP JP2005505190A patent/JPWO2004090969A1/ja active Pending
- 2004-03-24 WO PCT/JP2004/004023 patent/WO2004090969A1/ja not_active Ceased
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1167757A (ja) * | 1997-08-13 | 1999-03-09 | Agency Of Ind Science & Technol | 酸化薄膜形成方法 |
| JP2001291869A (ja) * | 2000-04-06 | 2001-10-19 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| JP2003086518A (ja) * | 2001-09-10 | 2003-03-20 | Toshiba Corp | 炭化珪素膜のcvd方法、cvd装置及びcvd装置用サセプター |
Non-Patent Citations (1)
| Title |
|---|
| NISHIO J, ET AL: "Investigation of residual impurities in 4H-SiC epitaxial layers grown by hot-wall chemical vapor deposition", MATERIALS SCIENCE FORUM VOLS., vol. 389-393, 2002, pages 215 - 218, XP002981719 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010123794A (ja) * | 2008-11-20 | 2010-06-03 | Toyota Motor Corp | p型SiC半導体 |
| DE112009003685T5 (de) | 2008-11-20 | 2012-10-18 | Toyota Jidosha Kabushiki Kaisha | P-SiC-Halbleiter |
| US8399888B2 (en) | 2008-11-20 | 2013-03-19 | Toyota Jidosha Kabushiki Kaisha | P-type SiC semiconductor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2004090969A1 (ja) | 2006-07-06 |
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