WO2004077450A1 - Halbleiterchipanordnung mit rom - Google Patents
Halbleiterchipanordnung mit rom Download PDFInfo
- Publication number
- WO2004077450A1 WO2004077450A1 PCT/DE2004/000269 DE2004000269W WO2004077450A1 WO 2004077450 A1 WO2004077450 A1 WO 2004077450A1 DE 2004000269 W DE2004000269 W DE 2004000269W WO 2004077450 A1 WO2004077450 A1 WO 2004077450A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- connection
- semiconductor chip
- memory cell
- memory
- conductor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- connection level consisting of a metallic solder is preferably arranged between the semiconductor chips, which ensures a mechanically stable connection of the two components and at the same time the electrical connection of the connections.
- the vast majority of the area of this connection level is used only for the mechanical connection of the two components and is not used electrically.
- the object of the present invention is to provide a ROM semiconductor memory which enables the memory to be increased without increasing the semiconductor chip.
- the semiconductor chip arrangement uses the connection level between the semiconductor chips as ROM.
- the connection made of electrically conductive material level structured so that it has an arrangement of conductor areas provided as a memory cell array, which can be read out via the circuits present in the semiconductor chips.
- the conductor area assigned to a respective memory cell in each case has one of two intended forms, so that each memory cell has one of two programmed states.
- the read-out circuit can be arranged in one of the two semiconductor chips connected to one another or in part in both semiconductor chips. Since the connection level is passive and contains no active components, it is necessary to place the relevant conductor areas on an electrical potential so that the respective programming of the memory cells can be detected by an electrical measurement.
- the different forms of the conductor surfaces may in the simplest case, a presence or absence of the SpeTchefzelle ⁇ 'defining T " ⁇ pe ⁇ icherkö t" ⁇ K: tflache'"Seih '.” "A preferred embodiment provides that a respective memory cell assigned conductor surface is connected to a portion of the connection level which is connected to one of the potentials of the supply voltage.
- FIG. 1 shows a chip stack in cross section.
- FIG. 2 shows a top view of the lower semiconductor chip.
- FIG. 3 shows a circuit for reading out a memory cell.
- FIG. 4 shows a structure of the connection level as a memory cell array.
- 1 shows in cross section a semiconductor chip arrangement in which a first semiconductor chip 1 and a second semiconductor chip 2 are attached one above the other.
- a connection area 3 and connection contact areas 4 form a connection level 5, in which the two semiconductor chips 1, 2 are connected to one another.
- the connection surface 3 can be made of the same material as the connection contact surfaces 4; it only serves to mechanically connect the two semiconductor chips to one another.
- the connection contact surfaces 4 are for
- the active components provided in the semiconductor chips are preferably each arranged on the upper side facing the other semiconductor chip and there directly with the connection
- FIG. 2 shows the top view of the first semiconductor chip 1 marked in FIG. 1, in which the connection area 3 and the connection contact areas 4 can be seen. In the sales
- Memory cell array are provided and form a matrix-like arrangement in this example.
- Memory contact areas 6 are arranged in a portion of the cutouts 16 corresponding to the programming concerned. Programming the
- respective memory cell is that the relevant memory contact area 6 is either present or not. In the absence of a respective memory contact area 6, there is no electrical connection detectable for the readout circuit at the relevant point. At this storage cell
- the control circuit for addressing and reading out can be in the first semiconductor chip 1, in the second semiconductor chip 2
- FIG. 3 shows a circuit suitable for reading out a relevant memory cell.
- the presence of a memory contact area 6 corresponds to the presence of a conductive fuse, while the lack of a memory contact area 6 corresponds to a missing or blown fuse.
- This fuse is shown in FIG. 3 with the designation fuse.
- This fuse together with an ohmic resistor R, forms a voltage divider between the connections V DD and V ss of the supply voltage
- connection between the fuse and the resistor controls the gate connections of two field effect transistors Ml and M2. These field effect transistors Ml, M2 are connected with their source and drain connections in series between the connections of the supply potential V DD , V ss . Depending on,
- the gate connection is at the potential V ss or at the potential V DD .
- the gate connection is at the potential V ss or at the potential V DD .
- This circuit can be provided for each memory cell, for example in the first semiconductor chip 1.
- connection level. 5 provided 25 memory cell array is carried out by using a suitable mask when structuring the connection level 5, with which memory contact surfaces 6 are produced or not at the provided locations. If at the existing memory contact areas 6 z. B. the potential V ss of the supply voltage is applied from the second semiconductor chip 2 from SO, a voltage corresponding to the programming of the relevant memory cell can be tapped at any point via the circuit shown in FIG.
- the individual memory cells are addressed by an addressing circuit known per se, which is preferably provided in the other semiconductor chip, in this example, in the first semiconductor chip 1.
- a supply voltage is applied to all of the memory contact areas 6 in order to read out the memory cell array. Therefore, the power consumption in this embodiment is relatively high.
- a further exemplary embodiment described below is improved in comparison.
- connection level 5 is structured in accordance with the illustration in FIG. 4.
- the first connection pads 7 alternate with the second connection pads 8, the first connection pads 7 each corresponding to the first potential, e.g. B. V ss of the supply voltage, and the second pads 8 to the other potential, in this example V DD .
- Each memory cell is alternatively formed by an electrical connection with a first connection surface 7 or a second connection surface 8.
- This electrical connection is, for example, a conductor surface provided in the connection plane 5, in particular a conductor strip 9, as in the example shown in FIG. 4.
- This conductor surface is in each case electrically insulated from the opposite connection surface; in the case of the exemplary embodiment shown in FIG. 4, the conductor strips 9 each have interruptions 10 on the relevant side.
- the conductor areas, in this example the conductor strips 9, have separate electrical connections 11 to an associated read-out circuit which is arranged proportionally in one of the semiconductor chips or in both semiconductor chips.
- the connections 11 are each located at the points marked with a cross in the middle between two successive connection surfaces 7, 8.
- the exemplary embodiment according to FIG. 4, in which the first connection surfaces 7 and the second connection surfaces 8 each have comb-like structured edges has the advantage particularly easy to manufacture. This is because recesses are formed between the connection surfaces between the outstanding portions of the edges, in each of which a conductor strip 9 can be arranged.
- connection level 5 LIST OF REFERENCE NUMBERS
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04710779A EP1597734A1 (de) | 2003-02-26 | 2004-02-13 | Halbleiterchipanordnung mit rom |
US11/213,341 US7714447B2 (en) | 2003-02-26 | 2005-08-25 | Semiconductor chip arrangement |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10308323.5 | 2003-02-26 | ||
DE10308323A DE10308323B4 (de) | 2003-02-26 | 2003-02-26 | Halbleiterchipanordnung mit ROM |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/213,341 Continuation US7714447B2 (en) | 2003-02-26 | 2005-08-25 | Semiconductor chip arrangement |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004077450A1 true WO2004077450A1 (de) | 2004-09-10 |
Family
ID=32863911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2004/000269 WO2004077450A1 (de) | 2003-02-26 | 2004-02-13 | Halbleiterchipanordnung mit rom |
Country Status (4)
Country | Link |
---|---|
US (1) | US7714447B2 (de) |
EP (1) | EP1597734A1 (de) |
DE (1) | DE10308323B4 (de) |
WO (1) | WO2004077450A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009045666A1 (en) | 2007-10-02 | 2009-04-09 | Freescale Semiconductor, Inc. | Programmable rom using two bonded strata and method of operation |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7499410B2 (en) | 2001-12-26 | 2009-03-03 | Cisco Technology, Inc. | Fibre channel switch that enables end devices in different fabrics to communicate with one another while retaining their unique fibre channel domain—IDs |
US7599360B2 (en) * | 2001-12-26 | 2009-10-06 | Cisco Technology, Inc. | Methods and apparatus for encapsulating a frame for transmission in a storage area network |
US7616637B1 (en) | 2002-04-01 | 2009-11-10 | Cisco Technology, Inc. | Label switching in fibre channel networks |
US7433326B2 (en) * | 2002-11-27 | 2008-10-07 | Cisco Technology, Inc. | Methods and devices for exchanging peer parameters between network devices |
US7593324B2 (en) * | 2004-10-25 | 2009-09-22 | Cisco Technology, Inc. | Graceful port shutdown protocol for fibre channel interfaces |
US7916628B2 (en) * | 2004-11-01 | 2011-03-29 | Cisco Technology, Inc. | Trunking for fabric ports in fibre channel switches and attached devices |
US7649844B2 (en) * | 2004-12-29 | 2010-01-19 | Cisco Technology, Inc. | In-order fibre channel packet delivery |
US8036296B2 (en) * | 2006-09-28 | 2011-10-11 | Broadcom Corporation | Method and system for achieving space and time diversity gain |
US20080266925A1 (en) * | 2007-04-30 | 2008-10-30 | International Business Machines Corporation | Array Split Across Three-Dimensional Interconnected Chips |
US7420832B1 (en) * | 2007-04-30 | 2008-09-02 | International Business Machines Corporation | Array split across three-dimensional interconnected chips |
US8916959B2 (en) | 2012-12-20 | 2014-12-23 | International Business Machines Corporation | Packaging structure |
US9583410B2 (en) | 2014-03-21 | 2017-02-28 | International Business Machines Corporation | Volumetric integrated circuit and volumetric integrated circuit manufacturing method |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0073486A2 (de) * | 1981-08-31 | 1983-03-09 | Kabushiki Kaisha Toshiba | Gestapelter Halbleiterspeicher |
US4939568A (en) * | 1986-03-20 | 1990-07-03 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method thereof |
US6541869B1 (en) * | 1998-12-04 | 2003-04-01 | Thin Film Electronics Asa | Scalable data processing apparatus |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4208726A (en) * | 1978-06-12 | 1980-06-17 | Texas Instruments Incorporated | Programming of semiconductor read only memory |
US5070026A (en) * | 1989-06-26 | 1991-12-03 | Spire Corporation | Process of making a ferroelectric electronic component and product |
US5319240A (en) * | 1993-02-03 | 1994-06-07 | International Business Machines Corporation | Three dimensional integrated device and circuit structures |
US5535156A (en) * | 1994-05-05 | 1996-07-09 | California Institute Of Technology | Transistorless, multistable current-mode memory cells and memory arrays and methods of reading and writing to the same |
JPH08129891A (ja) * | 1994-10-28 | 1996-05-21 | Sony Corp | メモリセル回路 |
US5567657A (en) * | 1995-12-04 | 1996-10-22 | General Electric Company | Fabrication and structures of two-sided molded circuit modules with flexible interconnect layers |
US5847442A (en) * | 1996-11-12 | 1998-12-08 | Lucent Technologies Inc. | Structure for read-only-memory |
TW307048B (en) * | 1996-11-22 | 1997-06-01 | United Microelectronics Corp | High density read only memory structure and manufacturing method thereof |
DE19713173C2 (de) * | 1997-03-27 | 2001-02-15 | Siemens Ag | ROM-Speicher |
JP4004103B2 (ja) * | 1997-07-01 | 2007-11-07 | 日本テキサス・インスツルメンツ株式会社 | マスクrom |
GB9722149D0 (en) * | 1997-10-22 | 1997-12-17 | Philips Electronics Nv | Semiconductior memory devices |
TW380317B (en) * | 1998-01-17 | 2000-01-21 | Winbond Electronics Corp | Manufacturing method for poly-load resistors of SRAM |
JP4010091B2 (ja) * | 2000-03-23 | 2007-11-21 | セイコーエプソン株式会社 | メモリデバイスおよびその製造方法 |
-
2003
- 2003-02-26 DE DE10308323A patent/DE10308323B4/de not_active Expired - Fee Related
-
2004
- 2004-02-13 EP EP04710779A patent/EP1597734A1/de not_active Withdrawn
- 2004-02-13 WO PCT/DE2004/000269 patent/WO2004077450A1/de not_active Application Discontinuation
-
2005
- 2005-08-25 US US11/213,341 patent/US7714447B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0073486A2 (de) * | 1981-08-31 | 1983-03-09 | Kabushiki Kaisha Toshiba | Gestapelter Halbleiterspeicher |
US4939568A (en) * | 1986-03-20 | 1990-07-03 | Fujitsu Limited | Three-dimensional integrated circuit and manufacturing method thereof |
US6541869B1 (en) * | 1998-12-04 | 2003-04-01 | Thin Film Electronics Asa | Scalable data processing apparatus |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009045666A1 (en) | 2007-10-02 | 2009-04-09 | Freescale Semiconductor, Inc. | Programmable rom using two bonded strata and method of operation |
EP2195843A1 (de) * | 2007-10-02 | 2010-06-16 | Freescale Semiconductor, Inc. | Programmierbarer rom mit zwei gebundenen schichten und betriebsverfahren dafür |
EP2195843A4 (de) * | 2007-10-02 | 2010-10-20 | Freescale Semiconductor Inc | Programmierbarer rom mit zwei gebundenen schichten und betriebsverfahren dafür |
KR101452203B1 (ko) | 2007-10-02 | 2014-10-21 | 프리스케일 세미컨덕터, 인크. | 2개의 본딩된 스트래텀들을 사용하는 프로그래밍가능한 rom 및 동작 방법 |
Also Published As
Publication number | Publication date |
---|---|
DE10308323A1 (de) | 2004-09-16 |
DE10308323B4 (de) | 2007-10-11 |
US7714447B2 (en) | 2010-05-11 |
US20060038263A1 (en) | 2006-02-23 |
EP1597734A1 (de) | 2005-11-23 |
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