WO2004073075A1 - Dispositif a semi-conducteur encapsule et son procede de fabrication - Google Patents

Dispositif a semi-conducteur encapsule et son procede de fabrication Download PDF

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Publication number
WO2004073075A1
WO2004073075A1 PCT/KR2004/000297 KR2004000297W WO2004073075A1 WO 2004073075 A1 WO2004073075 A1 WO 2004073075A1 KR 2004000297 W KR2004000297 W KR 2004000297W WO 2004073075 A1 WO2004073075 A1 WO 2004073075A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor chip
semiconductor
transparent electrode
resin
filler resin
Prior art date
Application number
PCT/KR2004/000297
Other languages
English (en)
Inventor
Ik-Seong Park
Original Assignee
Alti-Electronics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alti-Electronics Co., Ltd. filed Critical Alti-Electronics Co., Ltd.
Publication of WO2004073075A1 publication Critical patent/WO2004073075A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2224/73267—Layer and HDI connectors
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
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    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
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    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements

Definitions

  • the present invention relates to a package of a semiconductor device and a fabrication method thereof, and in particular, to a semiconductor package for electrically connecting a light emitting diode (LED) to an external lead using a transparent electrode, and a method of fabricating the same.
  • LED light emitting diode
  • a semiconductor package has a function of connecting a semiconductor chip to an external substrate, such as a printed circuit board, through fitting the semiconductor chip to a lead frame, and mounting it onto the external substrate.
  • an external substrate such as a printed circuit board
  • semiconductor packages are existent while being differentiated in the structure and the function thereof. Among them, wire bonding semiconductor packages have been most extensively used with excellent product adaptability.
  • Fig. 1 illustrates a semiconductor chip packaged using the wire bonding technique, which has an LED radiating visible rays of a specific wavelength.
  • a first bonding pad 2 is formed on a printed circuit board
  • the semiconductor chip 3 is mounted onto the printed circuit board 1 using a silver paste 5 as an adhesive.
  • the so-called wire bonding process is performed using a gold- based wire 6 to interconnect the first bonding pad 2 of the printed circuit board 1 and the second bonding pad 4 of the semiconductor chip 3.
  • a photolithography process is conventionally performed to form such a bonding pad.
  • the photolithography process involves the steps of coating a photoresist film onto a target, light-exposing and developing it, removing the photoresist film, and cleaning the target. That is, the photolithography process involves complicated processing steps with much time consumption.
  • the photolithography process it is required with the photolithography process to provide high cost equipments, such as a light exposing apparatus, a spin coater, a developer, and a wet etching apparatus. Furthermore, as the area of the non-transparent bonding pad on the semiconductor chip does not serve to make the light emission, the brightness of the resulting light-emitting device is limited.
  • the size of the bonding pad should be reduced as much as possible. Accordingly, the bonding pad is locally formed at a predetermined region on the chip. However, with such a structure, the current flow is concentrated close to the bonding pad so that it is not uniformly distributed over the entire area of the chip. This deteriorates the device light emission efficiency.
  • the flip chip package refers to the package where the chip is overturned, and attached to the substrate.
  • the flip chip is manufactured through attaching a chip to a substrate with connection pads arranged corresponding to the input and output pads of the chip, and forming a protective layer thereon.
  • a conductive bump is additionally formed on the bonding pad of the chip instead of the conventional wire bonding.
  • the semiconductor device package includes a semiconductor chip mounted on a printed circuit board, an external electrode formed on the printed circuit board, a transparent electrode formed on the semiconductor chip such that it is connected to the external electrode to supply power to the semiconductor chip, and a molding resin formed on the transparent electrode.
  • Fig. 1 is a sectional view of a semiconductor device package based on the wire bonding according to a prior art
  • Fig. 2 is a sectional view of a semiconductor device package according to an embodiment of the present invention
  • Fig. 3 is a sectional view of a semiconductor device package according to another embodiment of the present invention.
  • Fig. 2 is a sectional view of a semiconductor device package according to an embodiment of the present invention.
  • a semiconductor chip 13 is mounted on a printed circuit board 1 1 via an adhesive layer 12 based on a conductive resin, such as a silver paste.
  • First and second external electrodes 17 and 18 are formed at the printed circuit board 11 to supply power to the semiconductor chip 13.
  • a light emitting diode is mounted as the semiconductor chip 13.
  • the LED has a p-n contact structure, and emits visible rays.
  • the first external electrode 17 supplies power to the upper p layer of the p-n contact structure, and the second external electrode 18 supplies power to the lower n layer of the p-n contact structure.
  • a transparent electrode 15 is formed on the semiconductor chip 13 while being connected to the first external electrode 17.
  • the transparent electrode 15 is formed with a transparent conductive material, such as indium tin oxide (ITO), but it is not needed to limit the electrode material to the specific one. Furthermore, it is not needed to form the transparent electrode 15 only with the film shape.
  • the transparent electrode 15 may be formed with a transparent conductive polymer material.
  • a filler resin 14 may be formed at the lateral side of the semiconductor chip 13 with a non-conductive material to improve the insulating characteristic thereof.
  • the filler resin 14 may be formed with a material capable of transmitting visible rays, ultraviolet rays or infrared rays, but not limited thereto.
  • the filler resin 14 may be formed with a milk white-colored material.
  • the filler resin 14 it is preferable to form the filler resin 14 at the lateral side of the semiconductor chip 13. However, it may be formed also at a predetermined region on the top of the semiconductor chip 13 close to the lateral side thereof during the formation process. With the formation of the filler resin 14, it is preferable to form the transparent electrode 15 on the top surface of the semiconductor chip 13 together with the filler resin 14.
  • a molding resin 16 is formed on the top of the transparent electrode 15. In order to improve the brightness of the LED, it is preferable to form the molding resin 16 with a material capable of transmitting visible rays, ultraviolet rays or infrared rays.
  • an adhesion-inducement layer may be formed at the interface between the transparent electrode 15 and the semiconductor chip 13 as well as at the interface between the transparent electrode 15 and the filler resin 14 to reinforce the adhesive force.
  • Fig. 3 is a sectional view of a semiconductor device package according to another embodiment of the present invention. As different from the structure related to the previous embodiment of the present invention, the package involves plural numbers of semiconductor chips 23.
  • a plurality of semiconductor chips 23 are mounted on the printed circuit board 21 via an adhesive layer 22 based on a conductive resin, such as a silver paste.
  • a filler resin 24 is formed at the lateral side of the semiconductor chips with a non-conductive material to fill the space between the semiconductor chip neighbors 23.
  • a transparent electrode 25 is formed on the filler resin 24 and the semiconductor chips 23.
  • a reflector 27 may be installed between the semiconductor chips 23 to concentrate the light emitted from the chips 23.
  • the filler resin 24 fills the space between the semiconductor chip neighbors 23 except for the reflector 27.
  • the transparent electrode 25 is formed on the reflector 27, the filler resin 24, and the semiconductor chip 23.
  • a semiconductor chip 13 is mounted onto a printed circuit board 11 via an adhesive layer 12 based on a conductive resin, such as a silver paste, and first and second external electrodes 17 and 18 are formed on the printed circuit board 11 to supply power to the semiconductor chip 13.
  • a conductive resin such as a silver paste
  • a light emitting diode (LED) is mounted as the semiconductor chip 13.
  • the LED has a p-n contact structure, and emits visible rays.
  • the first external electrode 17 supplies power to the upper p layer of the p-n contact structure, and the second external electrode 18 supplies power to the lower n layer of the p-n contact structure.
  • the LED may radiate visible rays, ultraviolet rays, or infrared rays.
  • a transparent electrode 15 is formed on the top of the semiconductor chip 13 such that it is connected to the first external electrode 17.
  • the transparent electrode 15 may be formed using a sputtering technique, or other film formation techniques. Furthermore, it is not needed to form the transparent electrode 15 only with the film shape.
  • the transparent electrode 15 may be formed with a transparent conductive polymer material.
  • a filler resin 14 may be formed at the lateral side of the semiconductor chip 13 with a non-conductive material to improve the insulating characteristic thereof.
  • the filler resin 14 may be formed with a material capable of transmitting visible rays, ultraviolet rays or infrared rays, and other suitable materials.
  • the filler resin 14 may be formed with a milk white-colored material.
  • the filler resin 14 is preferably formed at the lateral side of the semiconductor chip 13, it may be also formed at a predetermined region on the top of the semiconductor chip 13 close to the lateral side thereof during the formation process. With the formation of the filler resin 14, the transparent electrode 15 is formed on the filler resin 14 and the semiconductor chip 13.
  • a molding resin 16 is formed on the top of the transparent electrode 15, thereby completing the package. It is preferable to form the molding resin 16 with a material capable of transmitting visible rays, ultraviolet rays or infrared rays. Furthermore, an adhesion-inducement layer (not shown) may be formed at the interface between the transparent electrode 15 and the semiconductor chip 13 as well as at the interface between the transparent electrode 15 and the filler resin 14 to reinforce the adhesive force.
  • a plurality of semiconductor chips 23 are mounted on the printed circuit board 21 via an adhesive layer 22 based on a conductive resin, such as a silver paste.
  • a filler resin 24 is formed at the lateral side of the semiconductor chips with a non-conductive material to fill the space between the semiconductor chip neighbors 23.
  • a transparent electrode 25 is formed on the filler resin 24 and the semiconductor chips 23.
  • a reflector 27 is installed between the semiconductor chips 23 to concentrate the light emitted from the chips 23.
  • the filler resin 24 fills the space between the semiconductor chip neighbors 23 except for the reflector 27. It is preferable that the transparent electrode 25 is formed on the reflector 27, the filler resin 24, and the semiconductor chip 23.
  • the photolithography process for forming a bonding pad in a separate manner is omitted with the inventive package fabricating method.
  • a transparent electrode is formed on the chip, it is not required to form a separate bonding pad, that is, to separately perform the photolithography process.
  • the overall process is simplified while reducing the processing time and cost.
  • the transparent electrode is formed at the entire area of the chip, the brightness of the LED is enhanced compared to the conventional case where the non-transparent bonding pad takes a local region on the semiconductor chip so that the brightness thereof is deteriorated.
  • the light emission efficiency of the device is enhanced.
  • the package can be effectively minimized.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Led Device Packages (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur encapsulé et son procédé de fabrication, lequel permet d'encapsuler le dispositif à semi-conducteur de façon simplifiée, rapide et économique, tout en améliorant son efficacité d'émission lumineuse, avec une structure d'encapsulation minimisée. Selon l'invention, le dispositif à semi-conducteur encapsulé comprend une puce de semi-conducteur montée sur une plaquette de circuit imprimé, une électrode extérieure formée sur la plaquette de circuit imprimé, une électrode transparente formée sur la puce de semi-conducteur de façon à être reliée à l'électrode extérieure pour alimenter en courant la puce de semi-conducteur, et une résine moulée placée sur l'électrode transparente. Grâce à cette structure, on obtient un dispositif encapsulé sans former une pastille de liaison conductrice non transparente, telle qu'une pastille de liaison de fil et une pastille de liaison de puce à bosse.
PCT/KR2004/000297 2003-02-13 2004-02-13 Dispositif a semi-conducteur encapsule et son procede de fabrication WO2004073075A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2003-0008966 2003-02-13
KR10-2003-0008966A KR100523803B1 (ko) 2003-02-13 2003-02-13 반도체 소자의 패키지 및 그 제조 방법

Publications (1)

Publication Number Publication Date
WO2004073075A1 true WO2004073075A1 (fr) 2004-08-26

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PCT/KR2004/000297 WO2004073075A1 (fr) 2003-02-13 2004-02-13 Dispositif a semi-conducteur encapsule et son procede de fabrication

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KR (1) KR100523803B1 (fr)
WO (1) WO2004073075A1 (fr)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102007008524A1 (de) * 2007-02-21 2008-08-28 Osram Opto Semiconductors Gmbh Strahlung emittierender Chip mit mindestens einem Halbleiterkörper
WO2012013435A1 (fr) * 2010-07-28 2012-02-02 Osram Opto Semiconductors Gmbh Élément semi-conducteur émetteur de lumière et procédé de fabrication d'un élément semi-conducteur émetteur de lumière
JP2013125816A (ja) * 2011-12-14 2013-06-24 Toshiba Corp 半導体発光素子
EP2362449A3 (fr) * 2010-02-18 2014-09-17 LG Innotek Co., Ltd. Structures d'électrode pour un dispositif électroluminescent et emballage correspondant
DE102015107591A1 (de) * 2015-05-13 2016-11-17 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils
US9537056B2 (en) 2010-02-18 2017-01-03 Lg Innotek Co., Ltd. Light emitting device
WO2021245344A1 (fr) * 2020-06-04 2021-12-09 Aledia Dispositif optoélectronique pour affichage lumineux à parois de confinement lumineux conductrices et procédé de fabrication correspondant

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100878327B1 (ko) * 2007-07-06 2009-01-14 한국광기술원 웨이퍼레벨 패키징된 발광다이오드 및 그의 제조 방법

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10162953A (ja) * 1996-12-03 1998-06-19 Hokuriku Electric Ind Co Ltd チップ型電界発光素子
JPH114020A (ja) * 1997-04-15 1999-01-06 Toshiba Corp 半導体発光素子及びその製造方法、並びに半導体発光装置
JPH1187779A (ja) * 1997-09-04 1999-03-30 Rohm Co Ltd チップ型発光素子
US6396082B1 (en) * 1999-07-29 2002-05-28 Citizen Electronics Co., Ltd. Light-emitting diode
US20020134988A1 (en) * 1999-12-17 2002-09-26 Hiroki Ishinaga A chip-type light-emitting device with case

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10162953A (ja) * 1996-12-03 1998-06-19 Hokuriku Electric Ind Co Ltd チップ型電界発光素子
JPH114020A (ja) * 1997-04-15 1999-01-06 Toshiba Corp 半導体発光素子及びその製造方法、並びに半導体発光装置
JPH1187779A (ja) * 1997-09-04 1999-03-30 Rohm Co Ltd チップ型発光素子
US6396082B1 (en) * 1999-07-29 2002-05-28 Citizen Electronics Co., Ltd. Light-emitting diode
US20020134988A1 (en) * 1999-12-17 2002-09-26 Hiroki Ishinaga A chip-type light-emitting device with case

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI514612B (zh) * 2007-02-21 2015-12-21 Osram Opto Semiconductors Gmbh 具有至少一個半導體晶粒之輻射發出晶片
US8067783B2 (en) 2007-02-21 2011-11-29 Osram Opto Semiconductors Gmbh Radiation-emitting chip comprising at least one semiconductor body
DE102007008524A1 (de) * 2007-02-21 2008-08-28 Osram Opto Semiconductors Gmbh Strahlung emittierender Chip mit mindestens einem Halbleiterkörper
EP2362449A3 (fr) * 2010-02-18 2014-09-17 LG Innotek Co., Ltd. Structures d'électrode pour un dispositif électroluminescent et emballage correspondant
US9537056B2 (en) 2010-02-18 2017-01-03 Lg Innotek Co., Ltd. Light emitting device
WO2012013435A1 (fr) * 2010-07-28 2012-02-02 Osram Opto Semiconductors Gmbh Élément semi-conducteur émetteur de lumière et procédé de fabrication d'un élément semi-conducteur émetteur de lumière
JP2013125816A (ja) * 2011-12-14 2013-06-24 Toshiba Corp 半導体発光素子
US9076924B2 (en) 2011-12-14 2015-07-07 Kabushiki Kaisha Toshiba Semiconductor light emitting device
DE102015107591A1 (de) * 2015-05-13 2016-11-17 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils
US20180108695A1 (en) 2015-05-13 2018-04-19 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component
US10381391B2 (en) 2015-05-13 2019-08-13 Osram Opto Semiconductors Gmbh Optoelectronic semiconductor component and method for producing an optoelectronic semiconductor component
DE102015107591B4 (de) 2015-05-13 2021-09-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils
WO2021245344A1 (fr) * 2020-06-04 2021-12-09 Aledia Dispositif optoélectronique pour affichage lumineux à parois de confinement lumineux conductrices et procédé de fabrication correspondant
FR3111235A1 (fr) * 2020-06-04 2021-12-10 Aledia Dispositif optoélectronique pour affichage lumineux à parois de confinement lumineux conductrices et procédé de fabrication

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