WO2004068579A1 - Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur - Google Patents
Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur Download PDFInfo
- Publication number
- WO2004068579A1 WO2004068579A1 PCT/DE2004/000147 DE2004000147W WO2004068579A1 WO 2004068579 A1 WO2004068579 A1 WO 2004068579A1 DE 2004000147 W DE2004000147 W DE 2004000147W WO 2004068579 A1 WO2004068579 A1 WO 2004068579A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- layer
- structures
- insulator layer
- active
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
Definitions
- the invention relates to SOI structures (Silicon-on-Insulator), in which component structures in an upper
- Semiconductor layer and in the semiconductor substrate are present, which are in electrical connections, which are guided through an insulator layer.
- An SOI structure consists of a thin semiconductor layer, which is located on a thin oxide layer.
- the oxide layer is usually produced as a buried oxide (BOX) and in turn lies on a semiconductor layer, generally a silicon layer, namely the silicon substrate, which usually has a thickness of 300 ⁇ m to ⁇ OO ⁇ iri. This substrate is only used to handle the structure.
- the actual components and functions are implemented as in normal CMOS processes on homogeneous silicon wafers in the near-surface semiconductor layer 0.
- the US-A 6,188,122 shows an SOI structure with "Capacitor” in the substrate and an FET (active device) in the upper silicon layer, column 4, lines 40 ff. Conductive vias, column 5, lines 11 ff. reach through the oxide layer (there 30).
- the object of the invention is to propose a method which enables improved substrate use to increase the packing density. Qualitative improvements in semiconductor circuits can be achieved.
- the invention is also intended to expand the integration possibilities of circuit arrangements on SOI semiconductor wafers to include components from others
- the substrate is also used for the expansion of circuits, i.e.
- the electrical connections to the substrate can suppress possible repercussions on the circuit structures in the thin upper silicon layer.
- Backside metallization of the substrate can be used for the purposes of including the substrate.
- the active components realized in the upper silicon layer are sensitive to an applied potential on the back.
- MOSFETs can be opened from the rear, at high rear voltages, or an on-resistance of high-voltage transistors depends on the rear voltage.
- Even simple diodes have a dependence of their breakdown voltage on the applied one
- substrate terminals Backside metallization
- Corresponding housings do not provide a rear contact and often the number of pins on circuits is not sufficient to be able to contact the rear.
- this electrical connection makes it possible to use the substrate in the sense of a qualitative expansion of component arrangements.
- FIG 1 shows schematically two different types of
- Transistors 40, 50 which are produced on an SOI wafer 10 by means of SOI technology.
- FIG. 2 shows schematically how p- and n-ion implantation and subsequent thermal treatment (the latter not shown) are used to produce p- and n-doped regions just below the boundary between insulation oxide 11 and substrate 13 in substrate 13 using a few process steps.
- FIG. 3 shows in the simplest case schematically the implementation of a contact (as a path) from a doped zone 13a in the substrate through the insulation oxide 11 to the upper silicon layer 12 (the latter not shown), cf. but Figure 2.
- FIG. 3 c shows designs of the aforementioned examples with the SOI wafer 10.
- Conductive (ohmic) contacts and Schottky contacts can be produced via the metal bridge 20 to the substrate 13.
- Diodes, MOSFETs, bipolar transistors, thyristors and IGBTs can be implemented as active structures.
- Capacities, resistances and shielding layers can be implemented as passive structures.
- shielding layers are not always absolutely necessary. Such areas are then floating freely (n.c). Shielding by means of substrate implantation achieves a desired reduction in the negative substrate influence (substrate bias) on structures in the upper active semiconductor layer 12. The shielding (not shown separately) realizes a decoupling of these active structures, for example 40 or 50, from effects which occur on the rear side R the SOI pane 10 can occur.
- the SOI wafer structure illustrated in FIG. 1 with an insulator layer 11, a stronger substrate 13 and an active, thin layer 12 above the insulator 11 shows two different types of transistors 40, 50, an SOI MOSFET and an SOI power transistor , These are already at least partially integrated into the active silicon layer 12 and a trench 12a is provided between the transistors 40, 50, which interrupts the active silicon layer 12. Further,
- Interruptions are to the left and right of the two transistor types shown by way of example and these interruptions are referred to below as 12a, 12b, while the remainders of the active layer 12 are then structurally designated as 12 ', 12 "and 12"'.
- the structure of the transistors is not described in any more detail; it is of a conventional design with a gate, drain and source and a bulk connection, which, however, is called a body here, since it does not affect the substrate but is arranged above the insulator layer 11. No openings are visible in FIG. 1, which break through the insulator layer and reach the substrate 13. These are illustrated in more detail in the following sections, in which structures of components in the substrate 13 are also shown, which have been omitted in FIG. 1 to illustrate the structure of transistors on an SOI wafer.
- Figure 2 illustrates the first process steps, here the radiation of ions by p-ion implantation and n-ion implantation.
- the p-type implantation 30 and the n-type implantation 31 are represented by vertical arrows. They reach through the active silicon as layer 12 from the front side V, through the buried oxide insulator 11, which represents the insulation layer of the SOI wafer, and into the substrate 13, to form symbolically represented doping regions 13 ', 13 ", as p-region (p-doping region) or as n-region 13 "
- these regions form component structures below the insulator layer 11 in the substrate.
- a thermal treatment activates the areas 13 ′, 13 ′′ just below the boundary between the insulation layer (the BOX) and the rest of the substrate 13.
- the active structures which have been symbolically represented with reference to FIGS. 1 and 2, are the first active structures for components 40, 50 above the insulator 11 and active structures 13 ', 13 "below this insulator, which are arranged as second structures for other components in the substrate. Electrical connections are made through the insulator layer, which are explained in more detail in the following examples.
- the embodiment according to FIG. 3 shows schematically the one produced by the filling 20 Breakthrough 19 in the insulator layer 11.
- the breakthroughs are generated at locations where the active silicon layer 12 is no longer present.
- the fillings 20 of the openings 19 of the insulator layer 11 can be made with a metal.
- These regions are regarded as lateral insulation regions which lie between two active residual layers of the active silicon layer 12, for example the lateral insulation region 12a of FIG. 3b, between the residual layers 12 "and 12" ', or the lateral one
- the ion implantation 30, 31 with high-energy ions is carried out from the front, based on the specific areas which are provided on the basis of the topology to be achieved.
- the ion implantation takes place through the semiconductor layer 12 and the insulator layer 11 into the substrate 13, using templates and with different types of ions 30 or 31, depending on the component to be produced.
- the activation by temperature can optionally take place in several steps and at different temperatures, adapted to a respectively selected, implanted ion type in accordance with the aforementioned different ion implantations.
- metallization layers can be provided, which are shown in different variants in FIGS. 3a to 3c, applied to the SOI wafer structure described above.
- the • metallization layers can for example on the
- Rear R can be arranged as shown as layer 14 in Figures 3b and 3c.
- the metallization layers can be insulated from one another.
- a filling is also regarded as metallization, which connects first structures on the top of the insulator layer with second structures under the insulator layer in the substrate 13 in an electrically conductive manner.
- the metal filling 20 connects a doping region 13a ′ (in FIG. 3 13a) with a metallization layer 15 above the insulator, as shown in FIG. 3.
- This metallization layer is shaped as a bridge, so that it connects the electrically conductive filling 20 to a component on the top which is arranged in the remaining silicon layer 12 ′′, for example according to FIG. 1.
- the insulator layer 11 can be designed as a silicon oxide layer, which is also the case with most SOI wafers.
- the substrate 13 can consist of single-crystal silicon.
- Schottky contacts result in a metal filling 22 in an opening 21 if the upper side of the substrate 13 has no doping region.
- a Schottky contact with the substrate 13 is produced in the region of the opening.
- This Schottky contact 13c is shown on the right in FIG. 3a.
- a metal bridge is also shown above the filling 22 in the opening 21, mirror image of the metal bridge 15, here as a bridge 15 'for the electrically conductive one Connection to the active residual layer 12 ", to the right of the lateral isolation area 12c
- a shielding layer 13a is shown under the residual layer 12 'located between the lateral insulation regions 12b, 12c. It lies directly below the insulator layer 11 and is not electrically conductively contacted.
- ohmic contact 13b between the metal filling 20 and the n- or p-doped region 13a ' is shown.
- a diode structure is formed between the doping region and the substrate 13, in contrast to an ohmic contact (without directional dependence on the conductivity in the contact plane on the underside of the insulator layer BOX, denoted by 11).
- the component produced using the described method lies on two levels, separated by the insulator layer 11. Above this layer are first structures, below this layer are second structures. Active components such as diodes can be provided in the substrate 13, cf. Figure 2 in the transition region between the doping region 13 'and 13 "and the substrate 13, or Figure 3 below the region 13a in the transition to the substrate 13, or MOSFETs, bipolar transistors, thyristors or IGBTs, in the manner of Figure 1, only within the Substrate 13.
- the same components can be located above the insulator layer 11 in the active layer 12, or at least extend into them, in accordance with FIG. 1.
- passive components can be arranged in the substrate 13 as second structures, such as capacitors, resistors or a shielding layer, as shown by 13a "in FIG. 3a.
- a resistance is obtained, for example, by a doping region corresponding to that 13a 'of FIG. 3a when it comes to two of its ends with a metallic filling 20 in one respective opening 19 is contacted in the sense of the ohmic contact 13b.
- FIG. 3b shows a continuous bridge 15 "with two arms, which bridge 15" conductively connects the two remaining layers 12 "and 12" ', at the same time making electrically conductive contact with the filling 20, which is arranged in the opening 19, in its central region. It forms an ohmic contact and a conductive path (vertical plug) through the insulator layer, to the doping region 13a.
- a metallic layer 14 is arranged on the rear side R on the opposite side.
- the contacting described by the plugs 20 is provided for passive structures in substrate 13. Shielding layers, such as 13a "according to FIG. 3a, do not need such conductive connections to the top. They can remain isolated in the substrate. Such areas are then identified as floating freely (usually n.c. - not connected).
- Shielding by means of substrate implantation 13a "can be achieved. This area shields electrically.
- FIG. 3c shows a metallic shield 14 'above a filling 20 in an opening 19 which leads to a
- Doping region 13a leads, as was illustrated in FIG. 3.
- a component 60 is shown schematically in section, which can correspond to that of FIG. 1, for example component 40.
- the trench can be seen in FIG. 3c, which also in FIG Figure 1 is clearly visible between two components above the insulator layer 11.
- the embodiment according to FIG. 3c has two metallizations opposite, from the front V and the rear R, and semiconductor structures above the insulator layer 11 and in the substrate 13, below the insulator layer 11.
- Die Components 60, 50 or 40 are dielectrically separated or insulated from one another by trenches which extend as far as the insulation layer 11. As a result, the mutual electrical influence of components which are arranged on the same side is greatly reduced.
- Such dielectric insulation makes SOI technology suitable for high-voltage applications.
- the components are not coupled to one another via the substrate; bulk connections are omitted, in favor of body connections for switchable components.
- the substrate is not ignored, but is used to expand the power circuits described, i.e. provided with doping areas in order to be able to integrate additional and different types of components.
- the rear side metallization 14 of FIGS. 3b and 3c suppresses adverse effects on the circuit structures 40, 50 and 60 in and above the active silicon layer 12 or their residues, after their structuring into the sections which were previously identified by 12 ', 12 "and 12"' were designated.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/DE2004/000147 WO2004068579A1 (de) | 2003-01-30 | 2004-01-30 | Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur |
AU2004208199A AU2004208199A1 (en) | 2003-01-30 | 2004-01-30 | SOI structure comprising substrate contacts on both sides of the box, and method for the production of such a structure |
EP04706606A EP1588418A1 (de) | 2003-01-30 | 2004-01-30 | Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur |
US10/543,923 US7195961B2 (en) | 2003-01-30 | 2004-01-30 | SOI structure comprising substrate contacts on both sides of the box, and method for the production of such a structure |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10303642A DE10303642A1 (de) | 2003-01-30 | 2003-01-30 | Integration von Substratbauelementen bei SOI-Halbleiterstrukturen |
DE10303642.3 | 2003-01-30 | ||
PCT/DE2004/000147 WO2004068579A1 (de) | 2003-01-30 | 2004-01-30 | Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004068579A1 true WO2004068579A1 (de) | 2004-08-12 |
Family
ID=32826180
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2004/000147 WO2004068579A1 (de) | 2003-01-30 | 2004-01-30 | Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur |
Country Status (4)
Country | Link |
---|---|
US (1) | US7195961B2 (de) |
EP (1) | EP1588418A1 (de) |
AU (1) | AU2004208199A1 (de) |
WO (1) | WO2004068579A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7955940B2 (en) * | 2009-09-01 | 2011-06-07 | International Business Machines Corporation | Silicon-on-insulator substrate with built-in substrate junction |
US8299561B2 (en) | 2010-04-21 | 2012-10-30 | International Business Machines Corporation | Shielding for high-voltage semiconductor-on-insulator devices |
US9461169B2 (en) | 2010-05-28 | 2016-10-04 | Globalfoundries Inc. | Device and method for fabricating thin semiconductor channel and buried strain memorization layer |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4441724A1 (de) * | 1994-11-23 | 1996-05-30 | Siemens Ag | SOI-Substrat |
US5805497A (en) * | 1996-03-29 | 1998-09-08 | Nec Corporation | Semiconductor static random access memory cell with additional capacitor coupled to memory nodes and process of fabrication thereof |
WO1999033115A1 (en) * | 1997-12-19 | 1999-07-01 | Advanced Micro Devices, Inc. | Silicon-on-insulator configuration which is compatible with bulk cmos architecture |
EP0948054A2 (de) * | 1998-03-27 | 1999-10-06 | International Business Machines Corporation | Vergrabene strukturierte Leiterebenen für einen integrierten Halbleiterschaltkreis auf einem Isolator |
US20020063285A1 (en) * | 2000-11-29 | 2002-05-30 | De-Yuan Wu | SOI device and method of fabrication |
US20030001658A1 (en) * | 2000-11-28 | 2003-01-02 | Koichi Matsumoto | Semiconductor device |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0832040A (ja) * | 1994-07-14 | 1996-02-02 | Nec Corp | 半導体装置 |
US5725729A (en) * | 1994-09-26 | 1998-03-10 | The Charles Stark Draper Laboratory, Inc. | Process for micromechanical fabrication |
JP3322492B2 (ja) * | 1994-11-28 | 2002-09-09 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP2001308330A (ja) * | 2000-04-19 | 2001-11-02 | Oki Electric Ind Co Ltd | 半導体集積回路装置 |
JP3808700B2 (ja) * | 2000-12-06 | 2006-08-16 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6919236B2 (en) * | 2002-03-21 | 2005-07-19 | Advanced Micro Devices, Inc. | Biased, triple-well fully depleted SOI structure, and various methods of making and operating same |
-
2004
- 2004-01-30 EP EP04706606A patent/EP1588418A1/de not_active Withdrawn
- 2004-01-30 US US10/543,923 patent/US7195961B2/en not_active Expired - Lifetime
- 2004-01-30 WO PCT/DE2004/000147 patent/WO2004068579A1/de active Search and Examination
- 2004-01-30 AU AU2004208199A patent/AU2004208199A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4441724A1 (de) * | 1994-11-23 | 1996-05-30 | Siemens Ag | SOI-Substrat |
US5805497A (en) * | 1996-03-29 | 1998-09-08 | Nec Corporation | Semiconductor static random access memory cell with additional capacitor coupled to memory nodes and process of fabrication thereof |
WO1999033115A1 (en) * | 1997-12-19 | 1999-07-01 | Advanced Micro Devices, Inc. | Silicon-on-insulator configuration which is compatible with bulk cmos architecture |
EP0948054A2 (de) * | 1998-03-27 | 1999-10-06 | International Business Machines Corporation | Vergrabene strukturierte Leiterebenen für einen integrierten Halbleiterschaltkreis auf einem Isolator |
US20030001658A1 (en) * | 2000-11-28 | 2003-01-02 | Koichi Matsumoto | Semiconductor device |
US20020063285A1 (en) * | 2000-11-29 | 2002-05-30 | De-Yuan Wu | SOI device and method of fabrication |
Non-Patent Citations (2)
Title |
---|
LU Q ET AL: "High voltage silicon-on-insulator (SOI) MOSFETs", POWER SEMICONDUCTOR DEVICES AND ICS, 1991. ISPSD '91., PROCEEDINGS OF THE 3RD INTERNATIONAL SYMPOSIUM ON BALTIMORE, MD, USA 22-24 APRIL 1991, NEW YORK, NY, USA,IEEE, US, 22 April 1991 (1991-04-22), pages 36 - 39, XP010044310, ISBN: 0-7803-0009-2 * |
See also references of EP1588418A1 * |
Also Published As
Publication number | Publication date |
---|---|
US20060154430A1 (en) | 2006-07-13 |
AU2004208199A1 (en) | 2004-08-12 |
EP1588418A1 (de) | 2005-10-26 |
US7195961B2 (en) | 2007-03-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102013112012B4 (de) | Halbleitervorrichtungen und Verfahren zum Herstellen einer Halbleitervorrichtung | |
DE10250832B4 (de) | MOS-Transistor auf SOI-Substrat mit Source-Durchkontaktierung und Verfahren zur Herstellung eines solchen Transistors | |
DE102012205742B4 (de) | Vertikale Halbleiteranordnung und Verfahren zur Herstellung | |
EP0833386A1 (de) | Durch Feldeffekt steuerbares, vertikales Halbleiterbauelement | |
DE112012002823T5 (de) | Bipolartransistor mit isoliertem Gate | |
DE112009002330T5 (de) | Leistungs-Mosfet mit einem verspannten Kanal in einer Halbleiter-Heterostruktur auf Metallsubstrat | |
DE102008051245A1 (de) | Hochvolttransistor mit hoher Stromtragfähigkeit und Verfahren zur Herstellung | |
DE3806164C2 (de) | ||
DE19720215B4 (de) | Verfahren zum Herstellen von Halbleiterbauteilen mit einem Graben-Gate mittels Seitenwandimplantation | |
DE102015106185B4 (de) | Halbleiterstruktur und Verfahren zur Verarbeitung eines Trägers | |
DE102006015076A1 (de) | Halbleiterbauelement mit SOI-Transistoren und Vollsubstrattransistoren und ein Verfahren zur Herstellung | |
EP0652594B1 (de) | Integrierte Schaltungsanordnung mit Leistungsbauelement und Niederspannungsbauelementen | |
EP0687013B1 (de) | Bipolartransistor und Herstellungsverfahren | |
DE102016202110B4 (de) | Halbleiterstruktur mit Backgate-Gebieten und Verfahren für ihre Herstellung | |
DE4041050A1 (de) | Integrierter schaltkreis | |
EP1581966A2 (de) | Verfahren zur herstellung eines halbleiterbauelements | |
DE112006001280B4 (de) | Halbleitervorrichtung und Verfahren zu deren Herstellung | |
DE102009011349B4 (de) | Halbleiterbauelemente und Verfahren zur Herstellung von Halbleiterchips | |
DE102018102949B4 (de) | Verfahren zur herstellung einer leistungs-halbleitervorrichtung | |
DE102014211904B4 (de) | Halbleitervorrichtung | |
EP0716453B1 (de) | MOSFET auf SOI-Substrat | |
EP1122796B1 (de) | Vertikales Halbleiterbauelement mit Source-Down-Design und entsprechendes Herstellungsverfahren | |
DE2141695B2 (de) | Verfahren zum herstellen eines monolithischen halbleiterbauelementes | |
EP1588418A1 (de) | Soi struktur mit substratkontakten beidseits der box und herstellungs-verfahren für eine solche struktur | |
DE102005024943B4 (de) | Soi-igbt |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BW BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE EG ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NA NI NO NZ OM PG PH PL PT RO RU SC SD SE SG SK SL SY TJ TM TN TR TT TZ UA UG US UZ VC VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWE | Wipo information: entry into national phase |
Ref document number: 541028 Country of ref document: NZ |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1020057013306 Country of ref document: KR |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004706606 Country of ref document: EP Ref document number: 20048031432 Country of ref document: CN |
|
ENP | Entry into the national phase |
Ref document number: 2006154430 Country of ref document: US Kind code of ref document: A1 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10543923 Country of ref document: US |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2004208199 Country of ref document: AU |
|
ENP | Entry into the national phase |
Ref document number: 2004208199 Country of ref document: AU Date of ref document: 20040130 Kind code of ref document: A |
|
WWP | Wipo information: published in national office |
Ref document number: 2004208199 Country of ref document: AU |
|
WWP | Wipo information: published in national office |
Ref document number: 1020057013306 Country of ref document: KR |
|
WWP | Wipo information: published in national office |
Ref document number: 2004706606 Country of ref document: EP |
|
DPEN | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed from 20040101) | ||
WWP | Wipo information: published in national office |
Ref document number: 10543923 Country of ref document: US |