WO2004051733A1 - Thin gaas die with copper back-metal structure - Google Patents

Thin gaas die with copper back-metal structure Download PDF

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Publication number
WO2004051733A1
WO2004051733A1 PCT/US2003/030861 US0330861W WO2004051733A1 WO 2004051733 A1 WO2004051733 A1 WO 2004051733A1 US 0330861 W US0330861 W US 0330861W WO 2004051733 A1 WO2004051733 A1 WO 2004051733A1
Authority
WO
WIPO (PCT)
Prior art keywords
microns
gaas substrate
semiconductor device
metal layer
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2003/030861
Other languages
English (en)
French (fr)
Inventor
Alexander J. Elliott
Jeffrey Dale Crowder
Monte Gene Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, Motorola Inc filed Critical Freescale Semiconductor Inc
Priority to AU2003277129A priority Critical patent/AU2003277129A1/en
Priority to JP2004557131A priority patent/JP2006517054A/ja
Priority to CN038254352A priority patent/CN1720610B/zh
Publication of WO2004051733A1 publication Critical patent/WO2004051733A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/70—Fillings or auxiliary members in containers or in encapsulations for thermal protection or control
    • H10W40/77—Auxiliary members characterised by their shape
    • H10W40/778—Auxiliary members characterised by their shape in encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

  • This invention relates generally to semi-conductor devices, and more particularly to Gallium Arsenide (GaAs) semiconductor devices.
  • GaAs Gallium Arsenide
  • Ceramic packages are preferred over plastic packages in some instances (e.g. when hemeticity and/or high frequency is required), but plastic packages are generally preferred over ceramic packages because plastic packages are less expensive.
  • Plastic packages are routinely used to package silicon die, however, attempts to package GaAs semiconductor die in plastic packages have proven somewhat problematic.
  • GaAs die i.e. those die having a thickness greater than about 3 mils
  • GaAs die limit the maximum power capabilities that can be implemented.
  • Tn order to overcome the power dissipation problems and allow more complex circuits, attempts have been made to reduce the thickness of the GaAs die to less than 3 mils.
  • the die handling processes associated with packaging are incompatible with thin, i.e. less than 3 mils, GaAs die.
  • the use of a thick, about 18 ⁇ m, gold back metal layer has been proposed in an attempt to strengthen GaAs die thinned for power dissipation purposes.
  • the thick gold back-metal layer is incompatible with plastic packaging processes for at least two reasons: 1) the thick gold causes embrittlement of the soft-solder used in plastic packaging processes to attach the semiconductor die to the lead-frame; and 2) gold tends to de-laminate from a plastic package. What is needed, therefore, is a way to allow high-powered GaAs semiconductor die to be used in plastic packages. By allowing a high-powered semiconductor die to be used in a plastic package, substantial cost savings could be achieved without performance loss.
  • FIG. 1 is a diagram of a thin GaAs semiconductor die having a copper back-metal structure according to an embodiment of the present disclosure.
  • FIG. 2 is a thin GaAs die having a copper back-metal structure encapsulated in a plastic package according to an embodiment of the present disclosure.
  • FIGS. 1-2 illustrate a thin GaAs die with a copper back-metal structure suitable for use in a plastic package, in accordance with the present disclosure.
  • various anti-stress and oxidation resistant layers are shown in addition to the copper back-metal layer.
  • FIG. 2 illustrates a completed semiconductor die encapsulated in a plastic package.
  • the GaAs substrate is less than 2 mils (about 50 microns) thick, and particular embodiments of the GaAs substrate of the semiconductor die have thicknesses of approximately 1-2 mils (about 25-50 microns), less than approximately 1.5 mils (about 38 microns), or less than or equal to approximately 1 mil (about 25 microns).
  • the copper back-metal layer provides both mechanical strength and improved heat dissipation properties to the GaAs die, and makes the GaAs die compatible with soft-solder die attach technologies.
  • Soft solder die attach refers to die attach methods using soft solders that generally comprise about 5% tin and 95% lead. Since soft-solder die attached methods are used when preparing a semiconductor die for encapsulation in a plastic package, the thin GaAs substrate with copper back-metal layer can be packaged in a plastic package.
  • Die 300 includes a GaAs Substrate 310 in which a semiconductor circuit is formed using methods known to those skilled in the art. While not shown in FIG. 1, GaAs Substrate 310 may also include various interconnection terminals on top of GaAs Substrate 310 for connecting Die 300 to leads during the packaging process.
  • a Diffusion Barrier 320 is formed over the bottom of GaAs Substrate 310, such that any subsequent layers formed over Diffusion Barrier 320 will not adversely impact the semiconductor circuits within GaAs Substrate 310.
  • Diffusion Barrier 320 includes an adhesion metal such as tantalum deposited in the form of tantalum nitride, or another suitable diffusion barrier known to those skilled in the art.
  • over or “overlying” is used to describe a layer formed completely or partially over another layer or surface.
  • overlying is used irrespective of the surface of the substrate on which overlying layer is formed.
  • a layer formed on the backside surface of a substrate and a layer formed on an active surface of a substrate are both considered to be overlying the substrate.
  • a Stress Relief Layer 330 is formed over Diffusion Barrier 320 in at least one embodiment.
  • Stress Relief Layer 330 provides protection for GaAs Substrate 310 and or diffusion layer 320 from uneven expansion, contraction or other physical movements of a back-metal or other layer overlying Stress Relief Layer 330.
  • gold is used as a stress relief layer. While FIG. 1 illustrates a single stress relief layer, using more than one stress relief layer does not depart from the spirit and scope of the present invention.
  • Copper Back-metal Layer 340 On top of Stress Relief Layer 330, a Copper Back-metal Layer 340 is formed. Copper Back-metal Layer 340 has a thickness chosen to be sufficient to provide the necessary support for GaAs Substrate 310 during the packaging process, including the process of soft-solder die attach. For example, a 3-mil-thick (about 16 microns) GaAs die needs very little, if any, additional mechanical support. Consequently, a 3-mil-thick (about 76 microns) GaAs die may not include Copper Back-metal Layer 340. However, a 1 mil thick (about 25 microns) GaAs die may include a Copper Back-metal layer 340 having a thickness of between about 11-15 microns to provide the additional mechanical support.
  • An appropriate thickness for Copper Back-metal Layer 340 can be selected empirically. For example, if it is known that 18-19 microns of gold are needed to provide adequate mechanical strength for a 25 micron thick GaAs die, then using the known physical properties of gold and copper, for example tensile strength, malleability, etc., the thickness of copper needed to provide an equivalent mechanical stability can be calculated.
  • Copper Metal Back layer 340 provides improved heat dissipation as compared to a thick GaAs substrate.
  • GaAs Substrate 310 can be made thinner and still dissipate enough heat through the use of the Copper Metal Back layer 340 to support high power circuits formed overlying the thin GaAs Substrate 310.
  • Those skilled in the art can readily calculate the amount of heat dissipation required by the circuits, and incorporate that information in their decision ⁇ regarding the thickness of Copper Back-metal Layer 340.
  • Oxidation Resistant Layer 350 is formed over Copper Back-metal Layer 340 to prevent oxidation of Copper Back-metal Layer 340.
  • Oxidation of Copper Back-metal Layer 340 is undesirable, since oxidation can adversely affect both the electrical and heat transfer properties of Copper Back-metal Layer 340.
  • the oxidation can adversely affect the bonding of Copper Back-metal layer 340 to the packaging (e.g. to the solder).
  • Oxidation Resistant Layer 340 is a thin layer of gold about 1500 Angstroms thick, which is referred to as a flash of gold.
  • Oxidation Resistant Layer 350 should be limited, particularly when gold is used, because solder embrittlement may occur due to soft-solder attachment of Die 300 to a lead frame if the Oxidation Resistant Layer 350 is formed too thick.
  • the semiconductor die shown in FIG. 1 is compatible with soft-solder die attach processes that are commonly used during packaging operations.
  • the GaAs Substrate 310 is less than 2 mils thick, thereby allowing a relatively high power circuit to be formed in GaAs Substrate 310.
  • GaAs Substrate 310 is less than 1 mil thick, and in at least one embodiment, GaAs Substrate 410 is nominally 1 mil (about 25 microns).
  • the use of Copper Back-metal Layer 340 also permits Die 300 to be packaged in a plastic package, because
  • Semiconductor Die 300 is compatible with soft-solder die attach methods.
  • FIG. 2 a semiconductor die having a thin GaAs substrate and a copper back-metal layer are illustrated inside of a plastic package according to an embodiment of the present invention.
  • the packaged die will be referred to as Packaged Die 500.
  • the semiconductor die illustrated in FIG.2 includes a thin GaAs Substrate 510 (in one embodiment having a thickness in the range of 15-35 microns), a Diffusion Barrier 520, a Copper Back-metal Layer 530 and an Oxidation Resistant Layer 540.
  • the semiconductor die is attached to Flag 560 using a soft-solder die attach method.
  • Flag 560 is coated with Soft-solder Layer 590.
  • Soft-solder Layer 590 is a layer of soft-solder, which in at least one embodiment comprises 5% tin and 95% lead. In alternate embodiments, eutectic solder or conductive epoxies can be used.
  • Soft-solder Layer 590 is heated, and brought into contact with the oxidation resistant layer 540 of the semiconductor die.
  • the Oxidation Resistant Layer 540, a portion of the Copper Back- metal Layer 530 and Soft-solder Layer 590 melt such that the components of each of the layers intermingle with the others to form a solder joint when the heat is removed and the materials are allowed to cool.
  • Soft-solder Layer 590 is adjacent to Copper Back-metal Layer 530, and the material in Oxidation Resistant Layer 540 (e.g. gold) is present within Soft-solder Layer 590, and at the interface between Soft-solder Layer 590 and Copper Back-metal Layer 530.
  • Bonding Wires 582 are bonded to the die and Bonding Fingers 580, and then the assembly is in a mold die.
  • a mold die Usually a plurality of such assemblies, e.g. as exist in a lead frame, is placed in a mold die.
  • a thermoset plastic compound is transferred into a cavity of the mold die to encapsulate the semiconductor die, thus forming a completed semiconductor package such as Plastic Package 500.
  • the thermoset plastic may be cured, and further processing (e.g. lead trim and form, package marking, and test) occur in a conventional manner.
  • a thin GaAs Substrate can be provided with a copper back- metal layer to allow the GaAs Substrate to be packaged using conventional plastic packaging technologies.
  • the GaAs substrate can be made thinner than 2 mils (about 50 microns), thereby reducing heat dissipation problems as well as allowing the semiconductor die to be compatible with soft-solder techniques.
  • substantial cost savings can be achieved.

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Electrodes Of Semiconductors (AREA)
PCT/US2003/030861 2002-11-27 2003-09-30 Thin gaas die with copper back-metal structure Ceased WO2004051733A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU2003277129A AU2003277129A1 (en) 2002-11-27 2003-09-30 Thin gaas die with copper back-metal structure
JP2004557131A JP2006517054A (ja) 2002-11-27 2003-09-30 銅裏面金属構造を備えるＧａＡｓ薄型ダイ
CN038254352A CN1720610B (zh) 2002-11-27 2003-09-30 具有铜背部金属结构的薄GaAs管芯

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/308,334 2002-11-27
US10/306,834 US6870243B2 (en) 2002-11-27 2002-11-27 Thin GaAs die with copper back-metal structure

Publications (1)

Publication Number Publication Date
WO2004051733A1 true WO2004051733A1 (en) 2004-06-17

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PCT/US2003/030861 Ceased WO2004051733A1 (en) 2002-11-27 2003-09-30 Thin gaas die with copper back-metal structure

Country Status (7)

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US (2) US6870243B2 (https=)
JP (1) JP2006517054A (https=)
KR (1) KR20050085143A (https=)
CN (1) CN1720610B (https=)
AU (1) AU2003277129A1 (https=)
TW (1) TWI339425B (https=)
WO (1) WO2004051733A1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6870243B2 (en) * 2002-11-27 2005-03-22 Freescale Semiconductor, Inc. Thin GaAs die with copper back-metal structure
US6833289B2 (en) * 2003-05-12 2004-12-21 Intel Corporation Fluxless die-to-heat spreader bonding using thermal interface material
US20050085084A1 (en) * 2003-10-16 2005-04-21 Chang Edward Y. Method of fabricating copper metallization on backside of gallium arsenide devices
US7221055B2 (en) * 2005-05-23 2007-05-22 Texas Instruments Incorporated System and method for die attach using a backside heat spreader
US7923842B2 (en) 2006-03-16 2011-04-12 Skyworks Solutions, Inc. GaAs integrated circuit device and method of attaching same
CN100449740C (zh) * 2006-06-19 2009-01-07 上海集成电路研发中心有限公司 降低半导体器件发热的散热方法、相应器件及其制造方法
JP4917375B2 (ja) * 2006-07-25 2012-04-18 株式会社豊田中央研究所 パワー半導体モジュールの製造方法
WO2008060447A2 (en) * 2006-11-09 2008-05-22 Quantum Leap Packaging, Inc. Microcircuit package having ductile layer
US20090108437A1 (en) * 2007-10-29 2009-04-30 M/A-Com, Inc. Wafer scale integrated thermal heat spreader
JP5103245B2 (ja) * 2008-03-31 2012-12-19 ルネサスエレクトロニクス株式会社 半導体装置
US8987878B2 (en) * 2010-10-29 2015-03-24 Alpha And Omega Semiconductor Incorporated Substrateless power device packages
US8415805B2 (en) 2010-12-17 2013-04-09 Skyworks Solutions, Inc. Etched wafers and methods of forming the same
JP2013098481A (ja) * 2011-11-04 2013-05-20 Sumitomo Electric Device Innovations Inc 半導体装置
US8900969B2 (en) 2012-01-27 2014-12-02 Skyworks Solutions, Inc. Methods of stress balancing in gallium arsenide wafer processing
CN103377914A (zh) * 2012-04-18 2013-10-30 稳懋半导体股份有限公司 半导体元件背面铜金属的改良结构及其加工方法
US9093506B2 (en) 2012-05-08 2015-07-28 Skyworks Solutions, Inc. Process for fabricating gallium arsenide devices with copper contact layer
JP2014099547A (ja) * 2012-11-15 2014-05-29 Mitsubishi Electric Corp 電力半導体モジュールおよびその製造方法
US9530719B2 (en) 2014-06-13 2016-12-27 Skyworks Solutions, Inc. Direct die solder of gallium arsenide integrated circuit dies and methods of manufacturing gallium arsenide wafers
TWI660471B (zh) * 2017-10-06 2019-05-21 財團法人工業技術研究院 晶片封裝
US11133241B2 (en) 2019-06-28 2021-09-28 Stmicroelectronics, Inc. Semiconductor package with a cavity in a die pad for reducing voids in the solder
CN112989744B (zh) * 2021-02-08 2023-11-17 泰凌微电子(上海)股份有限公司 一种半导体芯片的封装设计方法以及装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0194475A2 (en) * 1985-03-14 1986-09-17 Olin Corporation Semiconductor die attach system
US5821154A (en) * 1995-01-27 1998-10-13 Nec Corporation Semiconductor device
EP1063701A2 (en) * 1999-06-24 2000-12-27 Intersil Corporation Backmetal drain terminal with low stress and thermal resistance

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755720A (en) * 1972-09-25 1973-08-28 Rca Corp Glass encapsulated semiconductor device
US3942186A (en) * 1973-10-09 1976-03-02 Westinghouse Electric Corporation High frequency, field-effect transistor
US4321099A (en) * 1979-11-13 1982-03-23 Nasa Method of fabricating Schottky barrier solar cell
US4543442A (en) * 1983-06-24 1985-09-24 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration GaAs Schottky barrier photo-responsive device and method of fabrication
JPS61174723A (ja) * 1985-01-30 1986-08-06 Mitsubishi Electric Corp 半導体装置の製造方法
US4872047A (en) * 1986-11-07 1989-10-03 Olin Corporation Semiconductor die attach system
US4989117A (en) * 1990-02-12 1991-01-29 Rogers Corporation Molded integrated circuit package incorporating thin decoupling capacitor
JPH04225536A (ja) * 1990-12-27 1992-08-14 Nikko Kyodo Co Ltd 化合物半導体装置の製造方法
JPH05243396A (ja) * 1992-03-02 1993-09-21 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2978351B2 (ja) * 1993-02-16 1999-11-15 株式会社日立製作所 樹脂封止型半導体装置
US5545289A (en) * 1994-02-03 1996-08-13 Applied Materials, Inc. Passivating, stripping and corrosion inhibition of semiconductor substrates
IT1274129B (it) * 1994-11-29 1997-07-15 Soriani & Moser Manufacturers Giostra di divertimento di tipo perfezionato
US5528076A (en) * 1995-02-01 1996-06-18 Motorola, Inc. Leadframe having metal impregnated silicon carbide mounting area
US5622305A (en) * 1995-05-10 1997-04-22 Lucent Technologies Inc. Bonding scheme using group VB metallic layer
JPH09306932A (ja) * 1996-05-17 1997-11-28 Sanyo Electric Co Ltd 半導体装置の製造方法
US6105865A (en) * 1998-07-17 2000-08-22 Hardesty; Laurence Daniel Financial transaction system with retirement saving benefit
US6010966A (en) * 1998-08-07 2000-01-04 Applied Materials, Inc. Hydrocarbon gases for anisotropic etching of metal-containing layers
JP3690171B2 (ja) * 1999-03-16 2005-08-31 株式会社日立製作所 複合材料とその製造方法及び用途
US6609106B1 (en) * 1999-05-07 2003-08-19 Steven C. Robertson System and method for providing electronic multi-merchant gift registry services over a distributed network
US6426289B1 (en) * 2000-03-24 2002-07-30 Micron Technology, Inc. Method of fabricating a barrier layer associated with a conductor layer in damascene structures
TWI248384B (en) * 2000-06-12 2006-02-01 Hitachi Ltd Electronic device
US6551852B2 (en) * 2001-06-11 2003-04-22 Micron Technology Inc. Method of forming a recessed magnetic storage element
JP2003045875A (ja) * 2001-07-30 2003-02-14 Nec Kagobutsu Device Kk 半導体装置およびその製造方法
US6583500B1 (en) * 2002-02-11 2003-06-24 Texas Instruments Incorporated Thin tin preplated semiconductor leadframes
US6787910B2 (en) * 2002-07-23 2004-09-07 National Chiao Tung University Schottky structure in GaAs semiconductor device
US6870243B2 (en) * 2002-11-27 2005-03-22 Freescale Semiconductor, Inc. Thin GaAs die with copper back-metal structure
US20040146138A1 (en) * 2003-01-23 2004-07-29 Motorola, Inc. Large flat panel gallium arsenide arrays on silicon substrate for low dose X-ray digital imaging

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0194475A2 (en) * 1985-03-14 1986-09-17 Olin Corporation Semiconductor die attach system
US5821154A (en) * 1995-01-27 1998-10-13 Nec Corporation Semiconductor device
EP1063701A2 (en) * 1999-06-24 2000-12-27 Intersil Corporation Backmetal drain terminal with low stress and thermal resistance

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHEN C Y ET AL: "Backside copper metallisation of GaAs MESFETs", ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 36, no. 15, 20 July 2000 (2000-07-20), pages 1317 - 1318, XP006015473 *
CHEN C-Y ET AL: "BACKSIDE COPPER METALLIZATION OF GAAS MESFETS USING TAN AS THE DIFFUSION BARRIER", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 48, no. 6, June 2001 (2001-06-01), pages 1033 - 1036, XP001082386, ISSN: 0018-9383 *
GREBS T ET AL: "THE USE OF COPPER BASED BACKMETAL SCHEMES AS A LOW STRESS AND LOW THERMAL RESISTANCE ALTERNATIVE FOR USE IN THIN SUBSTRATE POWER DEVICES", PROCEEDINGS OF THE ELECTROCHEMICAL SOCIETY, NEW YORK,NY, US, 3 May 1999 (1999-05-03), pages 185 - 193, XP008011990 *

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Publication number Publication date
AU2003277129A1 (en) 2004-06-23
US20050127480A1 (en) 2005-06-16
CN1720610B (zh) 2010-10-13
JP2006517054A (ja) 2006-07-13
TW200416970A (en) 2004-09-01
US7092890B2 (en) 2006-08-15
TWI339425B (en) 2011-03-21
US6870243B2 (en) 2005-03-22
US20040099932A1 (en) 2004-05-27
CN1720610A (zh) 2006-01-11
KR20050085143A (ko) 2005-08-29

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