WO2004047163A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- WO2004047163A1 WO2004047163A1 PCT/JP2003/014513 JP0314513W WO2004047163A1 WO 2004047163 A1 WO2004047163 A1 WO 2004047163A1 JP 0314513 W JP0314513 W JP 0314513W WO 2004047163 A1 WO2004047163 A1 WO 2004047163A1
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- WIPO (PCT)
- Prior art keywords
- semiconductor device
- film
- pattern
- interlayer film
- lsi chip
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000011229 interlayer Substances 0.000 claims abstract description 68
- 230000007246 mechanism Effects 0.000 claims abstract description 18
- 230000003014 reinforcing effect Effects 0.000 claims description 68
- 239000010410 layer Substances 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 17
- 230000001629 suppression Effects 0.000 claims description 14
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims 2
- 230000000452 restraining effect Effects 0.000 claims 2
- 239000010949 copper Substances 0.000 description 27
- 238000000034 method Methods 0.000 description 16
- 230000000694 effects Effects 0.000 description 11
- 230000002787 reinforcement Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000002250 progressing effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000003416 augmentation Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Definitions
- the present invention relates to a semiconductor device including a low dielectric constant (1 ow — k) film having a dielectric constant of k ⁇ 3.0.
- LSI LargeScaleIntgegrattedccircuiit
- a method of manufacturing an LSI chip 10 using a low-k film as an interlayer film and using two-layer Cu damascene wiring will be described.
- a first interlayer film 12 is deposited on a silicon (Si) substrate 11.
- a first wiring layer 21a is formed on the surface through a predetermined damascene wiring process.
- a stopper material for example, a SiCN film
- a second interlayer film are formed on the first interlayer film 12 including the surface of the first wiring layer 21a.
- a 1 ow _ k film for example, a SiOC film
- a contact via 21 b connected to the first wiring layer 21 a is formed on the 1 ow-k film 14 and the stopper material 13.
- a second wiring layer 21 c connected to the via 21 b is formed on the surface of the 1 ow-k film 14 through a predetermined damascene wiring process.
- the two-layer damascene wiring structure two-layer Cu (Damascene wiring) 2 1 is completed.
- a stopper material 15 and a passivation film 16 are sequentially deposited.
- LSI chip 10 is assembled on the wafer 1 as shown in FIG. 13, for example.
- the wafer 1 is diced along the cutting line (the dashed line in the drawing) along the dicing section 2c .
- the wafer 1 is manufactured as described above.
- LSI chip 10 is separated for each chip.
- the end of the LSI chip 10 receives the damage 30 due to the dicing as shown in FIG. 14, for example.
- the LSI chips 10 separated in chip units are individually packaged, for example, as shown in FIG. That is, the LSI chip 10 is mounted on the mounting substrate 101 by using the mounting material 103. Then, each electrode pad of the LSI chip 10 is individually connected to the bump electrode 102 on the mounting board 101 by a bonding wire 104. Thereafter, the periphery of the LSI chip 10 is sealed with a sealing resin 105. At this time, the sealing resin 105 undergoes curing shrinkage.
- the 1 ow-k film 14 has a low film density. For this reason, the 1 ow-k film 14 has low adhesion strength to the lower stopper material 13. As a result, for example, as shown in FIG. 16A, in the LSI chip 10, when the sealing resin 105 hardens and contracts, the 1 ow-k film 14 peels (interlayer film peeling). 40 tends to occur. This The interlayer film peeling 40 is mainly caused by the part of the 1 ow-k film 14 and the stopper material 13 starting from the part of the edge of the LSI chip 10 that has been damaged by dicing 30. Occurs at the interface.
- interlayer peeling 40 occurs selectively from a part of the corner of LSI chip 10 as shown in FIG. 16B, for example.
- the generated interlayer film peeling 40 disconnects the wiring structure 21 inside the LSI chip 10. This leads to wiring defects and lowers the yield of the LSI chip 10.
- LSI failure may occur in the future. That is, in the subsequent use of the LSI chip 10, stress is applied to the LSI chip 10 due to, for example, a temperature difference caused by turning on and off the power supply. Then, the interlayer film peeling 40 proceeds due to the stress. This results in LSI failure.
- a 1 ow-k film as the interlayer film in the past, separation of the interlayer film from the interface of the 1 ow-k film, especially from the corner of the chip, has occurred. There was a problem that it was easy to do.
- the present invention provides a semiconductor device capable of suppressing interlayer film peeling due to weak adhesion strength of a 1 ow_k film and damage at the time of dicing, and preventing LSI failure due to interlayer film peeling. It is intended for this purpose.
- a semiconductor device using a low dielectric constant film having a dielectric constant of k ⁇ 3.0 as an interlayer film the semiconductor device including a suppression mechanism for suppressing a film peeling failure of the interlayer film.
- FIGS. 1A to 1E are configuration diagrams showing an example of an LSI chip according to the first embodiment of the present invention.
- FIGS. 2A to 2E are plan views illustrating an example of a reinforcing pattern in an LSI chip according to a second embodiment of the present invention.
- 3A to 3E are plan views showing still another example of the intensification pattern in the LSI chip according to the second embodiment of the present invention.
- FIG. 4 shows a case where the reinforcing pattern according to the first embodiment is combined with the reinforcing pattern according to the second embodiment.
- FIG. 3 is a plan view of an LSI chip, showing an example.
- 5A to 5D are configuration diagrams illustrating an example of an LSI chip according to the third embodiment of the present invention.
- 6A to 6E are plan views showing an example of a reinforcing pattern in an LSI chip according to a fourth embodiment of the present invention.
- FIG. 7A to 7C are plan views showing still another example of the reinforcing pattern in the LSI chip according to the fourth embodiment of the present invention.
- FIG. 8 is a plan view of an LSI chip showing an example in which a reinforcing pattern according to the first embodiment and a reinforcing pattern according to the fourth embodiment are combined.
- FIG. 9 is a plan view of an LSI chip showing an example of a case where a reinforcing pattern according to the third embodiment and a reinforcing pattern according to the fourth embodiment are combined.
- FIGS. 10A to 10D are configuration diagrams illustrating an example of an LSI chip according to a fifth embodiment of the present invention.
- FIGS. 11A to 11C are configuration diagrams illustrating an example of an LSI chip according to a sixth embodiment of the present invention.
- FIG. 12 is a cross-sectional view of an LSI chip shown to explain a conventional technique and its problems.
- FIG. 13 is a plan view showing the wafer before the LSI chip is cut out by dicing.
- FIG. 14 is a cross-sectional view of an LSI chip shown for explaining the damage given by dicing.
- FIG. 15 is a cross-sectional view showing an example of packaging of an LSI chip.
- Figures 16A and 16B are configuration diagrams of the LSI chip shown to explain the interlayer peeling failure.
- FIG. 1A to 1E show a configuration example of an LSI chip according to a first embodiment of the present invention.
- the present invention is applied to an LSI chip (for example, see FIG. 12) having a two-layer Cu damascene wiring employing a 1 ow-k film as an interlayer film.
- the LSI chip 10 is provided with an augmentation pattern 20 as a suppression mechanism for stopping the progress of interlayer film peeling at the outer peripheral portion.
- the reinforcing pattern 20 is composed of a plurality of (three in this example) dummy wiring patterns.
- the wiring pattern of each dummy is formed to have a two-layer damascene wiring structure, for example, as shown in FIG. 1C. More specifically, each dummy wiring pattern is composed of first and second Cu layers 20a and 20c, and the first and second Cu layers 20a and 20c. It is formed by vias 20b that connect each other.
- Fig. 1D shows the side surface of the intensification pattern 20 (cross section along the line Id-Id in Fig. 1C).
- a method of manufacturing the LSI chip 10 ′ including the reinforcing pattern 20 First, a first interlayer film 12 is deposited on the Si substrate 11. Then, a first wiring layer 21a and a first Cu layer 20a made of Cu are formed on the surface through a predetermined damascene wiring process. Next, on the first interlayer film 12 including the surface of the first wiring layer 21a and the surface of the first Cu layer 20a, a stopper material (for example, S i CN film) 13 is deposited. Next Ide, thereon, 1 o W of the second interlayer film - k film (.
- the material 13 includes a contact via 21 b connected to the first wiring layer 21 a, and a first via 21 b. Eleven layers 20 & Contact vias 2 Ob are connected to each other. Then, through a predetermined damascene wiring process, a second wiring layer 21c and a second Cu layer 20c connected to the vias 21b and 2Ob, respectively, are formed.
- a two-layer damascene wiring structure composed of Cu force (two-layer Cu damascene wiring) 21 and a reinforcement pattern 20 having substantially the same structure as the above wiring structure 21 are simultaneously completed.
- a reinforcing pattern 20 which partially eliminates the interface of the 1 ow-k film 14 is arranged so as to surround the outer periphery of the LSI chip 10 ′.
- a stopper material 15 and a passivation film 16 are sequentially deposited.
- the LSI chip 10 ′ manufactured as described above has a film density of 1 ow-k film 14 due to the reinforcing pattern 20 on the outer peripheral portion. Is low due to the low adhesive strength to the stopper material 13 (or the stopper material 15), and the interlayer film peeling due to damage 30 caused by dicing 4 Very strong against 0. As a result, even if the end of the LSI chip 10 ′
- the reinforcing pattern 20 has a two-layer Cu damascene wiring structure, and can be formed simultaneously with the wiring structure 21 by the same process. Therefore, it can be easily realized without adding a process or complicated control.
- the reinforcing pattern 20 need not necessarily be formed to have a two-layer Cu damascene wiring structure.
- the coercive pattern 20 can be formed using a wiring material other than Cu.
- FIGS. 2A to 2E and FIGS. 3A to 3E show configuration examples of an LSI chip according to the second embodiment of the present invention.
- the corners of the chip serve as suppression mechanisms.
- the case where the reinforcement pattern (wiring pattern) 50 of the above is arranged will be described.
- a reinforcing pattern 50 for stopping the progress of interlayer film peeling is provided at each corner.
- the reinforcing pattern 50 is arranged so as to partially eliminate the interface of the low-k film at each corner of the LSI chip 10a.
- various dummy wiring patterns 50a and 50b as shown in FIGS. 2B to 2E and 3A to 3D, for example, are used.
- 50c, 50d, 50e, 5Of, 50g, and 50h can be used.
- Various dummy arrangement / wire patterns 50 a, 50 b, 50 c, 50 d, 50 e, 5 O f, 50 g, 50 h are, for example, in the case of the first embodiment. Similarly, both have a two-layer damascene wiring structure made of Cu.
- Such a reinforcing pattern 50 is arranged at each corner of the LSI chip 10a where the interlayer film is liable to peel off. As a result, the same effect as that of the LSI chip 10 'shown in the above-described first embodiment can be expected. That is, as shown in FIG. 3E, the reinforcement pattern 50 can prevent the interlayer film peeling 40 from proceeding. Therefore, not only at the time of assembly but also after the assembly process, LSI failures such as disconnection of the wiring structure inside the LSI chip 10a as the interlayer film peeling 40 progresses can be prevented. It can be prevented.
- the reinforcing pattern 50 when configured to have a two-layer Cu damascene wiring structure, LSIs can be added without requiring additional processes and complicated control. Chip 10a can be easily realized.
- the reinforcing pattern 50 need not necessarily be formed to have a two-layer Cu damascene wiring structure. Further, the reinforcement pattern 50 can be formed using a wiring material other than Cu.
- the reinforcing pattern 50 of the second embodiment can be used in combination with the reinforcing pattern 20 of the above-described first embodiment.
- the LSI chip 10b is provided with a reinforcement pattern 50 of the second embodiment and a reinforcement pattern 20 of the first embodiment. According to such a configuration, the reinforcing patterns 20 and 50 can more reliably prevent the interlayer film peeling from progressing.
- 5A to 5D show a configuration example of an LSI chip according to a third embodiment of the present invention.
- a suppression mechanism is provided on the outer periphery of the chip. The following describes a case in which the reinforcing pattern (open pattern) 60 is provided.
- this LSI chip 10 As shown in FIG. 5A and FIG. 5B, this LSI chip 10.
- a reinforcing pattern 60 for stopping the progress of interlayer film peeling is provided on the outer periphery.
- the reinforcing pattern 60 is formed of at least the first interlayer film 12. Is formed by a groove having a depth reaching. That is, the above-mentioned reinforcing pattern 60 is formed by partially removing the interface between 1 ow-k fl and the stopper material 13 by etching or laser. In this way, the reinforcing pattern consisting of an opening pattern formed so as to partially surround the outer peripheral portion of the LSI chip 10c so as to eliminate the 1 ow-k film 14 is formed. 60 is placed.
- the reinforcing pattern 60 makes it possible to physically separate the end of the LSI chip 10c from the internal wiring structure 21.
- the reinforcing pattern 60 makes it possible to physically separate the end of the LSI chip 10c from the internal wiring structure 21.
- FIG. 5C and FIG. 5D for example, even if interlayer film peeling 40 due to damage 30 due to dicing occurs, from film peeling 4 0 proceeds more, c therefore and this made possible to prevent the reinforcing pattern 6 0, not only during assembly, even Oite after the assembly process, and the progress of the interlayer film peeling 4 0 As a result, it is possible to prevent an LSI failure such as a disconnection of the wiring structure 21 inside the LSI chip 10c.
- FIGS. 6A to 6E and FIGS. 7A to 7C show configuration examples of an LSI chip according to the fourth embodiment of the present invention.
- the corners of the chip serve as suppression mechanisms.
- the case where the reinforcing pattern (opening pattern) 70 is arranged to be arranged will be described.
- a reinforcing pattern 70 for stopping the progress of interlayer film peeling is provided at each corner.
- the reinforcing pattern 70 is constituted by a groove having a depth at least reaching the first interlayer film 12, as shown in FIG. 5C, for example.
- various open ends as shown in, for example, FIGS. 6B to 6E and FIGS. 7A and 7B, respectively.
- the turns 70a, 70b, 70c, 70d, 70e, and 70 ⁇ can be used.
- the various opening patterns 70 a, 70 b, 70 c, 70 d, 70 e, and 70 f are all the same as in the case of the third embodiment described above, for example.
- -Such a reinforcing pattern 70 is arranged at each corner of the LSI chip 10d, in particular, where the interlayer film peels off.
- the reinforcement pattern 70 can prevent the interlayer film peeling 40 from further progressing. Therefore, not only at the time of assembly but also after the assembly process, LSI failures such as disconnection of the wiring structure inside the LSI chip 10d as the interlayer film peels off 40 can be prevented beforehand. You can do it.
- the reinforcing pattern 70 of the fourth embodiment can be used in combination with the reinforcing pattern 20 of the above-described first embodiment.
- the LSI chip 10e is provided with a reinforcing pattern 70 of the fourth embodiment and a reinforcing pattern 20 of the first embodiment. According to such a configuration, the reinforcing patterns 20 and 70 can more reliably prevent the peeling of the interlayer film from proceeding.
- the reinforcing pattern 70 of the fourth embodiment can be used in combination with the reinforcing pattern 60 of the above-described third embodiment.
- a reinforcement pattern 70 of the fourth embodiment and a reinforcement pattern 60 of the third embodiment are provided on the LSI chip 10f. Even with such a configuration, the reinforcing patterns 60 and 70 can reliably prevent the interlayer film from peeling off.
- FIGS. 10A to 10D show a configuration example of an LSI chip according to a fifth embodiment of the present invention.
- the periphery of the chip (the die of The following describes a case in which a reinforcing pattern (wiring pattern) 80 as a suppression mechanism is disposed in the singing part).
- a reinforcing pattern 80 for suppressing occurrence of peeling of an interlayer film is provided in a dicing portion 2 of an aerial 1, which is a peripheral portion of the LSI chip 10.
- the reinforcing pattern 80 is provided so as to at least partially eliminate the interface of the 1 ow-k film 14. u is composed of a single wiring pattern.
- Such a reinforcing pattern 80 is arranged in the dicing section 2 of the wafer 1 which is particularly susceptible to the damage 30 during dicing.
- substantially the same effects as in the first to fourth embodiments can be expected. That is, as shown in FIG. 10C, it is possible to absorb the damage 30 at the time of dicing by the capturing pattern 80. In other words, damage 30 due to dicing can be prevented from being directly applied to the interface of the low-k film 14. As a result, it is possible to suppress occurrence of interlayer film peeling 40. Therefore, not only at the time of assembly, but also at the assembly process and thereafter, it is possible to solve the problem that the wiring structure 21 inside the LSI chip 10 is disconnected due to the occurrence of interlayer film peeling 40. It is.
- the reinforcing pattern 80 is not limited to the case where the reinforcing pattern 80 is constituted by one wiring pattern.
- the same effect can be obtained when a reinforcing pattern 80a composed of a plurality of (three in this example) wiring patterns is used.
- the LSI chip 10 can be easily manufactured without requiring additional processes or troublesome control.
- the reinforcing patterns 80 and 80a are the same as those in the first embodiment. As shown, it may be formed having a two-layer damascene wiring structure. Also, the reinforcing turns 0 80 and 80a can be formed using a wiring material other than Cu.
- FIGS. 11A to 11C show a configuration example of an LSI chip according to a sixth embodiment of the present invention.
- an LSI chip that employs a 1 ow_k film as an interlayer film and has two layers of Cu damascene wiring (see, for example, Fig. 12)
- the peripheral portion of the chip (Each dicing)
- a description will be given of a case in which a reinforcing pattern (opening pattern) 90 as a suppression mechanism is disposed in the first part.
- a reinforcing pattern 90 for suppressing the occurrence of interlayer film peeling is provided around the dicing portion 2 of the wafer 1, which is the periphery thereof. Have been.
- the reinforcing pattern 90 at least partially eliminates the interface of at least the 1 ow-k film 14 by, for example, etching or laser as shown in FIG. 11B. It is constituted by one groove thus formed.
- Such a reinforcing pattern 90 is arranged in the dicing section 2 of the wafer 1 which is particularly susceptible to damage 30 during dicing. Thereby, substantially the same effects as those of the above-described first to fifth embodiments can be expected. That is, as shown in FIG. 11C, the reinforcing pattern 90 can prevent the damage 30 due to dicing from being directly applied to the interface of the low_k film 14. It will be. As a result, the occurrence of interlayer film peeling is suppressed. Can be controlled. Therefore, not only at the time of assembling but also after the assembling process, it is possible to solve the problem that the wiring structure 21 inside the LSI chip 10 is disconnected due to the peeling of the interlayer film.
- the capturing pattern 90 is not limited to the case where it is constituted by one opening pattern (groove).
- a similar effect can be obtained when a plurality of opening patterns are used.
- the invention of the present application is not limited to the above (each) embodiment, and can be variously modified in an implementation stage without departing from the gist of the invention.
- the (each) embodiment includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent requirements. For example, even if some components are deleted from all the components shown in the embodiments, at least one of the problems described in the section of the problem to be solved by the invention is required. In other words, if the effects of the present invention can be solved and the effects (at least one of the effects) described in the section of the effects of the invention can be obtained, the configuration from which the constituent requirements have been deleted can be extracted as the invention.
- interlayer film peeling due to weak adhesion strength of 1 ow-k film and damage at the time of dicing can be suppressed, and LSI failure due to interlayer film peeling can be prevented.
- a possible semiconductor device is obtained.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2004-7019486A KR20040111717A (ko) | 2002-11-15 | 2003-11-14 | 반도체장치 |
EP03772778A EP1562227A4 (en) | 2002-11-15 | 2003-11-14 | SEMICONDUCTOR DEVICE |
US11/023,391 US20050110151A1 (en) | 2002-11-15 | 2004-12-29 | Semiconductor device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002332844A JP2004172169A (ja) | 2002-11-15 | 2002-11-15 | 半導体装置 |
JP2002-332844 | 2002-11-15 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/023,391 Continuation-In-Part US20050110151A1 (en) | 2002-11-15 | 2004-12-29 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2004047163A1 true WO2004047163A1 (ja) | 2004-06-03 |
Family
ID=32321677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2003/014513 WO2004047163A1 (ja) | 2002-11-15 | 2003-11-14 | 半導体装置 |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP1562227A4 (ja) |
JP (1) | JP2004172169A (ja) |
KR (1) | KR20040111717A (ja) |
CN (1) | CN1692481A (ja) |
TW (1) | TWI229370B (ja) |
WO (1) | WO2004047163A1 (ja) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005142351A (ja) * | 2003-11-06 | 2005-06-02 | Nec Electronics Corp | 半導体装置およびその製造方法 |
US7202563B2 (en) | 2004-03-25 | 2007-04-10 | Kabushiki Kaisha Toshiba | Semiconductor device package having a semiconductor element with resin |
JP4776195B2 (ja) | 2004-09-10 | 2011-09-21 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP4675147B2 (ja) * | 2005-05-10 | 2011-04-20 | パナソニック株式会社 | 半導体装置 |
JP4675159B2 (ja) * | 2005-05-26 | 2011-04-20 | パナソニック株式会社 | 半導体装置 |
JP2006351878A (ja) * | 2005-06-16 | 2006-12-28 | Matsushita Electric Ind Co Ltd | 半導体装置 |
JP4282646B2 (ja) | 2005-09-09 | 2009-06-24 | 株式会社東芝 | 半導体装置の製造方法 |
DE102005057076A1 (de) * | 2005-11-30 | 2007-05-31 | Advanced Micro Devices, Inc., Sunnyvale | Technik zum Verbessern der Haftung von Metallisierungsschichten durch Vorsehen von Platzhalterkontaktdurchführungen |
JP5262144B2 (ja) * | 2008-01-31 | 2013-08-14 | 日本電気株式会社 | 半導体デバイス及びその製造方法 |
US10461038B1 (en) * | 2018-08-31 | 2019-10-29 | Micron Technology, Inc. | Methods of alignment marking semiconductor wafers, and semiconductor packages having portions of alignment markings |
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TW303982U (en) * | 1996-06-28 | 1997-04-21 | Winbond Electronics Corp | Structure of chip guard ring using contact via |
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JP2001168093A (ja) * | 1999-12-09 | 2001-06-22 | Sharp Corp | 半導体装置 |
JP4118029B2 (ja) * | 2001-03-09 | 2008-07-16 | 富士通株式会社 | 半導体集積回路装置とその製造方法 |
-
2002
- 2002-11-15 JP JP2002332844A patent/JP2004172169A/ja not_active Abandoned
-
2003
- 2003-11-14 TW TW092131925A patent/TWI229370B/zh not_active IP Right Cessation
- 2003-11-14 EP EP03772778A patent/EP1562227A4/en not_active Withdrawn
- 2003-11-14 WO PCT/JP2003/014513 patent/WO2004047163A1/ja active Application Filing
- 2003-11-14 KR KR10-2004-7019486A patent/KR20040111717A/ko not_active Application Discontinuation
- 2003-11-14 CN CNA2003801005341A patent/CN1692481A/zh active Pending
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EP0605806A2 (en) * | 1992-12-29 | 1994-07-13 | International Business Machines Corporation | Process for producing crackstops on semiconductor devices and devices containing the crackstops |
JPH08172062A (ja) * | 1994-12-16 | 1996-07-02 | Oki Electric Ind Co Ltd | 半導体ウエハ及び半導体ウエハの製造方法 |
JPH08236522A (ja) * | 1995-02-27 | 1996-09-13 | Oki Electric Ind Co Ltd | 半導体チップ |
JPH0945766A (ja) * | 1995-07-28 | 1997-02-14 | Hitachi Ltd | 半導体集積回路装置およびその製造方法 |
JP2000150429A (ja) * | 1998-11-10 | 2000-05-30 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2000277465A (ja) * | 1999-03-26 | 2000-10-06 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2002289689A (ja) * | 2001-03-28 | 2002-10-04 | Fujitsu Ltd | 半導体集積回路装置とその製造方法 |
JP2002353307A (ja) * | 2001-05-25 | 2002-12-06 | Toshiba Corp | 半導体装置 |
JP2003338504A (ja) * | 2002-03-15 | 2003-11-28 | Fujitsu Ltd | 半導体装置及びその製造方法並びに位相シフトマスク |
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Also Published As
Publication number | Publication date |
---|---|
CN1692481A (zh) | 2005-11-02 |
JP2004172169A (ja) | 2004-06-17 |
EP1562227A1 (en) | 2005-08-10 |
TWI229370B (en) | 2005-03-11 |
TW200409188A (en) | 2004-06-01 |
KR20040111717A (ko) | 2004-12-31 |
EP1562227A4 (en) | 2009-04-22 |
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