WO2004017396A1 - 半導体基体上の絶縁膜を形成する方法 - Google Patents

半導体基体上の絶縁膜を形成する方法 Download PDF

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Publication number
WO2004017396A1
WO2004017396A1 PCT/JP2003/010357 JP0310357W WO2004017396A1 WO 2004017396 A1 WO2004017396 A1 WO 2004017396A1 JP 0310357 W JP0310357 W JP 0310357W WO 2004017396 A1 WO2004017396 A1 WO 2004017396A1
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WO
WIPO (PCT)
Prior art keywords
insulating film
film
plasma
semiconductor substrate
treatment
Prior art date
Application number
PCT/JP2003/010357
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
Toshiaki Hongoh
Original Assignee
Tokyo Electron Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited filed Critical Tokyo Electron Limited
Priority to JP2004528882A priority Critical patent/JPWO2004017396A1/ja
Priority to AU2003255034A priority patent/AU2003255034A1/en
Publication of WO2004017396A1 publication Critical patent/WO2004017396A1/ja

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/67Thin-film transistors [TFT]
    • H10D30/6758Thin-film transistors [TFT] characterised by the insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer

Definitions

  • the present invention relates to an insulating film of a semiconductor device, particularly a thin film transistor ( ⁇ ).
  • the present invention relates to the formation of a gate oxide film of TFT for LCD.
  • Insulating films are used in various semiconductor devices, and various methods such as oxidation or nitridation of semiconductor substrates, CVD (chemical vapor deposition), PVD (physical vapor deposition), and coating are used to form insulating films.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • coating are used to form insulating films.
  • Technology is used.
  • a modification treatment such as oxidation or nitridation by heat or plasma for modifying the underlying film is used.
  • a deposition process such as CVD is often used.
  • the film quality obtained by these treatments is different, for example, the surface order density of the insulating film obtained by such a modification treatment is relatively large, for example, about 5 ⁇ 10 1 Q e V— 1 cm— 2.
  • small and interface state density obtained Te cowpea deposition process Unaryo of CVD is example if by 5 XI 0 12 e V "relatively large as 1 ⁇ cm 2 or so. Also, provided by this good UNA modification treatment The fact that the film formation rate of the film is relatively low and the film formation rate of the film obtained by the deposition process is relatively high.
  • a plasma processing apparatus for the film may be used.
  • an object to be processed such as a semiconductor wafer or an LCD substrate is placed by passing a microwave of about 2.45 GHz through a slot electrode.
  • Microwaves convert these reactant gases into plasmas and radicals, which are highly active, and react with the workpiece to form a film.
  • a rare gas such as argon, which promotes plasma excitation, and a reactant gas are introduced into the processing chamber.
  • this reactant gas is, for example, oxygen and possibly hydrogen in an oxidation treatment of a semiconductor substrate called field oxidation, and in a CVD, tetraethyl orthosilicate (TEOS). And oxygen.
  • plasma CVD processing is generally performed to form a gate insulating film of a transistor.
  • a high temperature of about 100 ° C is required, but a plasma silicon oxide film is required. Can be grown at lower temperatures than the thermal oxidation method. Therefore, it is preferable for a device that dislikes high temperature, and has characteristics such that the growth rate is large, a compressive stress film can be easily obtained, the film is dense, and the oxidation rate does not depend on the surface orientation.
  • parameters representing the properties of an insulating film include a tundling bond represented by an interface state density, a dielectric strength voltage, a film density, a film forming speed, and the like.
  • Membrane Methods and apparatus are still needed.
  • the present invention provides a method for meeting the requirements regarding the parameters used in the evaluation of insulating films.
  • LCD TFT switches used amorphous silicon, and their gate oxide films were manufactured using a CVD process. However, it is considered that it is difficult to achieve the film quality required for the gate oxide film of the recently developed polysilicon and continuous grain silicon (CGS) TFT switches by CVD.
  • CGS continuous grain silicon
  • the film forming process proceeds by diffusing oxygen in the formed oxide film, so that the film forming speed becomes slower as the film thickness increases.
  • the present invention provides a method for obtaining an insulating film having a required film quality in a short time.
  • the present invention provides a method for manufacturing a semiconductor device, comprising: performing a modification process on a semiconductor substrate to form a first insulating film; and performing a deposition process for depositing a second insulating film on the first insulating film.
  • This is a method for forming an insulating film.
  • the insulating film on the semiconductor substrate is, in particular, a gate insulating film, more particularly, a TFT gate. Oxide film, and more particularly a TFT oxide film for a display such as an LCD.
  • the semiconductor substrate is a silicon substrate, such as a polysilicon substrate, a continuous grain boundary crystal silicon substrate or a single crystal silicon substrate.
  • both the first insulating film and the second insulating film are oxide films.
  • the first insulating film is an oxide film
  • the second insulating film is a nitride film
  • the thickness of the first insulating film is 10 to 100 A, particularly 10 to 30 °.
  • the thickness of the first insulating film may be a thickness sufficient to satisfy the requirement on the interface between the semiconductor substrate and the first insulating film, for example, the interface between the silicon substrate and the silicon oxide.
  • the thickness of the second insulating film is 100 to 2,000, particularly 500 to 1, 000. Further, the thickness of the second insulating film may be a thickness that satisfies the requirements regarding the dielectric strength voltage of the insulating film including the first insulating film and the second insulating film.
  • the interface state density between the first insulating film and the semiconductor substrate 1 0 12 e V -. 1 ⁇ cm less than 2, for example 1 0 12 ⁇ 1 0 10 e V "1 cm a 2 - L 0 9 e V ' !!!: 2, preferably less than 1 O ⁇ e V- 1 ⁇ cm 2, for example 1 0 10 ⁇ ..
  • the insulation withstand voltage of an insulation film on a semiconductor substrate including a first insulation film and a second insulation film has an insulation withstand voltage suitable for a desired application.
  • the voltage is more than 10 V, more than 20 V, or more than 30 V.
  • the modification treatment is a heat or plasma oxidation or nitridation treatment of the semiconductor substrate, and the deposition treatment is a CVD treatment.
  • This deposition process may be a PVD, coating.
  • the modification process is a plasma oxidation process
  • the deposition process is a plasma CVD process
  • the atmosphere of the plasma oxidation treatment contains a rare gas and oxygen.
  • the flow ratio of the rare gas to oxygen is 100: 3 or less.
  • the noble gas is, for example, krypton.
  • the plasma CVD processing atmosphere contains oxygen and a silicon-containing gas.
  • the Kei-containing gas for example, a monosilane SH 4.
  • the average film forming rate of the first insulating film is 10 to 100 AZ minutes, particularly 10 to 50 AZ minutes, and the average film forming rate of the second insulating film is Is from 100 to 100 A / min, especially from 500 to 1.0 OA / min.
  • the present invention also provides a method for forming an insulating film including a first insulating film and a second insulating film on a semiconductor substrate, the method comprising: forming an average film forming rate of the first insulating film adjacent to the semiconductor substrate. And the ratio of the deposition rate of the second insulating film adjacent to the first insulating film on the opposite side of the semiconductor substrate is 1: 1, 0 ⁇ 0 to 1: 1, particularly 1:10.
  • a method for producing a method for forming an insulating film including a first insulating film and a second insulating film on a semiconductor substrate, which is 0 to 1: 10 is provided by, for example, an inductively coupled plasma (ICP) generator, Or a microwave-excited plasma generator such as a slot emission type microwave-excited plasma generator, particularly a radial line slot antenna (RLSA) microwave-excited plasma generator.
  • ICP inductively coupled plasma
  • a microwave-excited plasma generator such as a slot emission type microwave-excited plasma generator, particularly a radial line slot antenna (RLSA) microwave-excited plasma generator.
  • the method can have any other features that can be understood from the description herein.
  • FIG. 1 is a diagram illustrating a process of forming an insulator film formed according to one embodiment of the present invention.
  • FIG. 2 is a schematic block diagram showing the structure of the RLSA microwave plasma processing apparatus used in one embodiment of the present invention.
  • FIG. 3 is a plan view of an antenna used in the RLSA microwave plasma processing apparatus of FIG.
  • FIG. 4 is a top view of a cluster tool using the plasma processing apparatus of FIG.
  • FIG. 5 is a diagram showing the time dependence of the film formation rate by direct oxidation of the silicon surface.
  • FIG. 6 is a diagram showing the deposition rate of the CVD oxide film.
  • Cluster tool 3 0 0 ... antenna 4 0 0... Cluster tool
  • FIG. 2 is a schematic block diagram of a radial line slot antenna (RLSA) plasma processing apparatus 200 capable of forming an insulating film of the present invention.
  • RLSA radial line slot antenna
  • the present invention will be described below with reference to an RLSA plasma processing apparatus, the insulating film of the present invention can be obtained by using any apparatus other than the plasma processing apparatus.
  • the present invention uses a plasma processing apparatus. This is because the plasma processing apparatus can achieve film formation at a relatively low temperature and achieve good film quality.
  • a microwave plasma apparatus such as an RLSA plasma processing apparatus capable of generating high-density plasma, an ICP (inductively coupled) plasma apparatus, an ECR plasma apparatus, or the like is used.
  • the microwave plasma processing apparatus 200 of the present embodiment includes a gate pulp 201 connected to a cluster tool 400 and a susceptor on which a workpiece W such as a semiconductor wafer substrate or an LCD substrate is placed.
  • the control system of the plasma processing apparatus 200 is not shown.
  • the processing chamber 202 has a side wall and a bottom made of a conductor such as aluminum.
  • the processing chamber 202 has, for example, a cylindrical shape, but the shape is arbitrary.
  • a susceptor 204 and a workpiece W are supported thereon.
  • the top plate 208 is a cylindrical plate-like body made of a dielectric material such as quartz-nitride aluminum that blocks the upper part of the processing chamber 202.
  • the antenna 300 has a plurality of slots 310 on a concentric circle.
  • the antenna 300 is made of, for example, a copper plate having a thickness of 1 mm or less, and is disposed on the upper surface of the top plate 208.
  • Each slot 310 is a substantially rectangular through hole, and adjacent slots are orthogonal to each other to form an alphabet “T” shape.
  • the arrangement, shape, and the like of the slot 310 are determined depending on the wavelength of the microphone mouth wave generated by the microwave generation source 210, the required plasma, and the like.
  • As the optional slow wave member 222 a predetermined material having a predetermined dielectric constant and a high thermal conductivity in order to shorten the wavelength of the microwave is selected.
  • the microwave source 210 is made of, for example, a magnetron, and can generate a microwave of 2.45 GHz (for example, 5 kW). The microwave then passes through the rectangular waveguide 2 11 1, the mode converter 2 12, and the circular coaxial waveguide 2 13 to reach the antenna member 300. In FIG. 2, devices such as an isolator that absorbs reflected microwaves returning to the magnetron are omitted.
  • the susceptor 204 can control the temperature of the processing object W in the processing chamber 202 as desired.
  • a temperature controller (not shown) controls the temperature of the susceptor 204.
  • the susceptor 204 can be configured to be able to move up and down in the processing chamber 202, and any technique known to those skilled in the art can be applied.
  • the gas supply pipes 240 and 270 are connected to a gas supply source, a pulp, a controller for a mashu opening, and the like (not shown).
  • the processing gas is directly supplied to the processing chamber 202, but it is also possible to supply the processing gas uniformly through a shower plate (not shown) at the upper part of the processing chamber 202. .
  • the inside of the processing chamber 202 can be maintained at a predetermined reduced pressure by the vacuum pump 206.
  • the vacuum pump 206 uniformly evacuates the processing chamber 202 to maintain a uniform plasma density and to prevent the processing density of the workpiece W from becoming uneven due to a partial concentration of the plasma density. .
  • the cluster tool 400 may be a cluster tool as shown in FIG.
  • the cluster tool 400 includes a processing system section 410 for performing processing such as film forming processing, diffusion processing, and etching processing on a wafer W as a substrate to be processed; And a transfer system unit 450 for loading and unloading wafers W from and to the wafer.
  • the processing system 410 is composed of a transfer chamber 4101, which can be evacuated, and four processing chambers 200A, connected via a pulp pulp 201A to 201D. In each of the champers 200 A to 200 D, the same type or different types of processing can be performed on the channel W. Further, a transfer arm 412 configured to be able to bend and extend and rotate freely is provided in the transfer chamber 411, and the processing chambers 200A to 200D and a load lock chamber to be described later are provided. Between 430 A and B and ⁇ ⁇ C W are to be delivered.
  • the transport system section 450 transports and transfers the wafer W to and from the cassette stage 480 for placing the carry cassette. And a transfer stage 470 for moving the transfer arm 471.
  • the cassette stage 480 is provided with a container mounting table 481, and a plurality of, in the illustrated example, up to four carrier cassettes 483 can be mounted thereon.
  • the carry cassette 483 can accommodate, for example, up to 25 wafers W at equal intervals in multiple stages.
  • the transfer stage 470 is provided with a guide rail 472 extending in the center thereof along the length direction, and the transfer arm 471 is slidably supported on the guide rail 472. Have been. At the other end of the transfer stage 470, an orienter 475 as a direction positioning device for positioning the wafer W is provided.
  • load lock chambers 430A and 430B which can be evacuated are provided.
  • FIG. 1 is a vertical cross-sectional view showing a process of manufacturing an insulator film according to one embodiment of the present invention.
  • a silicon substrate 101 is shown.
  • the silicon substrate 101 may be any silicon substrate, for example, a silicon wafer, amorphous silicon, low-temperature polysilicon, continuous grain boundary crystal silicon, or the like.
  • a first insulating film 102 shown in FIG. 1B is obtained.
  • This modification treatment may be any modification treatment such as thermal oxidation, thermal nitridation, thermal oxynitridation, plasma oxidation, plasma nitridation, and plasma oxynitridation. Therefore, the first insulating film 102 in FIG. 1B may be a so-called field oxide, nitride, or oxynitride film.
  • the processing conditions in this case include the following conditions for an 8-inch silicon wafer:
  • Processing temperature 100 to 500 ° C, for example, 250 ° C
  • Plasma source output 100 to 6, 00W, for example, 2000W
  • the second insulating film 103 in FIG. 1C is obtained.
  • This deposition process can be any modification process such as CVD, PVD, or coating.
  • the second insulating film 103 in FIG. 1 (c) may be a so-called deposition (deposited) oxide, nitride, oxynitride film, or polymer film.
  • argon gas is supplied from the processing gas supply paths 240 and 270 of the processing apparatus 100 in FIG. , yo Una rare gas krypton and subjected feeding the S i H 4 or TEOS by Unakei-containing gas. Although two supply paths are shown in FIG. 2, gas can be supplied from any number of supply paths.
  • the processing conditions in this case include the following conditions for an 8-inch silicon wafer:
  • Plasma source output 100 to 6,000 W, for example, 2,000 W
  • the insulating film of the present invention is formed.
  • a unique insulating film can be obtained by a combination of a modification treatment of a semiconductor substrate and a subsequent deposition treatment.
  • the method of the present invention can be obtained by adjusting properties relating to an interface obtained by a modification treatment of a semiconductor substrate and properties relating to a park obtained by a subsequent deposition treatment.
  • both the modification treatment and the deposition treatment are treatments using plasma.
  • the film quality obtained as described above is generally preferable.
  • both the denaturation process and the deposition process are plasma processes, these processes can be performed in the same apparatus.
  • the advantages of the good interface characteristics obtained by the modification treatment of the semiconductor substrate and the advantages of the rapid film formation obtained by the deposition treatment are compatible. That is, for example, the advantage of good interface characteristics obtained by the plasma oxidation treatment of the semiconductor substrate and the advantage of the high film forming rate obtained by the plasma CVD treatment are both compatible.
  • the insulating film obtained by the method of the present invention as a whole has an insulation withstand voltage that can be used for a gate insulating film such as a TFT gut insulating film for LCD.
  • a rare gas and oxygen-containing atmosphere is used in the plasma oxidation treatment, and the flow ratio of the rare gas and oxygen is set to 100: 3 or less, which is particularly suitable for TFTs of displays such as liquid crystal displays.
  • make a thick silicon oxide film Still another aspect of the present invention is a method for forming an insulating film including a first insulating film and a second insulating film on a semiconductor substrate, wherein the average film forming of the first insulating film adjacent to the semiconductor substrate is performed.
  • a ratio between the speed and an average deposition rate of the second insulating film adjacent to the first insulating film on the opposite side of the semiconductor substrate is 1: 1, 0000 to 1: 1;
  • This is a method of forming an insulating film including a film and a second insulating film on a semiconductor substrate.
  • the quality of the film to be formed and the film forming speed are problematic, but by changing the film forming speed of the interface portion and the parc portion, the film quality can be adjusted and improved. It is possible to obtain a film forming rate.
  • the method of the present invention is not limited to a silicon substrate, and can be applied to any other semiconductor substrate to which similar processing can be applied.
  • the insulating film of the present invention is formed using a plasma processing apparatus connected to a cluster apparatus.
  • the present invention can be performed by an arbitrary apparatus, for example, a so-called flow process currently being studied. I think it can be applied to In this case, the rapid formation of the insulating film of the present invention is considered to provide a great benefit.
  • Plasma source output 200 W
  • the deposition rate is about 20 AZ when forming a 2OA oxide film, about 12 A / min when forming a 25 A oxide film, and a 27 A oxide film is formed. It is about 9 A / min.
  • the deposition rate decreases as the thickness of the formed oxide film increases. This is thought to be because oxygen atoms must diffuse the already formed oxide film in order to form the oxide film. Therefore, it is not practical to make a relatively thick insulating film, for example, a gate insulating film of LCD, only by direct oxidation of the silicon surface, because it takes a long time.
  • Plasma source output 2,000W
  • the deposition rate of the CVD oxide film has reached from 1,000 A / min to 4,500 A / min.
  • This film formation rate is clearly higher than the oxide film formation rate by direct oxidation of the silicon surface.
  • a relatively thick oxide film such as an LCD gate insulating film can be used for a practical time. To make with enable.
  • the method of manufacturing an insulating film of the present invention can be applied to an insulating film of a semiconductor device, particularly a gate insulating film,
  • the present invention provides a method for obtaining an insulating film having a desired film quality (preferably in a short time).

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Thin Film Transistor (AREA)
PCT/JP2003/010357 2002-08-14 2003-08-14 半導体基体上の絶縁膜を形成する方法 WO2004017396A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004528882A JPWO2004017396A1 (ja) 2002-08-14 2003-08-14 半導体基体上の絶縁膜を形成する方法
AU2003255034A AU2003255034A1 (en) 2002-08-14 2003-08-14 Method of forming insulation film on semiconductor substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002236343 2002-08-14
JP2002-236343 2002-08-14

Publications (1)

Publication Number Publication Date
WO2004017396A1 true WO2004017396A1 (ja) 2004-02-26

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JP (1) JPWO2004017396A1 (zh)
KR (1) KR100729989B1 (zh)
CN (1) CN100380610C (zh)
AU (1) AU2003255034A1 (zh)
WO (1) WO2004017396A1 (zh)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005268798A (ja) * 2004-03-15 2005-09-29 Sharp Corp 酸化物薄膜を製造する方法
JP2006332619A (ja) * 2005-04-28 2006-12-07 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US7410839B2 (en) 2005-04-28 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and manufacturing method thereof
US7465677B2 (en) 2005-04-28 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US7608490B2 (en) 2005-06-02 2009-10-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7785947B2 (en) 2005-04-28 2010-08-31 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device comprising the step of forming nitride/oxide by high-density plasma
US7838347B2 (en) 2005-08-12 2010-11-23 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method of display device
US7855153B2 (en) 2008-02-08 2010-12-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8318554B2 (en) 2005-04-28 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of forming gate insulating film for thin film transistors using plasma oxidation
US8343816B2 (en) 2005-04-25 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Organic transistor, manufacturing method of semiconductor device and organic transistor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008041600A1 (fr) * 2006-09-29 2008-04-10 Tokyo Electron Limited Procédé d'oxydation par plasma, appareil de traitement au plasma et support de stockage
US10312600B2 (en) * 2016-05-20 2019-06-04 Kymeta Corporation Free space segment tester (FSST)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0422127A (ja) * 1990-05-17 1992-01-27 Matsushita Electric Ind Co Ltd 薄膜トランジスタの製造方法
JPH0443642A (ja) * 1990-06-11 1992-02-13 G T C:Kk ゲート絶縁膜の形成方法
WO2001008208A1 (fr) * 1999-07-26 2001-02-01 Tadahiro Ohmi Dispositif a semi-conducteur, procede permettant de former une couche d'oxyde de silicium et appareil permettant de former une couche d'oxyde de silicium

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0422127A (ja) * 1990-05-17 1992-01-27 Matsushita Electric Ind Co Ltd 薄膜トランジスタの製造方法
JPH0443642A (ja) * 1990-06-11 1992-02-13 G T C:Kk ゲート絶縁膜の形成方法
WO2001008208A1 (fr) * 1999-07-26 2001-02-01 Tadahiro Ohmi Dispositif a semi-conducteur, procede permettant de former une couche d'oxyde de silicium et appareil permettant de former une couche d'oxyde de silicium

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4703224B2 (ja) * 2004-03-15 2011-06-15 シャープ株式会社 酸化物薄膜を製造する方法
JP2005268798A (ja) * 2004-03-15 2005-09-29 Sharp Corp 酸化物薄膜を製造する方法
US8785259B2 (en) 2005-04-25 2014-07-22 Semiconductor Energy Laboratory Co., Ltd. Organic transistor, manufacturing method of semiconductor device and organic transistor
US8343816B2 (en) 2005-04-25 2013-01-01 Semiconductor Energy Laboratory Co., Ltd. Organic transistor, manufacturing method of semiconductor device and organic transistor
US7465677B2 (en) 2005-04-28 2008-12-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US7718547B2 (en) 2005-04-28 2010-05-18 Semiconductor Energy Laboratory Co., Ltd Semiconductor device and method for manufacturing the same
US7785947B2 (en) 2005-04-28 2010-08-31 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device comprising the step of forming nitride/oxide by high-density plasma
US8318554B2 (en) 2005-04-28 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method of forming gate insulating film for thin film transistors using plasma oxidation
US7410839B2 (en) 2005-04-28 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Thin film transistor and manufacturing method thereof
JP2006332619A (ja) * 2005-04-28 2006-12-07 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US7608490B2 (en) 2005-06-02 2009-10-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7838347B2 (en) 2005-08-12 2010-11-23 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method of display device
US8674366B2 (en) 2005-08-12 2014-03-18 Semiconductor Energy Laboratory Co., Ltd. Display device and manufacturing method of display device
US7855153B2 (en) 2008-02-08 2010-12-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US8324699B2 (en) 2008-02-08 2012-12-04 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device

Also Published As

Publication number Publication date
KR20050035883A (ko) 2005-04-19
CN1682357A (zh) 2005-10-12
AU2003255034A1 (en) 2004-03-03
JPWO2004017396A1 (ja) 2005-12-08
KR100729989B1 (ko) 2007-06-20
CN100380610C (zh) 2008-04-09

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