WO2004010507A1 - Procede de production d'une structure de grille en t et transistor a effet de champ correspondant - Google Patents

Procede de production d'une structure de grille en t et transistor a effet de champ correspondant Download PDF

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Publication number
WO2004010507A1
WO2004010507A1 PCT/DE2003/002350 DE0302350W WO2004010507A1 WO 2004010507 A1 WO2004010507 A1 WO 2004010507A1 DE 0302350 W DE0302350 W DE 0302350W WO 2004010507 A1 WO2004010507 A1 WO 2004010507A1
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Prior art keywords
gate
layer
spacer
sacrificial
highly conductive
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PCT/DE2003/002350
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German (de)
English (en)
Inventor
Hans-Joachim Barth
Helmut Tews
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Infineon Technologies Ag
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Publication of WO2004010507A1 publication Critical patent/WO2004010507A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Definitions

  • the present invention relates to a method for producing a T-gate structure and an associated field-effect transistor, and in particular to a method for producing a self-adjusting T-gate structure and an associated field-effect transistor in a sub-100 nanometer range.
  • a type of transistor that is widely used in such semiconductor circuits is the so-called field-effect transistor, in which a current between a source region and a drain region is driven via a so-called control electrode or gate.
  • this type of transistor is, however, largely determined by its size, with significant problems occurring in particular for structure sizes below 100 nanometers.
  • the electrical resistance of the control layer or of the gate and a gate capacitance are to be mentioned for field effect transistors.
  • the structure sizes that shrink as miniaturization progresses lead to increased gate capacitances and increased gate resistances, which reduce the electrical properties such as e.g. affect speed and power consumption of the circuit.
  • the gate resistance becomes larger due to the shortening gate lengths or channel lengths, which in particular limits the clock rates.
  • a so-called T-gate structure was therefore introduced, in which the control layer or the gate has a T-shape. With this T-shape, the desired short channel lengths can still be achieved in the lower area, while the widening in the upper area enables sufficiently small gate resistances.
  • a wide but shallow first trench is usually first formed in a dielectric material and then a narrow but deep second trench is then formed in the first trench and filled with a conductive semiconductor material, so that the desired T-gate Maintains structure.
  • a wide but shallow first trench is usually first formed in a dielectric material and then a narrow but deep second trench is then formed in the first trench and filled with a conductive semiconductor material, so that the desired T-gate Maintains structure.
  • such conventional methods for producing T-gate structures are difficult to produce, in particular for structure widths below 100 nanometers.
  • the required low gate resistances can no longer be realized with the polysilicon that is usually used as filler material.
  • the invention is therefore based on the object of creating a method for producing a T-gate structure and an associated field-effect transistor which is also suitable for sub-100 * nanometer structures.
  • T-gate structures can be produced in a self-adjusting manner and with a very low resistance in a simple manner even for very small dimensions.
  • a victim gate and a cover layer are preferably formed and structured as a victim gate stack, which is why adequate removal of the upper edge of the victim gate and thus of the later gate is obtained after removal of the cover layer.
  • the first spacer using the first etching stop layer and to widen the gate recess in the upper region of the remaining victim gate can be formed particularly easily.
  • the sacrificial gate can preferably be completely removed, a gate dielectric formed, a gate layer formed on the gate dielectric and the gate layer in the upper region subsequently removed again, thereby making it possible to produce very high quality and one each semiconductor material can produce adapted control layers.
  • the sacrificial gate may already have a gate dielectric on the surface of the semiconductor substrate and may otherwise consist of an electrically conductive gate material such as polysilicon, only an upper region of the sacrificial gate being removed.
  • a so-called damascene process can preferably be carried out for filling the widened gate cutout, a diffusion barrier layer and / or a seed or top layer to avoid undesired diffusion of dopants and to improve one
  • copper is preferably deposited and planarized as a highly conductive material, a further protective layer being formed to prevent undesired dopants from diffusing out.
  • so-called doped metal can also be deposited and planarized as a highly conductive material (e.g. Culn, CuAl, CuMg, CuSn, CuAg, CuZr), after which the diffusion barrier layer is formed on the surface in a self-adjusting manner by thermal treatment by outdiffusion of the dopants.
  • a highly conductive material e.g. Culn, CuAl, CuMg, CuSn, CuAg, CuZr
  • a further thermal treatment for generating grain growth in the highly conductive material can be carried out, whereby in particular conductivity can be further improved and the electromigration properties can be improved.
  • the sacrificial gate stack remaining in the lower part of the T-gate structure can also be completely removed and one before filling with the highly conductive material
  • Gate metal layer are formed, whereby the electrical properties of a field effect transistor to be formed can be further improved.
  • a necessary adaptation of a work function of the gate metal layer to a respective doping of the semiconductor substrate can be adapted by means of a nitrogen implantation.
  • one or more implantations for forming connection regions and / or source / drain regions can be carried out in the semiconductor substrate when the sidewall insulation structure is formed, as a result of which these regions can be produced particularly simply and in a self-adjusting manner.
  • highly conductive connection regions for the source / drain regions can in turn be formed in a self-adjusting manner by means of a silicide method, which is why this method is particularly suitable for field-effect transistors in the sub-100 nanometer range.
  • FIGS. 1A to 1H simplified sectional views to illustrate essential method steps according to a first exemplary embodiment
  • FIG. 2 shows a simplified sectional view to illustrate an essential method step according to a second exemplary embodiment
  • FIGS. 3A to 3C simplified sectional views to illustrate essential method steps according to a third embodiment.
  • FIGS 1A to 1H show simplified sectional views to illustrate essential manufacturing steps T-gate structure, as is preferably used in field-effect transistors in a sub-100 nanometer range.
  • the T-gate structure can also be used for other semiconductor components, such as, for example, non-volatile semiconductor memory elements.
  • a pad oxide and pad nitride for example, which are not shown, are first deposited in a standard process on a semiconductor substrate 1 (for example monocrystalline Si), and a flat trench isolation STI (shallow trench isolation) is formed in order to form active regions in the semiconductor substrate 1 , Trough implantations (not shown) can then also be carried out and a sacrificial oxide layer (sacrificial oxide) (not shown) can be formed on the surface of the semiconductor substrate 1.
  • a semiconductor substrate 1 for example monocrystalline Si
  • STI shallow trench isolation
  • a sacrificial gate layer 2 is deposited over the entire surface, preferably amorphous or polycrystalline semiconductor material such as e.g. Silicon is deposited.
  • a hard mask layer 3 is formed as a cover layer on the surface of the sacrificial gate layer 2, a TEOS hard mask being deposited, for example.
  • the cover layer 3 is structured using a conventional photolithographic method and the sacrificial gate layer 2 is structured using the structured cover layer 3, preferably selectively with respect to the oxide layer present on the semiconductor substrate surface.
  • the covering layer 3 should initially remain on the sacrificial gate layer 2 and should not be removed, as a result of which improved insulation properties result at a later point in time.
  • a side wall insulation layer 4 of, for example, 3 to 6 Nanometers of thermal oxide are obtained from the sacrificial gate stack shown in FIG. 1A.
  • Sidewall isolation structures are then formed on the sidewalls of the sacrificial gate stack.
  • a conventional spacer method e.g. a silicon nitride layer is deposited over the entire surface and then anisotropically etched, as a result of which the first spacers 5S and first residual layers 5 shown in FIG. 1a are obtained on the flanks of the trench insulation STI. Due to the remaining cover layer 3, the first spacer 5S extends to the upper edge of the hard mask or cover layer 3, which is why sufficient insulation to neighboring elements such as e.g. Receives contact connections.
  • Reactive ion etching (RIE) for example, is used as an anisotropic etching process.
  • a first implantation II can be carried out, as a result of which connection regions LDD for a respective channel region are formed in a self-adjusting manner in the semiconductor substrate.
  • an etching stop layer in the form of a thin oxide can optionally also be formed on the side flanks of the first spacer 5S.
  • an approximately 2 nanometer thick CVD silicon dioxide layer is deposited or this etch stop layer is thermally realized, for example, by converting part of the Si 3 N layer by means of an oxidation process.
  • the sacrificial gate stack is preferably formed sublithographically and can accordingly have a width of typically 30 to 50 nanometers.
  • the height of the sacrificial gate layer 2 is, for example, 100 to 200 nanometers and the thickness of the first spacers 5S is 10 to 20 nanometers. Of course, other dimensions can also be set depending on a particular application and the materials used.
  • a second spacer 6S is again formed analogously to the first spacer 5S by means of a conventional spacer method, a second silicon nitride layer being deposited and anisotropically etched, for example.
  • the thickness of this second spacer 6S is, for example, 50 to 70 nanometers, while its height in turn preferably extends to the upper edge of the hard mask or cover layer 3 and thereby improves insulation in this area.
  • a second implantation I 2 can be carried out using the first and second spacers 5S and 6S and the sacrificial gate stack, as a result of which the actual source / drain regions S, D are formed in the semiconductor substrate. Again, a self-adjusting process is obtained which is particularly suitable for very small structures.
  • highly conductive connection regions 7 for the source / drain regions S and D can already be formed at this point in time, for example by means of a self-adjusting silicide method (salicide process).
  • silicide process for example, siliconizable material or a siliconizable metal layer such as cobalt, nickel or platinum is first deposited over the entire surface. A conversion of the crystalline surface layer of the semiconductor substrate 1 is then carried out using the siliconizable material to form highly conductive connection regions 7, no silicon being present on the surfaces not in contact with semiconductor material (silicon).
  • connection regions 7 When using cobalt, nickel, titanium or platinum, 7 cobalt, nickel, titanium or platinum silicide layers are obtained as highly conductive connection regions, which can be designed to be self-adjusting.
  • the above-described formation of the connection regions 7 can, however, also be carried out at a later point in time, for example after the field effect transistor has been completed and contact openings have been formed.
  • Protective layer 8 formed and planarized together with the side wall insulation structure or the two spacers 5S and 6S up to the sacrificial gate layer 2. More specifically, for example, an HDP oxide layer (high density plasma), a BPSG layer (boron-phosphorus silicate glass) or a TEOS layer is deposited over the entire surface and planarized using a CMP process (Chemical Mechanical Polishing), the polysilicon being the stop layer Victim gate layer 2 is used.
  • CMP process Chemical Mechanical Polishing
  • a special gate replacement process can subsequently be carried out, at least an upper region I of the remaining sacrificial gate stack being removed in order to form a gate recess A.
  • the sacrificial gate layer 2 is first completely removed with a wet-chemical polysilicon etching and then with an oxide etching that is The sacrificial oxide layer formed on the conductor substrate surface and the side wall insulation layer 4 remaining on the side walls or the first spacer 5S are completely removed.
  • a gate dielectric 9 is then formed at least in the bottom region of the recess or on the exposed surface of the semiconductor substrate 1, silicon oxide, silicon nitride, oxynitride or a so-called high-k dielectric being deposited, for example.
  • Such gate dielectrics have a sufficiently high dielectric constant and can consequently implement a sufficiently high gate capacitance.
  • the gate recess A is then filled with the actual gate layer 10, it being possible, for example, to use undoped polysilicon.
  • a gate implantation (not shown) can be carried out for doping the gate layer 10 or for realizing sufficient conductivity of the gate layer 10.
  • in-situ doped materials such as e.g. Polysilicon or poly-SiGe can be used for NFET and PFET or gate metal layers with suitable work functions.
  • the insulation layer 8 is removed, e.g. by means of a wet chemical etching process. Then the desired metal layer, e.g. Co, Ni, Ti, or Pt deposited and silicided. Then the insulation layer 8 is applied again and planarized.
  • the introduced gate layer 10 in the upper region I is removed again, a so-called CDE process (Chemical Dry Etching) being carried out, for example, to a depth of 50 nanometers above the gate dielectric 9.
  • CDE process Chemical Dry Etching
  • the side wall insulation structure or the first spacer 5S which is exposed in the upper region I is now removed to form a widened gate recess AA.
  • This removal can take place either after a period of time or up to the optionally inserted etching stop layer.
  • the thin oxide layer formed between the first spacer 5S and the second spacer 6S serves as an etching stop layer.
  • a broadening of the gate stack in its upper region I is thus achieved by 20 nanometers, which represents a substantial broadening of the gate, particularly for structure sizes below 100 nanometers.
  • the gate in its upper region I is thus widened by 50% or more.
  • first spacer 5S and the second spacer 6S were formed at a time when the sacrificial gate stack with its sacrificial gate consisting of the side wall oxide layer 4 and the sacrificial gate layer 2 still had the covering layer 3, it is ensured that a sufficiently thick insulation layer or nitride layer extends from the second spacer 6S to the upper edge of the widened gate recess AA.
  • This insulation layer or the second spacer 6S thus prevents a possible short circuit in a later process step for realizing contact holes for gate and source / drain regions.
  • the desired material for the upper region I of the gate can be formed at this point in the further process control.
  • This can be polysilicon, for example, but an improved process control at this point uses highly conductive material 12 such as Cu.
  • a so-called Damascene process is referred to at this point, as it is used, for example, by T. Matsuki et. al. "Cu / Poly Si Damascene gate structured MOSFET with Ta and TaN stacked barrier", IEDM 1999, pages 261 to 264.
  • a layer 11 for example TiN, Ta, TaN, TaC, WN, WC, WCN
  • a layer 11 can first be formed in the widened gate recess AA, which on the one hand is an undesirable layer as a diffusion barrier layer and / or as a seed or growth layer Diffusion of disruptive impurities from the highly conductive material 12 is prevented and, on the other hand, improved growth in the very narrow trench is made possible.
  • Cu or Al, W, Ag, Au
  • a so-called cap layer 13 and a relatively thick insulation layer 14 are formed over the entire area in order to implement a further protective layer.
  • the cap layer 13 in turn serves as a diffusion barrier layer to prevent out-diffusion of, for example, Cu atoms and consists, for example, of silicon nitride, SiC or SiCN.
  • BPSG, TEOS or a low-k material with a low dielectric constant, for example, is used as the insulation layer 14 for the contact hole level.
  • contact holes V are formed at the locations of the source / drain regions and the gate.
  • FIG. 2 shows a simplified sectional view of a final manufacturing step according to a second exemplary embodiment, the same reference numerals representing the same or corresponding layers or elements and a repeated description being omitted below.
  • a selective deposition of a metal can also be carried out as a metallic diffusion barrier.
  • Such metals are essentially CoP, CoWP, (electrolessly deposited) CoWB, or (CVD-deposited) W or WN.
  • a further diffusion barrier layer 130 formed thereby is only on the highly conductive material 12 and not on the protective layer 8.
  • AA-doped metal layers and in particular doped Cu layers such as CuAl, CuMg, Culn, CuSn, CuZr etc. are used as the material for filling the widened gate recess, the deposition of such a cap layer is not necessary, since these layers after a Thermal treatment at a temperature less than 400 degrees Celsius diffuse the dopants to the surface and produce a self-passivating layer as a further diffusion barrier layer 130.
  • a further thermal annealing can also be carried out locally or globally in an oven process, grain growth in the highly conductive material 12 being optimized and a number of grain boundaries being minimized becomes. In addition to the improved conductivity, this also significantly improves the electromigration properties of the control layer.
  • a T-gate structure is thus produced using a special gate replacement process without performing an additional critical lithography step, both the gate resistance being reduced and gate capacitances being improved. Particularly when using highly conductive materials such as Cu, particularly low gate resistances are obtained.
  • the T-gate structure with improved conductivity can also be carried out without a complete replacement gate process, in which case the sacrificial gate is already a gate dielectric and an electrically conductive gate material and only an upper area of the victim gate is removed. In such an embodiment, the production can be significantly simplified at the expense of the electrical properties.
  • FIGS. 3A to 3C in turn show simplified sectional views to illustrate essential manufacturing steps in accordance with a third exemplary embodiment, the same reference symbols describing the same or corresponding layers as in exemplary embodiments 1 and 2, and a detailed description is therefore not given below.
  • the sacrificial gate stack or the sacrificial gate consisting of the gate layer 2 and the side wall insulation layer 4, is again completely removed, as a result of which improved electrical properties are obtained for a respective field effect transistor.
  • the manufacturing steps according to FIGS. 1A to 1D are first carried out in the same way as in the first exemplary embodiment, but now after the planarization according to FIG. 1D, the method step according to FIG. 3A is carried out.
  • the sacrificial gate layer 2 is not removed completely, ie as far as the semiconductor substrate 1, but rather only in the upper region I and then using this recess A to form the first spacers 5S in the same way as in the first exemplary embodiment according to FIG. 1F the widened gate Cutout AA removed.
  • the description in the first exemplary embodiment at this point is therefore made to the description in the first exemplary embodiment at this point.
  • the sacrificial gate for exposing the semiconductor substrate 1 is completely removed and the actual gate dielectric 9 is formed at least on the exposed semiconductor substrate 1.
  • thermal oxidation of the semiconductor substrate 1 is preferably carried out or a high-k material is deposited.
  • the materials here correspond to the materials for the gate dielectric 9 described above.
  • a so-called gate metal layer 100 is formed over the entire surface, for example Ta or TaN being deposited.
  • this gate metal layer 100 acts both as a diffusion barrier layer and as an adapted metal gate, as a result of which the electrical properties of a respective field effect transistor can be significantly improved.
  • the gate metal layer 100 is deposited, for example, using a CVD process (Chemical Vapor Deposition) or a PVD sputtering process (Physical Vapor Deposition), a so-called precursor for Ta being used in the case of the CVD process.
  • the growth or deposition takes place, for example, in an NH 3 atmosphere.
  • the PVD method either a TaN target is used, or Ta is sputtered, which then reacts to TaN.
  • a nitrogen implantation I N can optionally be carried out, for example.
  • the effects of such an The fit of the work functions of the gate metal layer 100 will be briefly explained later using the associated banding schemes.
  • the widened gate recess AA is again filled with highly conductive material 12 such as Cu and planarized by means of a CMP method.
  • a cap layer acting as a diffusion barrier layer 130 can be formed in the same way as in the exemplary embodiments described above.
  • a thick oxide layer can again be formed as an insulation layer for the contact hole level and the contact holes can be realized in the same way as in FIG. 1H.
  • the use of the gate metal layer 100 and the filling of the lower region II with highly conductive material also results in much faster cycle times with simultaneously reduced voltages and a reduced space requirement.
  • This exemplary embodiment is therefore particularly suitable for sub-100 nanometer field-effect transistors.
  • the invention has been described above using a silicon semiconductor substrate and correspondingly adapted materials. However, it is not limited to this and likewise includes alternative materials with corresponding effects. In the same way, the invention is not restricted to field-effect transistors with a T-gate structure, but rather also includes other semiconductor components with such T-gate structures.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un procédé permettant de produire une structure de grille en T, ainsi qu'un transistor à effet de champ correspondant. Une structure isolante de paroi latérale (5S, 6S) est formée au niveau des parois latérales d'un empilement de grilles sacrificielles (2, 3, 4). Au moins une zone supérieure (I) de l'empilement de grilles sacrificielles est enlevée pour former un dégagement de grille. Pour finir, une partie (5S) de la structure isolante de paroi latérale est enlevée dans la zone supérieure (I) et un dégagement de grille ainsi élargi est rempli avec un matériau (12) très conducteur.
PCT/DE2003/002350 2002-07-15 2003-07-11 Procede de production d'une structure de grille en t et transistor a effet de champ correspondant WO2004010507A1 (fr)

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DE2002131965 DE10231965B4 (de) 2002-07-15 2002-07-15 Verfahren zur Herstellung einer T-Gate-Struktur sowie eines zugehörigen Feldeffekttransistors
DE10231965.0 2002-07-15

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Cited By (5)

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DE102004020935B3 (de) * 2004-04-28 2005-09-01 Infineon Technologies Ag Verfahren zum Herstellen einer ersten Kontaktlochebene in einem Speicherbaustein
DE102004031741A1 (de) * 2004-06-30 2006-01-26 Infineon Technologies Ag Verfahren zur Herstellung von Feldeffekttransistorstrukturen mit Gateelektroden mit einer Metalllage
WO2009012536A1 (fr) * 2007-07-20 2009-01-29 Interuniversitair Microelektronica Centrum Contacts damasquinés sur des dispositifs cmos iii-v
DE102010030756A1 (de) * 2010-06-30 2012-01-05 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Austauschgateverfahren für Metallgatestapel mit großem ε auf der Grundlage eines nicht-konformen Zwischenschichtdielektrikums
CN114121667A (zh) * 2021-11-10 2022-03-01 上海华力集成电路制造有限公司 半导体器件的制造方法

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DE102004020935B3 (de) * 2004-04-28 2005-09-01 Infineon Technologies Ag Verfahren zum Herstellen einer ersten Kontaktlochebene in einem Speicherbaustein
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US7265007B2 (en) 2004-06-30 2007-09-04 Infineon Technologies Ag Method for fabricating field-effect transistor structures with gate electrodes with a metal layer
US7615807B2 (en) 2004-06-30 2009-11-10 Infineon Technologies Ag Field-effect transistor structures with gate electrodes with a metal layer
DE102004031741B4 (de) * 2004-06-30 2010-04-01 Qimonda Ag Verfahren zur Herstellung einer Kontaktanordnung für Feldeffekttransistorstrukturen mit Gateelektroden mit einer Metalllage und Verwendung des Verfahrens zur Herstellung von Feldeffekttransistoranordnungen in einem Zellenfeld
WO2009012536A1 (fr) * 2007-07-20 2009-01-29 Interuniversitair Microelektronica Centrum Contacts damasquinés sur des dispositifs cmos iii-v
US8492261B2 (en) 2007-07-20 2013-07-23 Imec Damascene contacts on III-V CMOS devices
DE102010030756A1 (de) * 2010-06-30 2012-01-05 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Austauschgateverfahren für Metallgatestapel mit großem ε auf der Grundlage eines nicht-konformen Zwischenschichtdielektrikums
DE102010030756B4 (de) * 2010-06-30 2013-06-06 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Austauschgateverfahren für Metallgatestapel mit großem ε auf der Grundlage eines nicht-konformen Zwischenschichtdielektrikums
CN114121667A (zh) * 2021-11-10 2022-03-01 上海华力集成电路制造有限公司 半导体器件的制造方法
CN114121667B (zh) * 2021-11-10 2024-04-30 上海华力集成电路制造有限公司 半导体器件的制造方法

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