WO2003100852A1 - Fil metallique de blindage dans une carte multicouches, puce a semi-conducteurs, element de circuit electronique et procede de production de ce fil - Google Patents

Fil metallique de blindage dans une carte multicouches, puce a semi-conducteurs, element de circuit electronique et procede de production de ce fil Download PDF

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Publication number
WO2003100852A1
WO2003100852A1 PCT/JP2003/006647 JP0306647W WO03100852A1 WO 2003100852 A1 WO2003100852 A1 WO 2003100852A1 JP 0306647 W JP0306647 W JP 0306647W WO 03100852 A1 WO03100852 A1 WO 03100852A1
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WO
WIPO (PCT)
Prior art keywords
multilayer substrate
conductor
coil
forming
parallel
Prior art date
Application number
PCT/JP2003/006647
Other languages
English (en)
Japanese (ja)
Inventor
Kouichirou Sagawa
Masahiko Oshimura
Original Assignee
Ajinomoto Co.,Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ajinomoto Co.,Inc. filed Critical Ajinomoto Co.,Inc.
Priority to AU2003241819A priority Critical patent/AU2003241819A1/en
Publication of WO2003100852A1 publication Critical patent/WO2003100852A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H01F27/363—Electric or magnetic shields or screens made of electrically conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors

Definitions

  • the present invention relates to a shield line, and more particularly, to a shield line formed in a multilayer substrate, and an electronic circuit element and a semiconductor chip on which the multilayer substrate is laminated.
  • the optimal arrangement of the elements is basically a matter of trial and error and is very inefficient.
  • the shield it is also practiced to cover the entire device or element with a copper plate or a paste made of copper as a main component.
  • a method of covering the entire device has no effect on the noise generated inside the device, and the method of covering the elements has many problems such as difficulty in high-density mounting.
  • the above-mentioned external shield cannot cope with it.
  • a coaxial cable-like structure described later that is, a GND with a large area, ideally an infinite area above and below a strip line used for signal transmission on the inner layer of the board Structures sandwiched between surfaces have been widely used.
  • this structure requires a large area for use in recent small-sized devices, and has many disadvantages.
  • a plurality of multilayer coils having a circuit surface in a direction perpendicular to the plane of the substrate and a method of manufacturing the same are disclosed in, for example, Japanese Patent Application Laid-Open No. H11-251146, which is suitable as a chip inductor.
  • a coil is formed in a direction perpendicular to the plane of the substrate in order to reduce the influence of external electromagnetic noise on the signal line wired in a plane parallel to the X direction.
  • a structure in which another circuit passes through the inside of the coil are disclosed in, for example, Japanese Patent Application Laid-Open No. H11-251146, which is suitable as a chip inductor.
  • Japanese Patent Application Laid-Open No. H11-1-26462 discloses a method for forming multiple solenoid coils around a semiconductor substrate for use in ICs. This method is an invention for obtaining a larger inductance, but it is also effective for avoiding noise of its internal elements. However, in this method, a very large volume has to be used for the coil portion, which is very problematic in terms of miniaturization. Further, as in the case of the chip induction, there is no mention of a structure in which another circuit passes through the inside of the coil.
  • Such include coaxial cables in addition to the stripline described above.
  • the signal line connected from the TV antenna to the receiver is covered with copper to reduce the effects of external noise.
  • Coaxial cables unlike strip lines, do not require a large area GND surface. Therefore, it has a structure similar to such a coaxial cable If shield lines can be formed in a multilayer board (printed circuit board), it would be possible to achieve both effective noise shielding and miniaturization.
  • a semiconductor chip (ic) and an electronic circuit element using such a small shielded line for a signal line can be produced. It is thought that it is possible.
  • a small shielded wire that uses a coil-shaped conductor, a cage-shaped conductor, or a conductor strip as the outer conductor of the shielded wire can be considered. I didn't.
  • An object of the present invention is to provide a shielded wire in a multilayer substrate which can save important signal lines in a high-frequency region from electromagnetic waves in a small space, and a method of manufacturing the same.
  • the invention according to claim 1 is a coil formed integrally with the multilayer substrate, wherein the coil includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. And a conductive wire formed integrally with the multilayer substrate, wherein the conductive wire is formed inside the coil.
  • the invention according to claim 2 is characterized in that the unit winding of the coil has a spiral pattern that turns in opposite directions when viewed from the same direction as another adjacent unit winding. And a set of unit windings adjacent to each other of the coil are connected alternately at the tips or ends of the spiral pattern.
  • the invention described in claim 3 has the feature that, in addition to the features of the invention described in claim 1 or 2, the coil has a conductive part in which winding portions parallel to the multilayer substrate are laminated. A winding part formed as a part of a layer and perpendicular to the multilayer substrate is formed as a bump connecting the adjacent conductive layers via the insulating layer.
  • the invention described in claim 4 has the feature that, in addition to the features of the invention described in claim 1 or 2, the coil has a winding portion parallel to the multilayer substrate by a build-up method. And a winding portion formed as a part of the stacked conductive layers and perpendicular to the multilayer substrate is formed as a via or a through hole connecting the adjacent conductive layers through the insulating layer.
  • the invention described in claim 5 is an external conductor formed integrally with the multilayer substrate, the external conductor including a conductor portion parallel to the multilayer substrate and a conductor portion perpendicular to the multilayer substrate. And a conductive wire formed integrally with the multilayer substrate, wherein the conductive wire is formed inside the outer conductor.
  • the invention described in claim 6 is characterized in that, in addition to the features of the invention described in claim 5, the outer conductor is such that a conductor portion parallel to the multilayer substrate is a conductor strip. I do.
  • the invention according to claim 7 is the invention according to claim 5 or 6, wherein the outer conductor is a conductor in which a conductor portion parallel to the multilayer substrate is laminated. A conductor portion formed as a part of an electric layer and perpendicular to the multilayered layer is formed as a bump connecting the adjacent conductive layers via the insulating layer.
  • the invention according to claim 8 has the feature that, in addition to the features of the invention according to claim 5 or 6, the outer conductor has a conductor portion parallel to the multilayer substrate by a bifured-up method. A conductor portion formed as a part of the stacked conductive layers and perpendicular to the multi-layer substrate, formed as a via or a single hole connecting the adjacent conductive layers through the insulating layer. .
  • a feature of the invention set forth in claim 9 is that the multilayer steel sheet including the multilayer S anti-inner shield wire according to any one of claims 1 to 8 is laminated on an outer surface. Sign.
  • the invention described in claim 10 is any one of claims 1 to 8 And mounted on the multilayer substrate including the shielded wire in the multilayer substrate described in (1).
  • the invention according to claim 11 includes a step of forming one insulating layer constituting a multilayer substrate; and forming at least a part of a winding portion of a coil parallel to the multilayer substrate in the multilayer substrate. Forming a conductive wire inside the coil with the coil and the insulating layer interposed therebetween; and at least a part of the winding portion of the coil parallel to the multilayer substrate.
  • the invention described in claim 12 is characterized in that, in addition to the features of the invention described in claim 11, the unit winding of the predetermined coil is in the same direction as another adjacent unit winding.
  • Each of which has a spiral pattern that turns in the opposite direction when viewed from above, and sets of unit windings adjacent to each other of the predetermined coil are formed at the leading ends or the trailing ends of the spiral pattern. Are connected alternately.
  • the invention described in claim 13 is a step of forming one insulating layer constituting a multilayer substrate, and forming at least a part of a conductor portion of an external conductor parallel to the multilayer substrate with an insulating layer in the multilayer substrate. Forming a conductive wire on the inner side of the outer conductor with the outer conductor and the insulating layer interposed therebetween; and at least a part of the conductor portions of the outer conductor parallel to the multilayer structure. A vertical connection portion for electrically connecting the outer conductor between the insulating layers, thereby forming a conductor portion of the outer conductor perpendicular to the multilayer substrate.
  • the invention described in claim 14 is characterized in that, in addition to the features of the invention described in claim 13, the conductor portion of the external conductor parallel to the multilayer substrate is a conductor strip.
  • the invention according to claim 15 is characterized in that, in addition to the features of the invention described in any one of claims 11 to 14, the shielded wire in the multilayer substrate is a semiconductor wafer. And a step of cutting the semiconductor wafer, on which the shield wires in the multilayer substrate are stacked, into semiconductor chip units.
  • the invention according to claim 16 is characterized in that, in addition to the features of the invention described in any one of claims 11 to 14, the shield wire in the multilayer substrate is provided on an outer surface of the semiconductor chip. It is characterized by being laminated.
  • the invention according to claim 17 is characterized in that, in addition to the features of the invention according to any one of claims 11 to 14, An electronic circuit element is mounted on the electronic device.
  • FIG. 1A is a perspective view showing a schematic configuration of a shield wire 1 in a multilayer substrate according to a first embodiment of the present invention
  • FIG. 1B is a perspective view showing a structure according to a second embodiment of the present invention
  • FIG. 1 is a perspective view showing a schematic configuration of a shielded wire 2 in a multilayer board
  • FIG. 1D is a perspective view showing a schematic configuration of a shield wire 3 in a multilayer substrate according to the embodiment
  • FIG. 1D is a perspective view showing a schematic configuration of a shield wire 4 in the multilayer substrate according to a fourth embodiment of the present invention.
  • Fig. 1 (e) and Fig. 1 (: f) are diagrams showing examples of the structure of another coil.
  • FIG. 2 is a schematic perspective view of an initial stage of manufacturing the shield wire 4 in the multilayer substrate.
  • FIG. 3 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 4 in the multilayer substrate.
  • FIG. 4 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 1 ′ in the multilayer substrate.
  • FIG. 5 is a conceptual perspective view showing an example of a method of manufacturing the shield wires 1-4 in the multilayer substrate.
  • FIG. 6 is a conceptual perspective view showing an example of a method for manufacturing the shield wire 4 in the multilayer substrate.
  • FIG. 7 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 4 in the multilayer substrate.
  • FIG. 8 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 1'4 in the multilayer substrate.
  • FIG. 9 is a schematic perspective view showing an example of a method for manufacturing the shield wires 1-4 in the multilayer substrate.
  • FIG. 10 is a conceptual perspective view showing an example of a method for producing the shield wires 4 in the multilayer substrate.
  • FIG. 11 is a conceptual perspective view showing an example of a method of manufacturing the shield wires 4 in the multilayer substrate.
  • FIG. 12 is a perspective conceptual view showing an example of a method of manufacturing the shield wires 4 in the multilayer substrate.
  • FIG. 13 is a cross-sectional view of the initial stage of manufacturing when the shield wires 4 in the multilayer substrate are formed on the semiconductor wafer.
  • FIG. 14 is a cross-sectional view for explaining via formation.
  • FIG. 15 is a cross-sectional view for explaining formation of a conductive pattern for forming a circuit.
  • FIG. 16 is a cross-sectional view for explaining the formation of the second insulating layer.
  • FIG. 17 is a cross-sectional view for explaining the formation of the second conductive pattern.
  • FIG. 18 is a conceptual cross-sectional view of a shield line in a multilayer substrate formed on a semiconductor wafer.
  • FIG. 19 is a conceptual cross-sectional view of a via.
  • FIG. 20 shows an example of a shield line in a multilayer substrate formed on a semiconductor wafer. It is sectional conceptual drawing.
  • FIG. 21 is a conceptual sectional view showing an example of a shield line in a multilayer substrate formed on a semiconductor wafer.
  • FIG. 1A is a perspective view showing a schematic configuration of a shield line 1 in a multilayer substrate.
  • the shielded wire 1 in the multilayer board is composed of a coil la, a conductor lb, and a multilayer board lc.
  • the coil la is a component that functions as an outer conductor of the shielded wire, which is formed as a part of the conductive layer in each step of forming a plurality of insulating layers and conductive layers in the multilayer substrate.
  • the coil la has a central axis parallel to the multilayer substrate, and includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate.
  • the coil 1a is preferably formed in a form in which unit windings having a repeating pattern of conducting wires having a rectangular or circular cross section are electrically and continuously connected in series.
  • the form of the coil 1a and its unit winding in the present specification widely includes any form that functions as an outer conductor of the shielded wire.
  • the winding portion of the coil la parallel to the multilayer substrate is formed as a part of the conductive layer to be laminated, and the winding portion perpendicular to the multilayer substrate is formed between the adjacent conductive layers via the insulating layer.
  • the coil 1a is formed as a connecting bump, via, or through hole.
  • the coil 1a is simultaneously formed in the multilayer substrate in a multilayer substrate manufacturing process using a known multilayer substrate (printed circuit board) manufacturing technique such as a build-up method. Can be achieved.
  • the conducting wire lb is formed inside the coil 1a with the coil 1a and the insulating layer interposed in the manufacturing process of the multilayer board.
  • the multilayer lc is a substrate configured by laminating insulating layers. In the actual step of forming the multilayer substrate 1c, insulating layers and conductive layers are alternately laminated. And the conductive layer part is in front It becomes a part of the coil 1a described above, and the other insulating layer part becomes the multilayer substrate 1c.
  • FIG. 1B is a perspective view showing a schematic configuration of the shield line 2 in the multilayer substrate.
  • the multilayer inner shield wire 2 includes a coil 2a, a conductor 2b, and a multilayer board 2c.
  • the unit windings of the coil 2a each have a helical pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings. They are connected to each other at the tips or ends of the spiral pattern.
  • FIG. 1C is a perspective view showing a schematic configuration of the shield wire 3 in the multilayer substrate.
  • the shield wire 3 in the multilayer board is composed of an outer conductor 3a, a conductor 3b, and a multilayer board 3c.
  • the outer conductor 3a includes a conductor portion parallel to the multilayer substrate 3c and a conductor portion perpendicular to the multilayer substrate.
  • the conductor portion may be strip-shaped or linear.
  • Fig. 1 (c) shows an example of a cage-shaped outer conductor consisting of linear conductors.
  • FIG. 1D is a perspective view showing a schematic configuration of the shield line 4 in the multilayer substrate.
  • the shield wire 4 in the multilayer board is composed of an outer conductor (parallel outer conductor 4a parallel to the multilayer board 4d and vertical outer conductor 4b perpendicular to the multilayer board 4d), a conductor 4c, and a multilayer board 4d. Is done.
  • the parallel outer conductor 4a is a conductor strip.
  • FIG. 1 (e) and (f) are examples of other coil structures. In these examples, the coil is constituted only by a winding portion in a direction parallel or perpendicular to the center axis of the coil.
  • the shield lines 1 to 4 in the multilayer substrate are also suitable for use as an imposer for mounting a semiconductor chip constituting a monolithic IC or the like thereon.
  • the shielded wires 1 to 4 in the multilayer board can be formed with other circuit elements inside or mounted outside, and such other circuit elements and the shield wires 1 to 4 in the multilayer board can be used. It is possible to configure a semiconductor package in which the function of the circuit to be configured is added to the function of the semiconductor chip itself.
  • the length of the shield wires 1 to 4 in the multilayer substrate can be easily and almost arbitrarily set by adjusting the extension direction of the coil or the external conductor.
  • the shield lines 1 to 4 in the multilayer substrate are supplied with a current such as a signal which is not preferably affected by noise through the internal conductor.
  • a current such as a signal which is not preferably affected by noise through the internal conductor.
  • the coil or external conductor should be grounded at one point. This achieves electrostatic shielding.
  • electromagnetic shielding it is recommended to use a coil or an external conductor as the return path of the current flowing through the conductor, so that it can be used similarly to a coaxial cable. Thereby, electromagnetic shielding is achieved.
  • it also prevents the current flowing through the conductor from affecting other surrounding wiring and elements.
  • a structure similar to the coaxial cable is applied to signal lines of print anti-collision, IC, and electronic equipment. That is, by sequentially forming an insulating layer, drilling holes, and forming a conductor pattern in parallel with the plane of the substrate, a part of the coil is formed in parallel with the plane of the substrate, and by repeating this, an electrical connection is obtained.
  • a coil-shaped circuit having a circuit surface perpendicular to the opposite plane can be formed in a spiral shape.
  • a coil can be formed on a plane parallel to the substrate plane, and a signal line penetrating therethrough can be formed using a via hole or the like.
  • the signal lines are very delicate and it is difficult to form a very uniform circuit in the vertical direction.
  • a coil can be easily obtained only at a desired portion.
  • the method may be applied to a portion that may generate an electromagnetic wave, so that a structure in which the electromagnetic wave does not leak to the outside of the portion can be obtained.
  • the method of the present invention cannot cover the entire periphery of the signal line like a general coaxial cable.
  • the method of the present invention It is known that there is no problem with the shielding effect even if there is a gap in the “cover”.
  • the extension direction of the coil can be set to an arbitrary direction on the plane of the substrate, the coil can be formed in the same process in any direction as necessary.
  • a method of manufacturing the shielded wires 1 to 4 in the multilayer substrate according to the present invention will be described together with advantages as compared with the prior art.
  • the case of the shielded wire 1 in a multi-layer substrate shown in Fig. 1 (a) using a shield using a single-layer coil and using an organic material as an insulator will be described.
  • a core substrate 1d having a through-hole serving as a part of a coil and a conductor 1b serving as a signal line is prepared.
  • Materials include known and commonly used copper-clad laminates, such as glass epoxy resin and bismaleimide-triazine substrates.
  • Drilling can be performed by a widely used method such as a drill or a carbon dioxide laser or a YAG laser.
  • the conductor can be patterned by a known and commonly used method such as a subtractive method or an additive method.
  • outermost layers 1e are laminated and formed on both surfaces of the core substrate 1d as shown in FIG.
  • the same material and method as the core material can be used for the material of the insulating layer, the drilling method, and the setting method.
  • an insulating layer and a conductive layer may be formed on both sides of the inner layer material, and the patterning and electrical connection may be performed.
  • the insulating layer is formed on a substrate made of the above inner layer material.
  • the insulating layer is a prepreg such as glass epoxy or aramide resin, a liquid or film-like thermoplastic or thermosetting resin composition, or a copper foil and an insulating resin layer, which is generally called resin-coated copper foil. Can be used.
  • the formation of the insulating layer is performed, for example, as follows.
  • prepregs 5, unpatterned copper foil 6, or resin-coated copper foil 7 as shown in Fig. 4 (b) are provided on both sides of the core substrate 1d. They are arranged, and they are collectively laminated and cured by a lamination press method as shown in Fig. 5, to create an integrated insulating layer and conductive layer.
  • a liquid composition is applied onto the above 1d by a known and conventional method such as screen printing, force coating, spray coating, etc., and cured by UV, electron beam, heat, or the like.
  • a film-shaped composition is pasted on the substrate by a method such as roll or lamination, and cured by a predetermined method to obtain an insulating layer 8. Subsequently, a via is formed. Drill and drill at predetermined positions on the substrate obtained by the above method.
  • Fig. 7 (a) shows the case where the pre-preda 5 and the copper foil 6 are used as the insulating layer and the conductive layer.
  • Fig. 7 (b) shows the copper foil 7 with resin
  • Fig. 7 (c) shows the liquid or film-like thermoplastic.
  • the thermosetting resin composition 8 is used is described.
  • a conductive paste containing a conductive powder such as silver or copper in a via is used. Is embedded by printing, dispensing, etc., and cured by a predetermined method.
  • a normal through-hole plating that is, an electroless plating after applying a plating catalyst in the via, followed by an electrolytic plating, is used.
  • the electrical connection can also be achieved by the method of forming.
  • the blind via is conductively connected with the conductive paste 10 or the print layer 11 to be connected.
  • the blind via may be made conductive first.
  • a catalyst is applied to the substrate on which the insulating layer and the blind via are formed, and electroless plating is performed, and then, if necessary, electrolytic plating is performed.
  • the formation of the layer 13 and the conduction of the blind via can also be performed at once.
  • the blind via can be made conductive by using a conductive paste.
  • the insulating layer, the conductive layer, and the electrical connection can be collectively performed by the following method. That is, as shown in FIG. 9, the conductive layer is placed at a predetermined position on the inner layer circuit 1d. After forming conductive bumps 14 with sharp tips using a paste or the like, prepreg 5 and copper foil 6 (Fig. 9 (a)) or film-like insulator 8 and copper foil 6 (Fig. 9 (b) ) Or press processing after placing the resin-coated copper foil 7 (FIG. 9 (c)) allows the sharp conductive bumps 14 to penetrate the insulating layer and realize connection with the conductive layer.
  • through holes or blind vias may be filled with a filling or filling process for filling holes to smooth the surface.
  • a four-layer structure using a glass epoxy pre-preda as the insulating layer will be described. That is, as shown in FIG. 10, a predetermined position on the base material 15 side of the copper-clad single-sided glass epoxy substrate is punched using a laser or the like. Subsequently, electric plating is performed using the copper foil 16 as an electrode, and the resulting hole is filled with the plating 17. Then, a low melting point metal bump 18 is continuously formed by the plating method.
  • the copper foil 16 is etched into a predetermined pattern as shown in FIG.
  • the conductor portion of the external conductor parallel to the multilayer substrate is used as the conductor strip (in the case of the shield wire 4 in the multilayer substrate)
  • this etching is not necessary.
  • the same composition 19 as that used for the insulating layer is thinly applied to the bump side and semi-cured.
  • the one manufactured from this single-sided substrate is the outermost layer, that is, the first and fourth layers.
  • the inner layer 1 d and the outermost layer of FIG. 11 are aligned, and the composition that has been semi-hardened by pressing is removed from the bump portion, and the insulation between the layers is removed.
  • the bump portion is electrically connected to the conductor of the inner layer, and a multilayer anti-inner shield line 1 in which a signal line is disposed through a coil having a four-layer structure is manufactured.
  • the shield wire 3 in the multilayer substrate can also be easily manufactured.
  • an electronic circuit element including the structure of the shield wires 1 to 4 in the multilayer substrate of the present invention can be easily manufactured. it can.
  • the shielded wire of the present invention can be formed by sequentially performing a method of forming a hole in a green sheet, filling a hole with a conductive paste, printing a pattern, laminating, and firing, which are conventional methods.
  • the process of simultaneously forming a coil or an external conductor and a conductor having a central axis in a direction parallel to the substrate plane on a semiconductor substrate will be described below.
  • the number of evenings, the number of columns (layers), the direction of formation, etc. can be set arbitrarily.
  • a lowermost insulating layer 21 is formed on a silicon wafer 20 on which transistors and electrode portions are formed.
  • the silicon oxide film can be formed using a vapor phase method such as CVD, or by spin coating an organic material such as polyimide or benzocyclobutene, which has recently attracted attention, and then performing a post-baking process. Subsequently, as shown in FIG. 14, necessary holes 22 are formed using various lasers. The hole 22 is where electrical connection with the lower electrode portion is made. Then, as shown in Figure 15 Thus, the conductive pattern 23 is formed.
  • a commonly used method is aluminum sputtering, or a copper layer is formed by a vapor phase method such as CVD or a wet method such as a plating method. Then, patterning is performed by exposing and etching. In this case, the conductive layer may be formed after the patterned resist layer is formed.
  • the hole 22 drilled in the step shown in FIG. 14 is also electrically conductive, and the first layer and the second layer are electrically connected.
  • the surface is usually flattened by physical polishing or a combination of chemical polishing and physical polishing called a CMP method.
  • a second insulating layer 24 is formed.
  • a hole is formed again, and a conductive pattern 25 of the second layer is formed by forming a conductive pattern.
  • a conductive wire can be formed at the same time.
  • a third insulating layer 26 is formed by the above-described method, a hole is formed, the conductive layer is patterned, a third conductive pattern 27 is formed, and the second layer and the third layer are formed. Take continuity of the layers. At this stage, the following can be formed on the semiconductor as shown in FIG. By applying this operation, it is possible to easily increase or decrease the number of evenings, increase or decrease the number of rows (layers), or form multiple shield wires having different extending directions.
  • a structure generally called a stacked via that is, a structure having a via hole can be formed again on a filled via hole, and the side of the coil can be made straight.
  • the silicon wafer 20 and the multilayer substrate including the shield line are separated into semiconductor chip units.
  • the silicon wafer 20 Before laminating a multilayer substrate incorporating a shield wire on silicon wafer 20 Alternatively, the silicon wafer 20 can be cut into chips. In this case, a multilayer substrate having a built-in shield line may be laminated on the outer surface of the semiconductor chip cut in advance in the same manner as the above process.
  • a stacked via structure cannot be formed by a commonly used method, that is, a method in which a via hole is not filled with a conductor. At that time, the manufactured coil has a cross-section in which the via-hole connection portion is stepped, as shown in FIG. Such a structure has no practical effect on the shielding effect.
  • the structure manufactured by the method of the present invention has a structure in which the signal line is covered with a coil or an external conductor formed at the same time. The effect increases.

Abstract

L'invention concerne un petit fil métallique de blindage dans une carte multicouches non sensible au bruit et son procédé de production. Ce fil monté dans une carte constitue une bobine formée de manière solidaire avec la carte, et se caractérise en ce qu'une partie de son enroulement est parallèle à la carte, et un conducteur est formé dans cette même bobine.
PCT/JP2003/006647 2002-05-29 2003-05-28 Fil metallique de blindage dans une carte multicouches, puce a semi-conducteurs, element de circuit electronique et procede de production de ce fil WO2003100852A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU2003241819A AU2003241819A1 (en) 2002-05-29 2003-05-28 Shielding wire in multilayer board, semiconductor chip, electronic circuit element, and method for producing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002156262A JP2005347287A (ja) 2002-05-29 2002-05-29 多層基板内シールド線、半導体チップ、電子回路素子、及びそれらの製造方法
JP2002-156262 2002-05-29

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JP5177387B2 (ja) * 2008-02-08 2013-04-03 日本電気株式会社 インダクタ用シールドおよびシールド付きインダクタ
JP5307664B2 (ja) * 2009-08-27 2013-10-02 京セラ株式会社 多層基板および電子機器
US11538766B2 (en) 2019-02-26 2022-12-27 Texas Instruments Incorporated Isolated transformer with integrated shield topology for reduced EMI
JP2020202255A (ja) * 2019-06-07 2020-12-17 株式会社デンソー 電子装置

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JPH04237106A (ja) * 1991-01-21 1992-08-25 Nippon Telegr & Teleph Corp <Ntt> 集積化インダクタンス素子及び集積化トランス
JPH0555043A (ja) * 1991-08-22 1993-03-05 Fujitsu Ltd 小型コイルとその製造方法，磁気ヘツドの製造方法及び磁気記憶装置
EP0588503A2 (fr) * 1992-09-10 1994-03-23 National Semiconductor Corporation Circuit intégré d'élément de mémoire magnétique et sa méthode de fabrication
JPH06112655A (ja) * 1992-09-29 1994-04-22 Matsushita Electric Ind Co Ltd コイル内蔵多層印刷配線板およびその製造方法
JPH10154795A (ja) * 1996-11-19 1998-06-09 Advanced Materials Eng Res Inc 半導体チップにおけるインダクター及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04237106A (ja) * 1991-01-21 1992-08-25 Nippon Telegr & Teleph Corp <Ntt> 集積化インダクタンス素子及び集積化トランス
JPH0555043A (ja) * 1991-08-22 1993-03-05 Fujitsu Ltd 小型コイルとその製造方法，磁気ヘツドの製造方法及び磁気記憶装置
EP0588503A2 (fr) * 1992-09-10 1994-03-23 National Semiconductor Corporation Circuit intégré d'élément de mémoire magnétique et sa méthode de fabrication
JPH06112655A (ja) * 1992-09-29 1994-04-22 Matsushita Electric Ind Co Ltd コイル内蔵多層印刷配線板およびその製造方法
JPH10154795A (ja) * 1996-11-19 1998-06-09 Advanced Materials Eng Res Inc 半導体チップにおけるインダクター及びその製造方法

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