WO2003100852A1 - Shielding wire in multilayer board, semiconductor chip, electronic circuit element, and method for producing the same - Google Patents

Shielding wire in multilayer board, semiconductor chip, electronic circuit element, and method for producing the same Download PDF

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Publication number
WO2003100852A1
WO2003100852A1 PCT/JP2003/006647 JP0306647W WO03100852A1 WO 2003100852 A1 WO2003100852 A1 WO 2003100852A1 JP 0306647 W JP0306647 W JP 0306647W WO 03100852 A1 WO03100852 A1 WO 03100852A1
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WO
WIPO (PCT)
Prior art keywords
multilayer substrate
conductor
coil
forming
parallel
Prior art date
Application number
PCT/JP2003/006647
Other languages
French (fr)
Japanese (ja)
Inventor
Kouichirou Sagawa
Masahiko Oshimura
Original Assignee
Ajinomoto Co.,Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ajinomoto Co.,Inc. filed Critical Ajinomoto Co.,Inc.
Priority to AU2003241819A priority Critical patent/AU2003241819A1/en
Publication of WO2003100852A1 publication Critical patent/WO2003100852A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H01F27/363—Electric or magnetic shields or screens made of electrically conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/645—Inductive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/34—Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields
    • H01F27/36—Electric or magnetic shields or screens
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors

Definitions

  • the present invention relates to a shield line, and more particularly, to a shield line formed in a multilayer substrate, and an electronic circuit element and a semiconductor chip on which the multilayer substrate is laminated.
  • the optimal arrangement of the elements is basically a matter of trial and error and is very inefficient.
  • the shield it is also practiced to cover the entire device or element with a copper plate or a paste made of copper as a main component.
  • a method of covering the entire device has no effect on the noise generated inside the device, and the method of covering the elements has many problems such as difficulty in high-density mounting.
  • the above-mentioned external shield cannot cope with it.
  • a coaxial cable-like structure described later that is, a GND with a large area, ideally an infinite area above and below a strip line used for signal transmission on the inner layer of the board Structures sandwiched between surfaces have been widely used.
  • this structure requires a large area for use in recent small-sized devices, and has many disadvantages.
  • a plurality of multilayer coils having a circuit surface in a direction perpendicular to the plane of the substrate and a method of manufacturing the same are disclosed in, for example, Japanese Patent Application Laid-Open No. H11-251146, which is suitable as a chip inductor.
  • a coil is formed in a direction perpendicular to the plane of the substrate in order to reduce the influence of external electromagnetic noise on the signal line wired in a plane parallel to the X direction.
  • a structure in which another circuit passes through the inside of the coil are disclosed in, for example, Japanese Patent Application Laid-Open No. H11-251146, which is suitable as a chip inductor.
  • Japanese Patent Application Laid-Open No. H11-1-26462 discloses a method for forming multiple solenoid coils around a semiconductor substrate for use in ICs. This method is an invention for obtaining a larger inductance, but it is also effective for avoiding noise of its internal elements. However, in this method, a very large volume has to be used for the coil portion, which is very problematic in terms of miniaturization. Further, as in the case of the chip induction, there is no mention of a structure in which another circuit passes through the inside of the coil.
  • Such include coaxial cables in addition to the stripline described above.
  • the signal line connected from the TV antenna to the receiver is covered with copper to reduce the effects of external noise.
  • Coaxial cables unlike strip lines, do not require a large area GND surface. Therefore, it has a structure similar to such a coaxial cable If shield lines can be formed in a multilayer board (printed circuit board), it would be possible to achieve both effective noise shielding and miniaturization.
  • a semiconductor chip (ic) and an electronic circuit element using such a small shielded line for a signal line can be produced. It is thought that it is possible.
  • a small shielded wire that uses a coil-shaped conductor, a cage-shaped conductor, or a conductor strip as the outer conductor of the shielded wire can be considered. I didn't.
  • An object of the present invention is to provide a shielded wire in a multilayer substrate which can save important signal lines in a high-frequency region from electromagnetic waves in a small space, and a method of manufacturing the same.
  • the invention according to claim 1 is a coil formed integrally with the multilayer substrate, wherein the coil includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. And a conductive wire formed integrally with the multilayer substrate, wherein the conductive wire is formed inside the coil.
  • the invention according to claim 2 is characterized in that the unit winding of the coil has a spiral pattern that turns in opposite directions when viewed from the same direction as another adjacent unit winding. And a set of unit windings adjacent to each other of the coil are connected alternately at the tips or ends of the spiral pattern.
  • the invention described in claim 3 has the feature that, in addition to the features of the invention described in claim 1 or 2, the coil has a conductive part in which winding portions parallel to the multilayer substrate are laminated. A winding part formed as a part of a layer and perpendicular to the multilayer substrate is formed as a bump connecting the adjacent conductive layers via the insulating layer.
  • the invention described in claim 4 has the feature that, in addition to the features of the invention described in claim 1 or 2, the coil has a winding portion parallel to the multilayer substrate by a build-up method. And a winding portion formed as a part of the stacked conductive layers and perpendicular to the multilayer substrate is formed as a via or a through hole connecting the adjacent conductive layers through the insulating layer.
  • the invention described in claim 5 is an external conductor formed integrally with the multilayer substrate, the external conductor including a conductor portion parallel to the multilayer substrate and a conductor portion perpendicular to the multilayer substrate. And a conductive wire formed integrally with the multilayer substrate, wherein the conductive wire is formed inside the outer conductor.
  • the invention described in claim 6 is characterized in that, in addition to the features of the invention described in claim 5, the outer conductor is such that a conductor portion parallel to the multilayer substrate is a conductor strip. I do.
  • the invention according to claim 7 is the invention according to claim 5 or 6, wherein the outer conductor is a conductor in which a conductor portion parallel to the multilayer substrate is laminated. A conductor portion formed as a part of an electric layer and perpendicular to the multilayered layer is formed as a bump connecting the adjacent conductive layers via the insulating layer.
  • the invention according to claim 8 has the feature that, in addition to the features of the invention according to claim 5 or 6, the outer conductor has a conductor portion parallel to the multilayer substrate by a bifured-up method. A conductor portion formed as a part of the stacked conductive layers and perpendicular to the multi-layer substrate, formed as a via or a single hole connecting the adjacent conductive layers through the insulating layer. .
  • a feature of the invention set forth in claim 9 is that the multilayer steel sheet including the multilayer S anti-inner shield wire according to any one of claims 1 to 8 is laminated on an outer surface. Sign.
  • the invention described in claim 10 is any one of claims 1 to 8 And mounted on the multilayer substrate including the shielded wire in the multilayer substrate described in (1).
  • the invention according to claim 11 includes a step of forming one insulating layer constituting a multilayer substrate; and forming at least a part of a winding portion of a coil parallel to the multilayer substrate in the multilayer substrate. Forming a conductive wire inside the coil with the coil and the insulating layer interposed therebetween; and at least a part of the winding portion of the coil parallel to the multilayer substrate.
  • the invention described in claim 12 is characterized in that, in addition to the features of the invention described in claim 11, the unit winding of the predetermined coil is in the same direction as another adjacent unit winding.
  • Each of which has a spiral pattern that turns in the opposite direction when viewed from above, and sets of unit windings adjacent to each other of the predetermined coil are formed at the leading ends or the trailing ends of the spiral pattern. Are connected alternately.
  • the invention described in claim 13 is a step of forming one insulating layer constituting a multilayer substrate, and forming at least a part of a conductor portion of an external conductor parallel to the multilayer substrate with an insulating layer in the multilayer substrate. Forming a conductive wire on the inner side of the outer conductor with the outer conductor and the insulating layer interposed therebetween; and at least a part of the conductor portions of the outer conductor parallel to the multilayer structure. A vertical connection portion for electrically connecting the outer conductor between the insulating layers, thereby forming a conductor portion of the outer conductor perpendicular to the multilayer substrate.
  • the invention described in claim 14 is characterized in that, in addition to the features of the invention described in claim 13, the conductor portion of the external conductor parallel to the multilayer substrate is a conductor strip.
  • the invention according to claim 15 is characterized in that, in addition to the features of the invention described in any one of claims 11 to 14, the shielded wire in the multilayer substrate is a semiconductor wafer. And a step of cutting the semiconductor wafer, on which the shield wires in the multilayer substrate are stacked, into semiconductor chip units.
  • the invention according to claim 16 is characterized in that, in addition to the features of the invention described in any one of claims 11 to 14, the shield wire in the multilayer substrate is provided on an outer surface of the semiconductor chip. It is characterized by being laminated.
  • the invention according to claim 17 is characterized in that, in addition to the features of the invention according to any one of claims 11 to 14, An electronic circuit element is mounted on the electronic device.
  • FIG. 1A is a perspective view showing a schematic configuration of a shield wire 1 in a multilayer substrate according to a first embodiment of the present invention
  • FIG. 1B is a perspective view showing a structure according to a second embodiment of the present invention
  • FIG. 1 is a perspective view showing a schematic configuration of a shielded wire 2 in a multilayer board
  • FIG. 1D is a perspective view showing a schematic configuration of a shield wire 3 in a multilayer substrate according to the embodiment
  • FIG. 1D is a perspective view showing a schematic configuration of a shield wire 4 in the multilayer substrate according to a fourth embodiment of the present invention.
  • Fig. 1 (e) and Fig. 1 (: f) are diagrams showing examples of the structure of another coil.
  • FIG. 2 is a schematic perspective view of an initial stage of manufacturing the shield wire 4 in the multilayer substrate.
  • FIG. 3 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 4 in the multilayer substrate.
  • FIG. 4 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 1 ′ in the multilayer substrate.
  • FIG. 5 is a conceptual perspective view showing an example of a method of manufacturing the shield wires 1-4 in the multilayer substrate.
  • FIG. 6 is a conceptual perspective view showing an example of a method for manufacturing the shield wire 4 in the multilayer substrate.
  • FIG. 7 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 4 in the multilayer substrate.
  • FIG. 8 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 1'4 in the multilayer substrate.
  • FIG. 9 is a schematic perspective view showing an example of a method for manufacturing the shield wires 1-4 in the multilayer substrate.
  • FIG. 10 is a conceptual perspective view showing an example of a method for producing the shield wires 4 in the multilayer substrate.
  • FIG. 11 is a conceptual perspective view showing an example of a method of manufacturing the shield wires 4 in the multilayer substrate.
  • FIG. 12 is a perspective conceptual view showing an example of a method of manufacturing the shield wires 4 in the multilayer substrate.
  • FIG. 13 is a cross-sectional view of the initial stage of manufacturing when the shield wires 4 in the multilayer substrate are formed on the semiconductor wafer.
  • FIG. 14 is a cross-sectional view for explaining via formation.
  • FIG. 15 is a cross-sectional view for explaining formation of a conductive pattern for forming a circuit.
  • FIG. 16 is a cross-sectional view for explaining the formation of the second insulating layer.
  • FIG. 17 is a cross-sectional view for explaining the formation of the second conductive pattern.
  • FIG. 18 is a conceptual cross-sectional view of a shield line in a multilayer substrate formed on a semiconductor wafer.
  • FIG. 19 is a conceptual cross-sectional view of a via.
  • FIG. 20 shows an example of a shield line in a multilayer substrate formed on a semiconductor wafer. It is sectional conceptual drawing.
  • FIG. 21 is a conceptual sectional view showing an example of a shield line in a multilayer substrate formed on a semiconductor wafer.
  • FIG. 1A is a perspective view showing a schematic configuration of a shield line 1 in a multilayer substrate.
  • the shielded wire 1 in the multilayer board is composed of a coil la, a conductor lb, and a multilayer board lc.
  • the coil la is a component that functions as an outer conductor of the shielded wire, which is formed as a part of the conductive layer in each step of forming a plurality of insulating layers and conductive layers in the multilayer substrate.
  • the coil la has a central axis parallel to the multilayer substrate, and includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate.
  • the coil 1a is preferably formed in a form in which unit windings having a repeating pattern of conducting wires having a rectangular or circular cross section are electrically and continuously connected in series.
  • the form of the coil 1a and its unit winding in the present specification widely includes any form that functions as an outer conductor of the shielded wire.
  • the winding portion of the coil la parallel to the multilayer substrate is formed as a part of the conductive layer to be laminated, and the winding portion perpendicular to the multilayer substrate is formed between the adjacent conductive layers via the insulating layer.
  • the coil 1a is formed as a connecting bump, via, or through hole.
  • the coil 1a is simultaneously formed in the multilayer substrate in a multilayer substrate manufacturing process using a known multilayer substrate (printed circuit board) manufacturing technique such as a build-up method. Can be achieved.
  • the conducting wire lb is formed inside the coil 1a with the coil 1a and the insulating layer interposed in the manufacturing process of the multilayer board.
  • the multilayer lc is a substrate configured by laminating insulating layers. In the actual step of forming the multilayer substrate 1c, insulating layers and conductive layers are alternately laminated. And the conductive layer part is in front It becomes a part of the coil 1a described above, and the other insulating layer part becomes the multilayer substrate 1c.
  • FIG. 1B is a perspective view showing a schematic configuration of the shield line 2 in the multilayer substrate.
  • the multilayer inner shield wire 2 includes a coil 2a, a conductor 2b, and a multilayer board 2c.
  • the unit windings of the coil 2a each have a helical pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings. They are connected to each other at the tips or ends of the spiral pattern.
  • FIG. 1C is a perspective view showing a schematic configuration of the shield wire 3 in the multilayer substrate.
  • the shield wire 3 in the multilayer board is composed of an outer conductor 3a, a conductor 3b, and a multilayer board 3c.
  • the outer conductor 3a includes a conductor portion parallel to the multilayer substrate 3c and a conductor portion perpendicular to the multilayer substrate.
  • the conductor portion may be strip-shaped or linear.
  • Fig. 1 (c) shows an example of a cage-shaped outer conductor consisting of linear conductors.
  • FIG. 1D is a perspective view showing a schematic configuration of the shield line 4 in the multilayer substrate.
  • the shield wire 4 in the multilayer board is composed of an outer conductor (parallel outer conductor 4a parallel to the multilayer board 4d and vertical outer conductor 4b perpendicular to the multilayer board 4d), a conductor 4c, and a multilayer board 4d. Is done.
  • the parallel outer conductor 4a is a conductor strip.
  • FIG. 1 (e) and (f) are examples of other coil structures. In these examples, the coil is constituted only by a winding portion in a direction parallel or perpendicular to the center axis of the coil.
  • the shield lines 1 to 4 in the multilayer substrate are also suitable for use as an imposer for mounting a semiconductor chip constituting a monolithic IC or the like thereon.
  • the shielded wires 1 to 4 in the multilayer board can be formed with other circuit elements inside or mounted outside, and such other circuit elements and the shield wires 1 to 4 in the multilayer board can be used. It is possible to configure a semiconductor package in which the function of the circuit to be configured is added to the function of the semiconductor chip itself.
  • the length of the shield wires 1 to 4 in the multilayer substrate can be easily and almost arbitrarily set by adjusting the extension direction of the coil or the external conductor.
  • the shield lines 1 to 4 in the multilayer substrate are supplied with a current such as a signal which is not preferably affected by noise through the internal conductor.
  • a current such as a signal which is not preferably affected by noise through the internal conductor.
  • the coil or external conductor should be grounded at one point. This achieves electrostatic shielding.
  • electromagnetic shielding it is recommended to use a coil or an external conductor as the return path of the current flowing through the conductor, so that it can be used similarly to a coaxial cable. Thereby, electromagnetic shielding is achieved.
  • it also prevents the current flowing through the conductor from affecting other surrounding wiring and elements.
  • a structure similar to the coaxial cable is applied to signal lines of print anti-collision, IC, and electronic equipment. That is, by sequentially forming an insulating layer, drilling holes, and forming a conductor pattern in parallel with the plane of the substrate, a part of the coil is formed in parallel with the plane of the substrate, and by repeating this, an electrical connection is obtained.
  • a coil-shaped circuit having a circuit surface perpendicular to the opposite plane can be formed in a spiral shape.
  • a coil can be formed on a plane parallel to the substrate plane, and a signal line penetrating therethrough can be formed using a via hole or the like.
  • the signal lines are very delicate and it is difficult to form a very uniform circuit in the vertical direction.
  • a coil can be easily obtained only at a desired portion.
  • the method may be applied to a portion that may generate an electromagnetic wave, so that a structure in which the electromagnetic wave does not leak to the outside of the portion can be obtained.
  • the method of the present invention cannot cover the entire periphery of the signal line like a general coaxial cable.
  • the method of the present invention It is known that there is no problem with the shielding effect even if there is a gap in the “cover”.
  • the extension direction of the coil can be set to an arbitrary direction on the plane of the substrate, the coil can be formed in the same process in any direction as necessary.
  • a method of manufacturing the shielded wires 1 to 4 in the multilayer substrate according to the present invention will be described together with advantages as compared with the prior art.
  • the case of the shielded wire 1 in a multi-layer substrate shown in Fig. 1 (a) using a shield using a single-layer coil and using an organic material as an insulator will be described.
  • a core substrate 1d having a through-hole serving as a part of a coil and a conductor 1b serving as a signal line is prepared.
  • Materials include known and commonly used copper-clad laminates, such as glass epoxy resin and bismaleimide-triazine substrates.
  • Drilling can be performed by a widely used method such as a drill or a carbon dioxide laser or a YAG laser.
  • the conductor can be patterned by a known and commonly used method such as a subtractive method or an additive method.
  • outermost layers 1e are laminated and formed on both surfaces of the core substrate 1d as shown in FIG.
  • the same material and method as the core material can be used for the material of the insulating layer, the drilling method, and the setting method.
  • an insulating layer and a conductive layer may be formed on both sides of the inner layer material, and the patterning and electrical connection may be performed.
  • the insulating layer is formed on a substrate made of the above inner layer material.
  • the insulating layer is a prepreg such as glass epoxy or aramide resin, a liquid or film-like thermoplastic or thermosetting resin composition, or a copper foil and an insulating resin layer, which is generally called resin-coated copper foil. Can be used.
  • the formation of the insulating layer is performed, for example, as follows.
  • prepregs 5, unpatterned copper foil 6, or resin-coated copper foil 7 as shown in Fig. 4 (b) are provided on both sides of the core substrate 1d. They are arranged, and they are collectively laminated and cured by a lamination press method as shown in Fig. 5, to create an integrated insulating layer and conductive layer.
  • a liquid composition is applied onto the above 1d by a known and conventional method such as screen printing, force coating, spray coating, etc., and cured by UV, electron beam, heat, or the like.
  • a film-shaped composition is pasted on the substrate by a method such as roll or lamination, and cured by a predetermined method to obtain an insulating layer 8. Subsequently, a via is formed. Drill and drill at predetermined positions on the substrate obtained by the above method.
  • Fig. 7 (a) shows the case where the pre-preda 5 and the copper foil 6 are used as the insulating layer and the conductive layer.
  • Fig. 7 (b) shows the copper foil 7 with resin
  • Fig. 7 (c) shows the liquid or film-like thermoplastic.
  • the thermosetting resin composition 8 is used is described.
  • a conductive paste containing a conductive powder such as silver or copper in a via is used. Is embedded by printing, dispensing, etc., and cured by a predetermined method.
  • a normal through-hole plating that is, an electroless plating after applying a plating catalyst in the via, followed by an electrolytic plating, is used.
  • the electrical connection can also be achieved by the method of forming.
  • the blind via is conductively connected with the conductive paste 10 or the print layer 11 to be connected.
  • the blind via may be made conductive first.
  • a catalyst is applied to the substrate on which the insulating layer and the blind via are formed, and electroless plating is performed, and then, if necessary, electrolytic plating is performed.
  • the formation of the layer 13 and the conduction of the blind via can also be performed at once.
  • the blind via can be made conductive by using a conductive paste.
  • the insulating layer, the conductive layer, and the electrical connection can be collectively performed by the following method. That is, as shown in FIG. 9, the conductive layer is placed at a predetermined position on the inner layer circuit 1d. After forming conductive bumps 14 with sharp tips using a paste or the like, prepreg 5 and copper foil 6 (Fig. 9 (a)) or film-like insulator 8 and copper foil 6 (Fig. 9 (b) ) Or press processing after placing the resin-coated copper foil 7 (FIG. 9 (c)) allows the sharp conductive bumps 14 to penetrate the insulating layer and realize connection with the conductive layer.
  • through holes or blind vias may be filled with a filling or filling process for filling holes to smooth the surface.
  • a four-layer structure using a glass epoxy pre-preda as the insulating layer will be described. That is, as shown in FIG. 10, a predetermined position on the base material 15 side of the copper-clad single-sided glass epoxy substrate is punched using a laser or the like. Subsequently, electric plating is performed using the copper foil 16 as an electrode, and the resulting hole is filled with the plating 17. Then, a low melting point metal bump 18 is continuously formed by the plating method.
  • the copper foil 16 is etched into a predetermined pattern as shown in FIG.
  • the conductor portion of the external conductor parallel to the multilayer substrate is used as the conductor strip (in the case of the shield wire 4 in the multilayer substrate)
  • this etching is not necessary.
  • the same composition 19 as that used for the insulating layer is thinly applied to the bump side and semi-cured.
  • the one manufactured from this single-sided substrate is the outermost layer, that is, the first and fourth layers.
  • the inner layer 1 d and the outermost layer of FIG. 11 are aligned, and the composition that has been semi-hardened by pressing is removed from the bump portion, and the insulation between the layers is removed.
  • the bump portion is electrically connected to the conductor of the inner layer, and a multilayer anti-inner shield line 1 in which a signal line is disposed through a coil having a four-layer structure is manufactured.
  • the shield wire 3 in the multilayer substrate can also be easily manufactured.
  • an electronic circuit element including the structure of the shield wires 1 to 4 in the multilayer substrate of the present invention can be easily manufactured. it can.
  • the shielded wire of the present invention can be formed by sequentially performing a method of forming a hole in a green sheet, filling a hole with a conductive paste, printing a pattern, laminating, and firing, which are conventional methods.
  • the process of simultaneously forming a coil or an external conductor and a conductor having a central axis in a direction parallel to the substrate plane on a semiconductor substrate will be described below.
  • the number of evenings, the number of columns (layers), the direction of formation, etc. can be set arbitrarily.
  • a lowermost insulating layer 21 is formed on a silicon wafer 20 on which transistors and electrode portions are formed.
  • the silicon oxide film can be formed using a vapor phase method such as CVD, or by spin coating an organic material such as polyimide or benzocyclobutene, which has recently attracted attention, and then performing a post-baking process. Subsequently, as shown in FIG. 14, necessary holes 22 are formed using various lasers. The hole 22 is where electrical connection with the lower electrode portion is made. Then, as shown in Figure 15 Thus, the conductive pattern 23 is formed.
  • a commonly used method is aluminum sputtering, or a copper layer is formed by a vapor phase method such as CVD or a wet method such as a plating method. Then, patterning is performed by exposing and etching. In this case, the conductive layer may be formed after the patterned resist layer is formed.
  • the hole 22 drilled in the step shown in FIG. 14 is also electrically conductive, and the first layer and the second layer are electrically connected.
  • the surface is usually flattened by physical polishing or a combination of chemical polishing and physical polishing called a CMP method.
  • a second insulating layer 24 is formed.
  • a hole is formed again, and a conductive pattern 25 of the second layer is formed by forming a conductive pattern.
  • a conductive wire can be formed at the same time.
  • a third insulating layer 26 is formed by the above-described method, a hole is formed, the conductive layer is patterned, a third conductive pattern 27 is formed, and the second layer and the third layer are formed. Take continuity of the layers. At this stage, the following can be formed on the semiconductor as shown in FIG. By applying this operation, it is possible to easily increase or decrease the number of evenings, increase or decrease the number of rows (layers), or form multiple shield wires having different extending directions.
  • a structure generally called a stacked via that is, a structure having a via hole can be formed again on a filled via hole, and the side of the coil can be made straight.
  • the silicon wafer 20 and the multilayer substrate including the shield line are separated into semiconductor chip units.
  • the silicon wafer 20 Before laminating a multilayer substrate incorporating a shield wire on silicon wafer 20 Alternatively, the silicon wafer 20 can be cut into chips. In this case, a multilayer substrate having a built-in shield line may be laminated on the outer surface of the semiconductor chip cut in advance in the same manner as the above process.
  • a stacked via structure cannot be formed by a commonly used method, that is, a method in which a via hole is not filled with a conductor. At that time, the manufactured coil has a cross-section in which the via-hole connection portion is stepped, as shown in FIG. Such a structure has no practical effect on the shielding effect.
  • the structure manufactured by the method of the present invention has a structure in which the signal line is covered with a coil or an external conductor formed at the same time. The effect increases.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A small shielding wire in a multilayer board insusceptible to noise, and its producing method. The shielding wire in a multilayer board which is a coil being formed integrally with the multilayer board and characterized by having a coil including a winding part parallel with the multilayer board and a winding part perpendicular to the multilayer board, and a conductor formed in that coil integrally with the multilayer board.

Description

明細書  Specification
多層基板内シールド線、 半導体チップ、 電子回路素子、 及びそれらの製造方法  Shield wire in multilayer substrate, semiconductor chip, electronic circuit element, and manufacturing method thereof
(技術分野） (Technical field)
本発明は、 シールド線に関し、 より詳しくは、 多層基板内に形成されるシール ド線、 及び当該多層基板が積層された電子回路素子及び半導体チップに関する。  The present invention relates to a shield line, and more particularly, to a shield line formed in a multilayer substrate, and an electronic circuit element and a semiconductor chip on which the multilayer substrate is laminated.
(背景技術）  (Background technology)
近年、 パソコン、 携帯電話など、 高周波を利用した電気機器が広く使用されて いる。 また、 これらの機器ではいわゆる軽薄短小化が進み、 使用される半導体パ ヅケージ ¾反を含むプリント基板、 I C；、 電子部品は小型化が急速に進行してい る。 この傾向に伴い、 これらの基板、 I C、 電子部品は導体同士が非常に接近す る構造になっている。 また、 各素子が非常に接近して配置されるようになってき ている。  In recent years, high-frequency electrical devices such as personal computers and mobile phones have been widely used. In addition, in these devices, so-called lighter and thinner and smaller, the printed circuit boards, ICs, and electronic components, including semiconductor packages used, are being rapidly reduced in size. With this trend, these substrates, ICs, and electronic components have structures in which conductors are very close to each other. In addition, each element is being arranged very close.
そのため、 例えば、 信号ライン近傍に電磁波を発生する機器あるいは素子があ る場合、 ある一定以上のノィズレベルに達すると信号が乱れて誤動作が生じるこ とがある。近年この問題は多発しており、 対応が急がれている。現状は素子の配 置の最適化や全体のシールドなどで対応されている。  Therefore, for example, if there is a device or element that generates electromagnetic waves near the signal line, if the noise level reaches a certain level or more, the signal may be disturbed and malfunction may occur. In recent years, this problem has occurred frequently, and the response is urgent. At present, this is handled by optimizing the arrangement of elements and shielding the entire system.
しかしながら、 素子の配置の最適ィ匕は基本的には試行錯誤を繰り返すしかなく、 効率が非常に悪い。 シールドに関しては、 機器あるいは素子全体を銅板あるいは 銅を主成分とするペーストの硬ィ匕物で覆うことも行われている。 しかし、 このよ うな機器全体を覆う方法では、 機器内部で発生するノイズには効果が得られず、 素子を覆う方法では高密度な実装が困難になるなど問題が多い。 更に、 近年一般 化した多層基板では、 基板の内部にも電磁波の発生源があり、 上記の外部シール ドでは対応できない。 高周波回路ではこれまで、 ノイズ回避のため、 後述する同軸ケーブル状の構造、 すなわち基板の内層の信号伝送に用いられるストリップラインの上下を、 広い面 積、 理想的には無限大の面積を有する GND面で挟み込まれた構造が広く用いら れてきた。 しかしながら、 この構造は近年の小型ィ匕した機器に用いるには広い面 積が必要であり、 不都合な点が多い。 However, the optimal arrangement of the elements is basically a matter of trial and error and is very inefficient. As for the shield, it is also practiced to cover the entire device or element with a copper plate or a paste made of copper as a main component. However, such a method of covering the entire device has no effect on the noise generated inside the device, and the method of covering the elements has many problems such as difficulty in high-density mounting. Furthermore, in a multi-layer substrate that has been generalized in recent years, there are sources of electromagnetic waves inside the substrate, and the above-mentioned external shield cannot cope with it. In high-frequency circuits, to avoid noise, a coaxial cable-like structure described later, that is, a GND with a large area, ideally an infinite area above and below a strip line used for signal transmission on the inner layer of the board Structures sandwiched between surfaces have been widely used. However, this structure requires a large area for use in recent small-sized devices, and has many disadvantages.
基板平面と垂直方向に回路面を持つ多層コイルおよびその製造方法は、 例えば チップインダク夕として好適なものとして、 特開平 1 1— 2 5 1 1 4 6号公報な どに複数開示されている。 しかしながら、 これらの方法には、 X反と平行な平面 に配線される信号ラインと、 該信号ラインへの外部の電磁気ノイズの影響を少な くするために、 基板平面と垂直な方向にコイルを形成する方法に関しては全く記 載がない。 すなわち、 コイルの内部を別の回路が貫通するような構造に関しての 言及は全くない。  A plurality of multilayer coils having a circuit surface in a direction perpendicular to the plane of the substrate and a method of manufacturing the same are disclosed in, for example, Japanese Patent Application Laid-Open No. H11-251146, which is suitable as a chip inductor. However, in these methods, a coil is formed in a direction perpendicular to the plane of the substrate in order to reduce the influence of external electromagnetic noise on the signal line wired in a plane parallel to the X direction. There is no mention of how to do this. That is, there is no mention of a structure in which another circuit passes through the inside of the coil.
また、 I C用として、 特開平 1 1—2 1 4 6 2 2号公報には、 多重ソレノィド コイルを半導体基板の周囲に形成する方法が開示されている。 この方法は、 より 大きなインダク夕を得るための発明であるが、 同時にその内部素子のノイズ回避 にも有効である。 しかしながら、 この方法ではコイル部分に非常に多くの体積を 使用せざるを得ないため、 小型ィ匕の観点から非常に問題がある。 また、 前記チッ ブインダク夕の場合と同様、 コイルの内部を別の回路が貫通する構造についての 言及はない。  Japanese Patent Application Laid-Open No. H11-1-26462 discloses a method for forming multiple solenoid coils around a semiconductor substrate for use in ICs. This method is an invention for obtaining a larger inductance, but it is also effective for avoiding noise of its internal elements. However, in this method, a very large volume has to be used for the coil portion, which is very problematic in terms of miniaturization. Further, as in the case of the chip induction, there is no mention of a structure in which another circuit passes through the inside of the coil.
信号ラインのように、 重要な情報を伝達する回路をノィズから保護するために は、 その周囲を導体で覆うことが最も有効である。 そのようなものには、 前述の ストリップライン以外に、 同軸ケーブルがある。例えばテレビアンテナから受像 器に接続する信号線は、 その周囲が銅で被覆され、 外部からのノイズの影響を少 なくしている。 同軸ケーブルは、 ストリヅプラインと異なって、 広い面積の GN D面は必要としない。従って、 そのような同軸ケーブルに類似した構造からなる シ一ルド線を、 多層基板 （プリント基板） 内に形成することができれば、 効果的 なノイズの遮蔽と小型化とを両立することができると考えられる。 また、 そのよ うな多層基板を半導体チップ （i c)、 電子回路素子に積層させることにより、 信号ラインにそのような小型のシールド線を使用した半導体チップ （i c)、 電 子回路素子を作成することができると考えられる。 ここで、 シールド線の外部導 体に、 コイル状の導体、 かご状の導体、 導体ストリップなどを使用した小型のシ —ルド線が考えられるが、 そのような構造のシールド線は、 従来、 存在しなかつ た。 To protect circuits that transmit important information, such as signal lines, from noise, it is most effective to cover them with conductors. Such include coaxial cables in addition to the stripline described above. For example, the signal line connected from the TV antenna to the receiver is covered with copper to reduce the effects of external noise. Coaxial cables, unlike strip lines, do not require a large area GND surface. Therefore, it has a structure similar to such a coaxial cable If shield lines can be formed in a multilayer board (printed circuit board), it would be possible to achieve both effective noise shielding and miniaturization. In addition, by stacking such a multilayer substrate on a semiconductor chip (ic) and an electronic circuit element, a semiconductor chip (ic) and an electronic circuit element using such a small shielded line for a signal line can be produced. It is thought that it is possible. Here, a small shielded wire that uses a coil-shaped conductor, a cage-shaped conductor, or a conductor strip as the outer conductor of the shielded wire can be considered. I didn't.
本発明は、 省スペースで、 高周波領域において重要な信号ラインを電磁波から 遮蔽できる多層基板内シールド線、 およびその製造方法を提供することを課題と している。  An object of the present invention is to provide a shielded wire in a multilayer substrate which can save important signal lines in a high-frequency region from electromagnetic waves in a small space, and a method of manufacturing the same.
(発明の開示）  (Disclosure of the Invention)
本発明によれば、 上記課題は、 次の手段により達成できる。 請求の範囲第 1項 に記載の発明は、 多層基板と一体的に形成されるコイルであって、 当該多層基板 に平行な巻線部分及び当該多層基板に垂直な卷線部分を含むコィルと、 前記多層 基板と一体的に形成される導線であって、 前記コイルの内部に形成される導線と、 を有することを特徴とする。  According to the present invention, the above object can be achieved by the following means. The invention according to claim 1 is a coil formed integrally with the multilayer substrate, wherein the coil includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. And a conductive wire formed integrally with the multilayer substrate, wherein the conductive wire is formed inside the coil.
請求の範囲第 2項に記載の発明は、 前記コイルの単位巻線は、 隣接する他の単 位卷線と同じ方向から見た場合に互いに反対方向に旋回する螺旋状のパターンを それそれ有し、 及び前記コイルの互いに隣接する単位卷線の組は、 当該螺旋状の パターンの先端同士又は末端同士において交互に接続されることを特徴とする。 請求の範囲第 3項に記載の発明は、 請求の範囲第 1又は 2項に記載の発明の特 徴に加えて、 前記コイルは、 前記多層基板に平行な卷線部分が、 積層された導電 層の一部として形成され、 前記多層基板に垂直な卷線部分が、 前記絶縁層を介し て隣接する前記導電層間を接続するバンプとして形成されることを特徴とする。 請求の範囲第 4項に記載の発明は、 請求の範囲第 1又は 2項に記載の発明の特 徴に加えて、 前記コイルは、 ビルドアップ工法により、 前記多層基板に平行な卷 線部分が、 積層された導電層の一部として形成され、 前記多層基板に垂直な巻線 部分が、 前記絶縁層を通して隣接する前記導電層間を接続するビア或いはスルー ホールとして形成されることを特徴とする。 The invention according to claim 2 is characterized in that the unit winding of the coil has a spiral pattern that turns in opposite directions when viewed from the same direction as another adjacent unit winding. And a set of unit windings adjacent to each other of the coil are connected alternately at the tips or ends of the spiral pattern. The invention described in claim 3 has the feature that, in addition to the features of the invention described in claim 1 or 2, the coil has a conductive part in which winding portions parallel to the multilayer substrate are laminated. A winding part formed as a part of a layer and perpendicular to the multilayer substrate is formed as a bump connecting the adjacent conductive layers via the insulating layer. The invention described in claim 4 has the feature that, in addition to the features of the invention described in claim 1 or 2, the coil has a winding portion parallel to the multilayer substrate by a build-up method. And a winding portion formed as a part of the stacked conductive layers and perpendicular to the multilayer substrate is formed as a via or a through hole connecting the adjacent conductive layers through the insulating layer.
請求の範囲第 5項に記載の発明は、 多層基板と一体的に形成される外部導体で あって、 当該多層基板に平行な導体部分及び当該多層基板に垂直な導体部分を含 む外部導体と、 前記多層基板と一体的に形成される導線であって、 前記外部導体 の内部に形成される導線と、 を有することを特徴とする。  The invention described in claim 5 is an external conductor formed integrally with the multilayer substrate, the external conductor including a conductor portion parallel to the multilayer substrate and a conductor portion perpendicular to the multilayer substrate. And a conductive wire formed integrally with the multilayer substrate, wherein the conductive wire is formed inside the outer conductor.
請求の範囲第 6項に記載の発明は、 請求の範囲第 5項に記載の発明の特徴に加 えて、 前記外部導体は、 前記多層基板に平行な導体部分が導体ストリップである ことを特徴とする。  The invention described in claim 6 is characterized in that, in addition to the features of the invention described in claim 5, the outer conductor is such that a conductor portion parallel to the multilayer substrate is a conductor strip. I do.
請求の範囲第 7項に記載の発明は、 請求の範囲第 5又は 6項に記載の発明の特 徴に加えて、 前記外部導体は、 前記多層基板に平行な導体部分が、 積層された導 電層の一部として形成され、 前記多層雄反に垂直な導体部分が、 前記絶縁層を介 して隣接する前記導電層間を接続するバンプとして形成されることを特徴とする。 請求の範囲第 8項に記載の発明は、 請求の範囲第 5又は 6項に記載の発明の特 徴に加えて、 前記外部導体は、 ビフレドアップ工法により、 前記多層基板に平行な 導体部分が、 積層された導電層の一部として形成され、 前記多層基板に垂直な導 体部分が、 前記絶縁層を通して隣接する前記導電層間を接続するビア或いはスル 一ホールとして形成されることを特徴とする。  The invention according to claim 7 is the invention according to claim 5 or 6, wherein the outer conductor is a conductor in which a conductor portion parallel to the multilayer substrate is laminated. A conductor portion formed as a part of an electric layer and perpendicular to the multilayered layer is formed as a bump connecting the adjacent conductive layers via the insulating layer. The invention according to claim 8 has the feature that, in addition to the features of the invention according to claim 5 or 6, the outer conductor has a conductor portion parallel to the multilayer substrate by a bifured-up method. A conductor portion formed as a part of the stacked conductive layers and perpendicular to the multi-layer substrate, formed as a via or a single hole connecting the adjacent conductive layers through the insulating layer. .
請求の範囲第 9項に記載の発明の特徴は、 請求の範囲第 1乃至 8項のいずれか 1項に記載の多層 S反内シールド線を含む多層 ¾反が外面に積層されたことを特 徴とする。  A feature of the invention set forth in claim 9 is that the multilayer steel sheet including the multilayer S anti-inner shield wire according to any one of claims 1 to 8 is laminated on an outer surface. Sign.
請求の範囲第 1 0項に記載の発明は、 請求の範囲第 1乃至 8項のいずれか 1項 に記載の多層基板内シールド線を含む多層基板上に搭載されたことを特徴とする。 請求の範囲第 1 1項に記載の発明は、 多層基板を構成する 1つの絶縁層を形成 するステップと、 前記多層 ¾ί反に平行なコイルの卷線部分の少なくとも一部を前 記多層基板内の絶縁層上に形成するステップと、 導線を、 前記コイルの内側に当 該コイルと前記絶縁層を介在させて形成するステップと、 前記多層基板に平行な コイルの前記巻線部分の少なくとも一部同士を絶縁層間で電気的に接続する垂直 接続部を形成し、 それによつて前記多層基板に垂直なコイルの巻線部分の少なく とも一部を形成するステップと、 絶縁層を形成する前記ステップ、 前記多層基板 に平行なコイルの卷線部分の少なくとも一部を形成する前記ステップ、 及び前記 多層基板に垂直なコイルの卷線部分の少なくとも一部を形成する前記ステヅプの 少なくともいずれかを、 前記多層基板に平行なコイルの巻線部分と前記多層基板 に垂直なコィルの卷線部分とで前記多層基板内に支持される所定のコィルが形成 されるまで、 それまでに形成された多層基板の部分に対して適宜反復するステヅ プと、 を具備することを特徴とする。 The invention described in claim 10 is any one of claims 1 to 8 And mounted on the multilayer substrate including the shielded wire in the multilayer substrate described in (1). The invention according to claim 11 includes a step of forming one insulating layer constituting a multilayer substrate; and forming at least a part of a winding portion of a coil parallel to the multilayer substrate in the multilayer substrate. Forming a conductive wire inside the coil with the coil and the insulating layer interposed therebetween; and at least a part of the winding portion of the coil parallel to the multilayer substrate. Forming a vertical connection portion for electrically connecting them to each other between the insulating layers, thereby forming at least a part of a winding portion of a coil perpendicular to the multilayer substrate; and forming the insulating layer. Forming at least a portion of a coil winding portion parallel to the multilayer substrate; and at least a step of forming at least a portion of a coil winding portion perpendicular to the multilayer substrate. Either one is formed until a predetermined coil supported in the multilayer substrate is formed by the winding portion of the coil parallel to the multilayer substrate and the winding portion of the coil perpendicular to the multilayer substrate. And a step of appropriately repeating the portion of the multi-layer substrate thus obtained.
請求の範囲第 1 2項に記載の発明は、 請求の範囲第 1 1項に記載の発明の特徴 に加えて、 前記所定のコイルの単位卷線は、 隣接する他の単位卷線と同じ方向か ら見た場合に互いに反対方向に旋回する螺旋状のパターンをそれそれ有し、 及び 前記所定のコイルの互いに隣接する単位卷線の組は、 前記螺旋状のパターンの先 端同士又は末端同士において交互に接続されることを特徴とする。  The invention described in claim 12 is characterized in that, in addition to the features of the invention described in claim 11, the unit winding of the predetermined coil is in the same direction as another adjacent unit winding. Each of which has a spiral pattern that turns in the opposite direction when viewed from above, and sets of unit windings adjacent to each other of the predetermined coil are formed at the leading ends or the trailing ends of the spiral pattern. Are connected alternately.
請求の範囲第 1 3項に記載の発明は、 多層基板を構成する 1つの絶縁層を形成 するステップと、 前記多層 に平行な外部導体の導体部分の少なくとも一部を 前記多層基板内の絶縁層上に形成するステップと、 導線を、 前記外部導体の内側 に当該外部導体と前記絶縁層を介在させて形成するステヅプと、 前記多層 ¾反に 平行な外部導体の前記導体部分の少なくとも一部同士を絶縁層間で電気的に接続 する垂直接続部を形成し、 それによつて前記多層基板に垂直な外部導体の導体部 分の少なくとも一部を形成するステップと、 絶縁層を形成する前記ステップ、 前 記多層基板に平行な外部導体の導体部分の少なくとも一部を形成する前記ステヅ プヽ 及び前記多層基板に垂直な外部導体の導体部分の少なくとも一部を形成する 前記ステップの少なくともいずれかを、 前記多層基板に平行な外部導体の導体部 分と前記多層基板に垂直な外部導体の導体部分とで前記多層基板内に支持される 所定の外部導体が形成されるまで、 それまでに形成された多層基板の部分に対し て適宜反復するステップと、 を具備することを特徴とする。 The invention described in claim 13 is a step of forming one insulating layer constituting a multilayer substrate, and forming at least a part of a conductor portion of an external conductor parallel to the multilayer substrate with an insulating layer in the multilayer substrate. Forming a conductive wire on the inner side of the outer conductor with the outer conductor and the insulating layer interposed therebetween; and at least a part of the conductor portions of the outer conductor parallel to the multilayer structure. A vertical connection portion for electrically connecting the outer conductor between the insulating layers, thereby forming a conductor portion of the outer conductor perpendicular to the multilayer substrate. Forming at least a portion of the external conductor, forming the insulating layer, forming the insulating layer, forming the at least part of the conductor portion of the external conductor parallel to the multilayer substrate, and forming the external portion perpendicular to the multilayer substrate. Forming at least a part of the conductor portion of the conductor, at least one of the steps is performed in the multilayer substrate by the conductor portion of the external conductor parallel to the multilayer substrate and the conductor portion of the external conductor perpendicular to the multilayer substrate. Until a predetermined external conductor to be supported is formed, and appropriately repeating the portion of the multilayer substrate formed so far.
請求の範囲第 1 4項に記載の発明は、 請求の範囲第 1 3項に記載の発明の特徴 に加えて、 前記外部導体の多層基板に平行な導体部分は、 導体ストリップである ことを特徴とする。  The invention described in claim 14 is characterized in that, in addition to the features of the invention described in claim 13, the conductor portion of the external conductor parallel to the multilayer substrate is a conductor strip. And
請求の範囲第 1 5項に記載の発明は、 請求の範囲第 1 1乃至 1 4項のいずれか 1項に記載の発明の特徴に加えて、 前記多層基板内シールド線は半導体ゥェ一ハ の外面に積層されるものであり、 前記多層基板内シールド線が積層された前記半 導体ゥェ一ハを半導体チヅプ単位に切り分けるステツプ、 を更に有することを特 ®とする。  The invention according to claim 15 is characterized in that, in addition to the features of the invention described in any one of claims 11 to 14, the shielded wire in the multilayer substrate is a semiconductor wafer. And a step of cutting the semiconductor wafer, on which the shield wires in the multilayer substrate are stacked, into semiconductor chip units.
請求の範囲第 1 6項に記載の発明は、 請求の範囲第 1 1乃至 1 4項のいずれか 1項に記載の発明の特徴に加えて、 前記多層基板内シールド線は半導体チヅプの 外面に積層されることを特徴とする。  The invention according to claim 16 is characterized in that, in addition to the features of the invention described in any one of claims 11 to 14, the shield wire in the multilayer substrate is provided on an outer surface of the semiconductor chip. It is characterized by being laminated.
請求の範囲第 1 7項に記載の発明は、 請求の範囲第 1 1乃至 1 4項のいずれか 1項に記載の発明の特徴に加えて、 前記多層基板内シールド線を含む多層基板の 上に電子回路素子が搭載されることを特徴とする。  The invention according to claim 17 is characterized in that, in addition to the features of the invention according to any one of claims 11 to 14, An electronic circuit element is mounted on the electronic device.
(図面の簡単な説明）  (Brief description of drawings)
図 1 ( a) は、 本発明の第 1の実施形態に係る多層基板内シールド線 1の概略 構成を示す斜視図であり、 図 1 ( b ) は、 本発明の第 2の実施形態に係る多層基 板内シールド線 2の概略構成を示す斜視図であり、 図 1 ( c ) は、 本発明の第 3 の実施形態に係る多層基板内シールド線 3の概略構成を示す斜視図であり、 図 1 ( d ) は、 本発明の第 4の実施形態に係る多層基板内シールド線 4の概略構成を 示す斜視図であり、 図 1 ( e ) 及び図 1 (： f ) は、 他のコイルの構造の例を示す 図である。 FIG. 1A is a perspective view showing a schematic configuration of a shield wire 1 in a multilayer substrate according to a first embodiment of the present invention, and FIG. 1B is a perspective view showing a structure according to a second embodiment of the present invention. FIG. 1 is a perspective view showing a schematic configuration of a shielded wire 2 in a multilayer board, and FIG. FIG. 1D is a perspective view showing a schematic configuration of a shield wire 3 in a multilayer substrate according to the embodiment, and FIG. 1D is a perspective view showing a schematic configuration of a shield wire 4 in the multilayer substrate according to a fourth embodiment of the present invention. Fig. 1 (e) and Fig. 1 (: f) are diagrams showing examples of the structure of another coil.
図 2は、 多層基板内シールド線 4の製造初期段階の斜視概念図である。 図 3は、 多層基板内シールド線 4の製法の一例を示す斜視概念図である。 図 4は、 多層基板内シールド線 1 ' の製法の一例を示す斜視概念図である。 図 5は、 多層基板内シールド線 1 - 4の製法の一例を示す斜視概念図である。 図 6は、 多層基板内シールド線 4の製法の一例を示す斜視概念図である。 図 7は、 多層基板内シールド線 4の製法の一例を示す斜視概念図である。 図 8は、 多層基板内シールド線 1 ' 4の製法の一例を示す斜視概念図である。 図 9は、 多層基板内シールド線 1 - 4の製法の一例を示す斜視概念図である。 図 1 0は、 多層基板内シールド線 〜 4の製法の一例を示す斜視概念図である。 図 1 1は、 多層基板内シールド線 〜 4の製法の一例を示す斜視概念図である。 図 1 2は、 多層基板内シールド線 〜 4の製法の一例を示す斜視概念図である。 図 1 3は、 多層基板内シールド線 〜 4を半導体ゥェ一ハ上に形成する場合の 製造初期の断面図である。  FIG. 2 is a schematic perspective view of an initial stage of manufacturing the shield wire 4 in the multilayer substrate. FIG. 3 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 4 in the multilayer substrate. FIG. 4 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 1 ′ in the multilayer substrate. FIG. 5 is a conceptual perspective view showing an example of a method of manufacturing the shield wires 1-4 in the multilayer substrate. FIG. 6 is a conceptual perspective view showing an example of a method for manufacturing the shield wire 4 in the multilayer substrate. FIG. 7 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 4 in the multilayer substrate. FIG. 8 is a conceptual perspective view showing an example of a method of manufacturing the shield wire 1'4 in the multilayer substrate. FIG. 9 is a schematic perspective view showing an example of a method for manufacturing the shield wires 1-4 in the multilayer substrate. FIG. 10 is a conceptual perspective view showing an example of a method for producing the shield wires 4 in the multilayer substrate. FIG. 11 is a conceptual perspective view showing an example of a method of manufacturing the shield wires 4 in the multilayer substrate. FIG. 12 is a perspective conceptual view showing an example of a method of manufacturing the shield wires 4 in the multilayer substrate. FIG. 13 is a cross-sectional view of the initial stage of manufacturing when the shield wires 4 in the multilayer substrate are formed on the semiconductor wafer.
図 1 4は、 ビア形成の説明のための断面図である。  FIG. 14 is a cross-sectional view for explaining via formation.
図 1 5は、 回路形成のための導電パ夕一ン形成の説明のための断面図である。 図 1 6は、 第 2の絶縁層形成の説明のための断面図である。  FIG. 15 is a cross-sectional view for explaining formation of a conductive pattern for forming a circuit. FIG. 16 is a cross-sectional view for explaining the formation of the second insulating layer.
図 1 7は、 第 2の導電パターン形成の説明ための断面図である。  FIG. 17 is a cross-sectional view for explaining the formation of the second conductive pattern.
図 1 8は、 半導体ゥェ一ハ上に形成された多層基板内シ一ルド線の断面概念図 である。  FIG. 18 is a conceptual cross-sectional view of a shield line in a multilayer substrate formed on a semiconductor wafer.
図 1 9は、 ビアの断面概念図である。  FIG. 19 is a conceptual cross-sectional view of a via.
図 2 0は、 半導体ゥエーハ上に形成された多層基板内シールド線の一例を示す 断面概念図である。 FIG. 20 shows an example of a shield line in a multilayer substrate formed on a semiconductor wafer. It is sectional conceptual drawing.
図 2 1は、 半導体ゥヱーハ上に形成された多層基板内シールド線の一例を示す 断面概念図である。  FIG. 21 is a conceptual sectional view showing an example of a shield line in a multilayer substrate formed on a semiconductor wafer.
(発明を実施するための最良の形態）  (Best mode for carrying out the invention)
以下、 本発明の実施の形態について、 図面を参照しながら説明していく。 これ から本発明の第 1の実施形態に係る多層基板内シールド線 1の構成について説明 する。 図 1 ( a ) は、 多層基板内シ一ルド線 1の概略構成を示す斜視図である。 多層基板内シールド線 1は、 コイル l a、 導線 l b、 及び多層基板 l cから構成 される。 コイル l aは、 多層基板における複数の絶縁層及び導電層のそれそれの 形成ステップにおいて導電層の一部として形成される、 シールド線の外部導体と して機能する構成要素である。 コイル l aは、 中心軸が多層基板に平行であり、 多層基板に平行な卷線部分及び当該多層基板に垂直な巻線部分を含む。 コイル 1 aは、 好適には、 断面形状が四角形、 円形等の導線の繰り返されるパターンであ る単位卷線が、 電気的に直列に連続して接続された形態で構成される。 本明細書 におけるコイル 1 a及びそれの単位卷線の形態は、 シールド線の外部導体として 機能するためのいかなる形態も広く含むものとする。好適には、 コイル l aの多 層基板に平行な巻線部分は、 積層される導電層の一部として形成され、 多層基板 に垂直な卷線部分は、 絶縁層を介して隣接する導電層間を接続するバンプ、 ビア 或いはスルーホールなどとして形成される。 このようにしてコイル 1 aを形成す ることにより、 ビルドアヅプ工法などの公知の多層基板 （プリント基板） 製造技 術を利用して、 多層基板の製造工程においてコイル 1 aを多層基板内に同時に形 成することが可能となる。 導線 l bは、 多層基板の製造工程において、 コイル 1 aの内部にコイル 1 aと絶縁層を介在させて形成される。 多層 l cは、 絶縁 層を積層させて構成される基板である。 なお、 実際の多層基板 1 cの形成ステツ プでは、 絶縁層と導電層とが交互に積層させられる。 そして、 導電層の部分は前 述のコイル 1 aの一部となり、 他の絶縁層の部分は多層基板 1 cとなる。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. Hereinafter, the configuration of the shield wire 1 in the multilayer substrate according to the first embodiment of the present invention will be described. FIG. 1A is a perspective view showing a schematic configuration of a shield line 1 in a multilayer substrate. The shielded wire 1 in the multilayer board is composed of a coil la, a conductor lb, and a multilayer board lc. The coil la is a component that functions as an outer conductor of the shielded wire, which is formed as a part of the conductive layer in each step of forming a plurality of insulating layers and conductive layers in the multilayer substrate. The coil la has a central axis parallel to the multilayer substrate, and includes a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate. The coil 1a is preferably formed in a form in which unit windings having a repeating pattern of conducting wires having a rectangular or circular cross section are electrically and continuously connected in series. The form of the coil 1a and its unit winding in the present specification widely includes any form that functions as an outer conductor of the shielded wire. Preferably, the winding portion of the coil la parallel to the multilayer substrate is formed as a part of the conductive layer to be laminated, and the winding portion perpendicular to the multilayer substrate is formed between the adjacent conductive layers via the insulating layer. It is formed as a connecting bump, via, or through hole. By forming the coil 1a in this manner, the coil 1a is simultaneously formed in the multilayer substrate in a multilayer substrate manufacturing process using a known multilayer substrate (printed circuit board) manufacturing technique such as a build-up method. Can be achieved. The conducting wire lb is formed inside the coil 1a with the coil 1a and the insulating layer interposed in the manufacturing process of the multilayer board. The multilayer lc is a substrate configured by laminating insulating layers. In the actual step of forming the multilayer substrate 1c, insulating layers and conductive layers are alternately laminated. And the conductive layer part is in front It becomes a part of the coil 1a described above, and the other insulating layer part becomes the multilayer substrate 1c.
次に、 本発明の第 2の実施形態に係る多層基板内シールド線 2の構成について 説明する。 図 1 ( b ) は、 多層基板内シ一ルド線 2の概略構成を示す斜視図であ る。 多層 内シールド線 2は、 コイル 2 a、 導線 2 b、 及び多層基板 2 cから 構成される。 コイル 2 aの単位巻線は、 隣接する他の単位卷線と同じ方向から見 た場合に反対方向に旋回する螺旋状のパターンをそれそれ有し、 及び互いに隣接 する単位卷線同士は、 当該螺旋状のパターンの先端同士又は末端同士において互 いに接続される。 コイル 2 aをそのように構成することによって、 単位卷線内の 卷数を 1より大きくすることができ、 より大きいシールド効果を得ることができ る。 導線 2 b及び多層基板 2 cは、 第 1の実施形態と同様の構成要素である。 次に、 本発明の第 3の実施形態に係る多層基板内シールド線 3の構成について 説明する。 図 1 ( c ) は、 多層基板内シールド線 3の概略構成を示す斜視図であ る。 多層基板内シ一ルド線 3は、 外部導体 3 a、 導線 3 b、 及び多層基板 3 cか ら構成される。 外部導体 3 aは、 多層基板 3 cに平行な導体部分及び当該多層基 板に垂直な導体部分を含む。 その導体部分は、 ストリップ状でも線状であっても よい。 図 1 ( c ) では、 線状の導体部分からなるかご形の外部導体の例を表わし ている。導線 3 b及び多層基板 3 cは、 第 1の実施形態と同様の構成要素である。 次に、 本発明の第 4の実施形態に係る多層基板内シールド線 4の構成について 説明する。 図 1 ( d ) は、 多層基板内シ一ルド線 4の概略構成を示す斜視図であ る。 多層基板内シールド線 4は、 外部導体 （多層基板 4 dに平行な平行外部導体 4 a、 及び多層基板 4 dに垂直な垂直外部導体 4 b )、 導線 4 c、 及び多層基板 4 dから構成される。 平行外部導体 4 aは、 導体ストリップである。 このように 構成することによって、 多層基板の積層工程において、 多層 *反 4 cに平行な導 体部分に微細な形状のエッチングを行う処理が不要になると共に、 線ではなく面 で遮蔽するため、 シールドの効果が高まるという利点がある。垂直外部導体 4 b は、 好適には線状の導体である。 導線 4 c及び多層基板 4 dは、 第 1の実施形態 と同様の構成要素である。 図 1 ( e ) 及び （f ) は、 他のコイルの構造の例であ る。 これらの例では、 コイルの中心軸に平行又は直交する方向の卷線部分のみで コイルが構成されている。 Next, the configuration of the shield wire 2 in the multilayer substrate according to the second embodiment of the present invention will be described. FIG. 1B is a perspective view showing a schematic configuration of the shield line 2 in the multilayer substrate. The multilayer inner shield wire 2 includes a coil 2a, a conductor 2b, and a multilayer board 2c. The unit windings of the coil 2a each have a helical pattern that turns in the opposite direction when viewed from the same direction as the other adjacent unit windings. They are connected to each other at the tips or ends of the spiral pattern. By configuring the coil 2a as such, the number of turns in a unit winding can be made larger than one, and a larger shielding effect can be obtained. The conductor 2b and the multilayer board 2c are the same components as in the first embodiment. Next, the configuration of the shield wire 3 in the multilayer substrate according to the third embodiment of the present invention will be described. FIG. 1C is a perspective view showing a schematic configuration of the shield wire 3 in the multilayer substrate. The shield wire 3 in the multilayer board is composed of an outer conductor 3a, a conductor 3b, and a multilayer board 3c. The outer conductor 3a includes a conductor portion parallel to the multilayer substrate 3c and a conductor portion perpendicular to the multilayer substrate. The conductor portion may be strip-shaped or linear. Fig. 1 (c) shows an example of a cage-shaped outer conductor consisting of linear conductors. The conductor 3b and the multilayer board 3c are the same components as in the first embodiment. Next, a configuration of the shield wire 4 in the multilayer substrate according to the fourth embodiment of the present invention will be described. FIG. 1D is a perspective view showing a schematic configuration of the shield line 4 in the multilayer substrate. The shield wire 4 in the multilayer board is composed of an outer conductor (parallel outer conductor 4a parallel to the multilayer board 4d and vertical outer conductor 4b perpendicular to the multilayer board 4d), a conductor 4c, and a multilayer board 4d. Is done. The parallel outer conductor 4a is a conductor strip. With this configuration, in the lamination process of the multi-layer substrate, it is not necessary to perform a process of etching a fine shape in the conductor portion parallel to the multi-layer * anti-4c, and to shield with a surface instead of a line, There is an advantage that the effect of the shield is enhanced. Vertical outer conductor 4 b Is preferably a linear conductor. The conductor 4c and the multilayer board 4d are the same components as in the first embodiment. Figures 1 (e) and (f) are examples of other coil structures. In these examples, the coil is constituted only by a winding portion in a direction parallel or perpendicular to the center axis of the coil.
これから多層基板内シールド線 1〜4の動作について説明する。 多層基板内シ —ルド線 1〜4は、 モノリシヅク I Cなどを構成する半導体チップをその上にマ ゥントするイン夕ポーザとして使用しても好適である。 また、 多層基板内シール ド線 1〜4は、 他の回路素子をその内部に形成又は外部にマウントすることがで き、 そのような他の回路素子と多層基板内シールド線 1〜4とで構成される回路 の機能を、 半導体チヅプ自身の機能に付加した半導体パヅケージを構成すること が可能になる。 多層基板内シールド線 1〜4は、 コイル又は外部導体の伸長方向 の調節により、 シールド線の長さを簡便且つほぼ任意に設定できる。 多層基板内 シ一ルド線 1〜4は、 内部の導線に、 ノイズの影響を受けることが好ましくない 信号などの電流を流すと好適である。 この際、 静電誘導的なノイズを遮蔽する場 合は、 コイル又は外部導体をいずれか 1点で接地するとよい。 これによつて静電 遮蔽が達成される。 また、 電磁誘導的なノイズを遮蔽する場合は、 導線に流す電 流の帰路をコィル又は外部導体とすることによって、 同軸ケーブルと同様に使用 するとよい。 これによつて、 電磁遮蔽が達成される。 また、 外部からのノイズの 影響を導線が受けないようにするだけでなく、 導線を流れる電流が周りの他の配 線、 素子などに影響を与えないようにもなる。  The operation of the shield wires 1 to 4 in the multilayer substrate will now be described. The shield lines 1 to 4 in the multilayer substrate are also suitable for use as an imposer for mounting a semiconductor chip constituting a monolithic IC or the like thereon. Also, the shielded wires 1 to 4 in the multilayer board can be formed with other circuit elements inside or mounted outside, and such other circuit elements and the shield wires 1 to 4 in the multilayer board can be used. It is possible to configure a semiconductor package in which the function of the circuit to be configured is added to the function of the semiconductor chip itself. The length of the shield wires 1 to 4 in the multilayer substrate can be easily and almost arbitrarily set by adjusting the extension direction of the coil or the external conductor. It is preferable that the shield lines 1 to 4 in the multilayer substrate are supplied with a current such as a signal which is not preferably affected by noise through the internal conductor. At this time, in order to shield static induction noise, the coil or external conductor should be grounded at one point. This achieves electrostatic shielding. When shielding electromagnetically induced noise, it is recommended to use a coil or an external conductor as the return path of the current flowing through the conductor, so that it can be used similarly to a coaxial cable. Thereby, electromagnetic shielding is achieved. In addition to preventing the conductor from being affected by external noise, it also prevents the current flowing through the conductor from affecting other surrounding wiring and elements.
本発明はこの同軸ケーブル類似の構造を、 プリント凝反、 I C、 電子機器の信 号ラインに適用するものである。 すなわち、 基板平面と平行に絶縁層の形成、 穴 開けおよび導体パターンの形成を順次行うことにより、 基板平面と平行にコイル の一部分を形成し、 これを繰り返して電気的接続をすることにより、 ¾反平面と 垂直方向に回路面を持つコイル状回路を螺旋状に形成することができる。 これら コイルの作成時に、 あわせて基板平面と平行な方向に信号ラインを形成すること により、 一括で基板平面と垂直方向および平面方向両方に回路を形成できる。 同様な構造は、 基板平面と平行な平面にコイルを形成して、 その中を貫通する 信号ラインをビアホールなどを用いて形成することもできる。 しかしながら、 信 号ラインは非常に繊細であり、 ¾反と垂直方向に非常に均一な回路を形成するこ とは困難である。 更に、 信号ラインを 平面と垂直方向のみに形成することは 事実上不可能であり、 基板平面と平行な平面に形成する必要が必ず生じる。 この 方法では基板平面と平行な平面に形成された信号ラインのシールドは不可能であ る。 In the present invention, a structure similar to the coaxial cable is applied to signal lines of print anti-collision, IC, and electronic equipment. That is, by sequentially forming an insulating layer, drilling holes, and forming a conductor pattern in parallel with the plane of the substrate, a part of the coil is formed in parallel with the plane of the substrate, and by repeating this, an electrical connection is obtained. A coil-shaped circuit having a circuit surface perpendicular to the opposite plane can be formed in a spiral shape. these By forming signal lines in the direction parallel to the substrate plane when creating the coil, circuits can be formed in the board plane and both in the vertical and planar directions. In a similar structure, a coil can be formed on a plane parallel to the substrate plane, and a signal line penetrating therethrough can be formed using a via hole or the like. However, the signal lines are very delicate and it is difficult to form a very uniform circuit in the vertical direction. Furthermore, it is practically impossible to form signal lines only in the direction perpendicular to the plane, and it is necessary to form them in a plane parallel to the substrate plane. With this method, it is impossible to shield a signal line formed on a plane parallel to the substrate plane.
また、 本発明の方法を用いれば、 所望の部分のみにコイルを簡便に得ることが できる。 これまで方法が全くなかった、 基板内部での電磁波対策も可能となる。 更に、 必要であれば、 電磁波を発生する可能性のある部位にこの方法を適用して、 該部位の外部に電磁波が漏洩しない構造とすることもできる。  Further, by using the method of the present invention, a coil can be easily obtained only at a desired portion. Until now, there has been no method at all, and countermeasures against electromagnetic waves inside the substrate are also possible. Further, if necessary, the method may be applied to a portion that may generate an electromagnetic wave, so that a structure in which the electromagnetic wave does not leak to the outside of the portion can be obtained.
この際、 本発明の方法では、 一般の同軸ケーブルのように、 信号ラインの周囲 全てを覆うことはできないが、 近年の電子 ·電気機器で主流となっている高周波 領域では本発明の方法、 すなわち 「覆い」 に隙間がある構造でもシールド効果に 題がないことが知られている。 更に、 本発明の方法では、 コイルの伸長方向を 基板平面の任意の方向に設定できるため、 必要に応じてどの方向にも同一プロセ スでコイルを形成することが可能である。  At this time, the method of the present invention cannot cover the entire periphery of the signal line like a general coaxial cable. However, in the high frequency region that has become mainstream in recent electronic and electric devices, the method of the present invention, It is known that there is no problem with the shielding effect even if there is a gap in the “cover”. Further, in the method of the present invention, since the extension direction of the coil can be set to an arbitrary direction on the plane of the substrate, the coil can be formed in the same process in any direction as necessary.
次に、 本発明の多層基板内シールド線 1〜 4の製造方法について、 従来技術と 比較した利点と共に説明する。 図 1 ( a) に示した、 単層コイルを用いたシール ドを有機材料を絶縁体として用いた多層基板内シールド線 1の場合につき説明す る。 まず、 図 2に示すような、 コイルの一部となるスルーホールと、 信号ライン となる導体 1 bが形成されたコア基板 1 dを用意する。材料としては公知慣用の 銅張積層板、 例えばガラスエポキシ樹脂、 ビスマレイミド一トリアジン基板ある いは、 誘電特性に優れたポリフエ二レンェ一テル樹脂、 ポリエ一テルエ一テルケ トン横 ¾旨、 ベンゾシクロブテン樹脂などを用いた が使用できる。 穴あけはド リルあるいは炭酸ガスレーザーや Y A Gレーザーなどの広く用いられている方法 で行うことができる。 導体のパ夕一ニングは、 サブトラクティブ法、 アディティ ブ法など、 公知慣用の方法で行うことができる。 Next, a method of manufacturing the shielded wires 1 to 4 in the multilayer substrate according to the present invention will be described together with advantages as compared with the prior art. The case of the shielded wire 1 in a multi-layer substrate shown in Fig. 1 (a) using a shield using a single-layer coil and using an organic material as an insulator will be described. First, as shown in FIG. 2, a core substrate 1d having a through-hole serving as a part of a coil and a conductor 1b serving as a signal line is prepared. Materials include known and commonly used copper-clad laminates, such as glass epoxy resin and bismaleimide-triazine substrates. Alternatively, a material using a polyphenylene ether resin having excellent dielectric properties, a polyester ether terketone, a benzocyclobutene resin, or the like can be used. Drilling can be performed by a widely used method such as a drill or a carbon dioxide laser or a YAG laser. The conductor can be patterned by a known and commonly used method such as a subtractive method or an additive method.
続いて、 コア基板 1 dの両面に最外層 1 eを図 3のように積層 '形成する。 絶 縁層の材料、 穴開け方法、 ノ 夕一ニング方法としてはコア材と同様の材料、 方法 が使用できる。  Subsequently, outermost layers 1e are laminated and formed on both surfaces of the core substrate 1d as shown in FIG. The same material and method as the core material can be used for the material of the insulating layer, the drilling method, and the setting method.
最外層の積層 '形成は、 内層材に対し、 両面に絶縁層、 更に導電層を作成し、 パ夕一ニングおよび電気的接続を行えばよい。 いくつかの方法につき具体的に例 を挙げて説明する。  To form the outermost layer, an insulating layer and a conductive layer may be formed on both sides of the inner layer material, and the patterning and electrical connection may be performed. Several methods will be described with specific examples.
いわゆるビルドアヅプ法による場合につき説明する。 上記内層材からなる基板 に絶縁層を形成する。 絶縁層としてはガラスエポキシ系あるいはァラミド樹脂系 などのプリプレグ、 液状あるいはフィルム状の熱可塑あるいは熱硬化性の樹脂組 成物あるいは一般的に樹脂付き銅箔と呼ばれる、 銅箔と絶縁樹脂層を一体化した ものなどが使用できる。  The case of the so-called build-up method will be described. An insulating layer is formed on a substrate made of the above inner layer material. The insulating layer is a prepreg such as glass epoxy or aramide resin, a liquid or film-like thermoplastic or thermosetting resin composition, or a copper foil and an insulating resin layer, which is generally called resin-coated copper foil. Can be used.
絶縁層の形成は例えば以下のように行われる。 図 4 ( a ) に示すように、 上記 コア基板基板 1 dの両面にプリプレグ類 5、 パターン化されていない銅箔 6、 あ るいは図 4 ( b ) に示すように樹脂付き銅箔 7を配置し、 図 5に示すように積層 プレス法によりこれらを一括で積層、 硬化させ、 絶縁層と導電層を一体化したも のを作成する。 あるいは、 図 6に示すように、 上記 ¾¾ 1 d上に液状の組成物を スクリーン印刷、 力一テンコート、 スプレーコートなどの公知慣用の方法で塗布 し、 UV、 電子線、 熱などで硬化させる。 あるいは上記基板上にフィルム状の組 成物をロール、 ラミネートなどの方法で貼り付け、 所定の方法にて硬化させ、 絶 縁層 8を得る。 続いてビアを形成する。 上記の方法で得られた基板の所定の位置にドリル、 レThe formation of the insulating layer is performed, for example, as follows. As shown in Fig. 4 (a), prepregs 5, unpatterned copper foil 6, or resin-coated copper foil 7 as shown in Fig. 4 (b) are provided on both sides of the core substrate 1d. They are arranged, and they are collectively laminated and cured by a lamination press method as shown in Fig. 5, to create an integrated insulating layer and conductive layer. Alternatively, as shown in FIG. 6, a liquid composition is applied onto the above 1d by a known and conventional method such as screen printing, force coating, spray coating, etc., and cured by UV, electron beam, heat, or the like. Alternatively, a film-shaped composition is pasted on the substrate by a method such as roll or lamination, and cured by a predetermined method to obtain an insulating layer 8. Subsequently, a via is formed. Drill and drill at predetermined positions on the substrate obtained by the above method.
—ザ一などを用いてビア 9を形成する。 図 7 ( a ) は絶縁層および導電層として プリプレダ 5と銅箔 6を用いた場合、 同様に図 7 ( b ) は樹脂付き銅箔 7、 図 7 ( c ) は液状あるいはフィルム状の熱可塑あるいは熱硬化性の樹脂組成物 8を用 いた場合について記したものである。 プリプレダ類あるいは樹脂付き銅箔を用い て絶縁層と共に導電層も形成した場合に、 ブラインドビアの形成に広く用いられ ている炭酸ガスレ一ザ一を用いる場合には、 必要に応じてあらかじめ所定の位置 の導電体をエッチングで除く、 いわゆるマスク加工を施してもよい。 — Form a via 9 by using the method described above. Fig. 7 (a) shows the case where the pre-preda 5 and the copper foil 6 are used as the insulating layer and the conductive layer. Similarly, Fig. 7 (b) shows the copper foil 7 with resin, and Fig. 7 (c) shows the liquid or film-like thermoplastic. Alternatively, the case where the thermosetting resin composition 8 is used is described. When a conductive layer is formed together with an insulating layer using a pre-preda or a resin-coated copper foil, if a carbon dioxide laser widely used for forming blind vias is used, A so-called mask process may be performed to remove the conductor by etching.
プリプレグ類あるいは樹脂付き銅箔を用いて絶縁層と共に導電層も形成した場 合は、 例えば図 8 ( a) に示すようにビアに銀、 銅などの導電性粉末を配合した 導電性ペースト 1 0を印刷、 デイスペンスなどの方法で埋め込み、 所定の方法で 硬化させる。 あるいは、 図 8 ( b ) に示すように通常のスルーホールメツキすな わちビア内にメツキ触媒を付与したのちに無電解メヅキを行い、 続いて電解メヅ キを行う方法によってメツキ層 1 1を形成する方法によっても電気的接続は達成 される。液状もしくはフィルム状の組成物を用いて絶縁層を形成した場合は、 図 8 ( c ) に示すように、 例えば銅箔 1 2をプレスし、 絶縁層の外側に導電層を形 成し、 所定の位置をマスク加工した後、 ブラインドビアを導電性ペースト 1 0あ るいはメヅキ層 1 1により導電ィ匕し接続する。 この場合、 先にブラインドビアの 導電化を行っても良い。 また、 図 8 ( d ) に示すように、 絶縁層、 ブラインドビ ァが形成された基板に触媒を付与し、 無電解メツキ処理し、 続いて必要に応じて 電解メヅキ処理することによつて導電層 1 3の形成とブラインドビアの導電化を 一括で行うこともできる。 この場合、 ブラインドビアの導電化は導電性ペースト によっても行うことができる。  When a conductive layer is formed together with an insulating layer using prepregs or resin-coated copper foil, for example, as shown in FIG. 8 (a), a conductive paste containing a conductive powder such as silver or copper in a via is used. Is embedded by printing, dispensing, etc., and cured by a predetermined method. Alternatively, as shown in FIG. 8 (b), a normal through-hole plating, that is, an electroless plating after applying a plating catalyst in the via, followed by an electrolytic plating, is used. The electrical connection can also be achieved by the method of forming. When the insulating layer is formed using a liquid or film-like composition, as shown in FIG. 8 (c), for example, a copper foil 12 is pressed, and a conductive layer is formed outside the insulating layer. After performing the mask processing at the position, the blind via is conductively connected with the conductive paste 10 or the print layer 11 to be connected. In this case, the blind via may be made conductive first. In addition, as shown in FIG. 8 (d), a catalyst is applied to the substrate on which the insulating layer and the blind via are formed, and electroless plating is performed, and then, if necessary, electrolytic plating is performed. The formation of the layer 13 and the conduction of the blind via can also be performed at once. In this case, the blind via can be made conductive by using a conductive paste.
あるいは以下の方法により、 絶縁層と導電層、 電気的接続を一括で行うことも できる。 すなわち、 図 9に示すように、 内層回路 1 d上の所定の場所に導電性ぺ ーストなどを用いて先端のとがった導電性バンプ 1 4を形成した後、 プリプレグ 5と銅箔 6 (図 9 ( a))、 あるいはフィルム状の絶縁体 8と銅箔 6 (図 9 ( b ) )、 または樹脂付き銅箔 7を配置した後にプレス加工を行うこと （図 9 ( c )) に よりとがった導電性バンプ 1 4が絶縁層を貫通し、 導電層との接続を実現する。 なお、 メヅキにより接続されたスル一ホール ¾反を用い、 上記の液状あるいは フィルム状の絶縁材料を使用する場合、 あるいは一旦ビルドァヅプ法により形成 したブラインドビアのある絶縁層上に更に積層する場合には、 穴埋め用のィンキ あるいはメツキ処理によりスルーホールあるいはブラインドビアを埋め、 表面を 平滑ィ匕してもよい。 Alternatively, the insulating layer, the conductive layer, and the electrical connection can be collectively performed by the following method. That is, as shown in FIG. 9, the conductive layer is placed at a predetermined position on the inner layer circuit 1d. After forming conductive bumps 14 with sharp tips using a paste or the like, prepreg 5 and copper foil 6 (Fig. 9 (a)) or film-like insulator 8 and copper foil 6 (Fig. 9 (b) ) Or press processing after placing the resin-coated copper foil 7 (FIG. 9 (c)) allows the sharp conductive bumps 14 to penetrate the insulating layer and realize connection with the conductive layer. In addition, when the above liquid or film-like insulating material is used by using a through-hole film connected by a make-up, or when further laminated on an insulating layer having a blind via once formed by a build-up method, Alternatively, through holes or blind vias may be filled with a filling or filling process for filling holes to smooth the surface.
あるいは、 以下の方法により一括に積層させることもできる。絶縁層としてガ ラスエポキシ系のプリプレダを用いた 4層構造の場合につき説明する。 すなわち、 図 1 0に示すように、 銅張片面ガラスエポキシ基板の基材 1 5側の所定の位置を レーザ一などを用いて穴開け加工する。続いて、 銅箔 1 6を電極として電気メヅ キを行い、 生じた穴をメヅキ 1 7で充填する。 その上に、 低融点の金属バンプ 1 8を引き続きメツキ法により作成する。  Alternatively, they can be collectively laminated by the following method. The case of a four-layer structure using a glass epoxy pre-preda as the insulating layer will be described. That is, as shown in FIG. 10, a predetermined position on the base material 15 side of the copper-clad single-sided glass epoxy substrate is punched using a laser or the like. Subsequently, electric plating is performed using the copper foil 16 as an electrode, and the resulting hole is filled with the plating 17. Then, a low melting point metal bump 18 is continuously formed by the plating method.
銅箔 1 6は図 1 1に示すように所定のパターンにエッチング加工する。 なお、 外部導体の多層基板に平行な導体部分を導体ストリヅプとするとき （多層基板内 シールド線 4の場合） は、 このエッチング加工は不要である。 バンプ側には絶縁 層に用いるものと同様の組成物 1 9を薄く塗布し、 半硬化させておく。 この片面 基板から製造されたものは最外層すなわち第 1層および第 4層となる。  The copper foil 16 is etched into a predetermined pattern as shown in FIG. When the conductor portion of the external conductor parallel to the multilayer substrate is used as the conductor strip (in the case of the shield wire 4 in the multilayer substrate), this etching is not necessary. The same composition 19 as that used for the insulating layer is thinly applied to the bump side and semi-cured. The one manufactured from this single-sided substrate is the outermost layer, that is, the first and fourth layers.
続いて、 図 1 2に示すように、 内層 1 dと図 1 1の最外層を位置あわせし、 プ レス加工することにより半硬ィ匕させた組成物はバンプ部から除かれ、 層間の絶縁 層を形成すると同時にバンプ部は内層の導電体と電気的に接続され、 4層構造を 有するコイルを貫通して信号ラインが配置された多層 ¾反内シールド線 1が製造 される。 この方法を応用することにより、 更なる多層化も容易に行うことができ る o Subsequently, as shown in FIG. 12, the inner layer 1 d and the outermost layer of FIG. 11 are aligned, and the composition that has been semi-hardened by pressing is removed from the bump portion, and the insulation between the layers is removed. Simultaneously with the formation of the layer, the bump portion is electrically connected to the conductor of the inner layer, and a multilayer anti-inner shield line 1 in which a signal line is disposed through a coil having a four-layer structure is manufactured. By applying this method, further multilayering can be easily performed. O
螺旋状のパターンをより密にしたい場合は、 更なる多層化が必要となる。 上記 のいずれの方法を用いても、 更なる多層化が可能である。  In order to make the spiral pattern denser, further multilayering is required. Further multilayering is possible using any of the above methods.
これらの方法を応用することにより、 必要に応じて、 例えば図 1 ( b) に示し た多層コィルで信号ラインをシールドした構造の多層基板内シールド線 2や、 か ご形などの外部導体を有する多層基板内シールド線 3も容易に製造できる。 また、 上記の各種の積層方法で各種基板を製造する際、 所定の位置で上記方法 を応用すれば、 本発明の多層基板内シールド線 1〜 4の構造を含有する電子回路 素子も容易に製造できる。  By applying these methods, if necessary, for example, a shield wire 2 in a multilayer board with a signal line shielded by a multilayer coil as shown in Fig. 1 (b) and an external conductor such as a cage The shield wire 3 in the multilayer substrate can also be easily manufactured. In addition, when various substrates are manufactured by the above-described various lamination methods, if the above method is applied at a predetermined position, an electronic circuit element including the structure of the shield wires 1 to 4 in the multilayer substrate of the present invention can be easily manufactured. it can.
セラミック材料を絶縁材料に用いた場合も、 基本的には有機材料と同様の工程 すなわち、 各層にコイルの一部分および信号ラインを形成し、 これを積層する事 により製造できる。従来から行われている方法である、 グリーンシートへの穴開 け、 導電ペーストによる穴埋めおよびパターン印刷、 積層、 焼成を順次行うこと により本発明のシールド線は形成できる。  Even when a ceramic material is used as an insulating material, it can be manufactured by basically performing the same process as that for an organic material, that is, forming a part of a coil and a signal line in each layer and laminating them. The shielded wire of the present invention can be formed by sequentially performing a method of forming a hole in a green sheet, filling a hole with a conductive paste, printing a pattern, laminating, and firing, which are conventional methods.
半導体基板上に、 基板平面と平行な方向に中心軸を有するコイル或いは外部導 体と導線を同時に形成する過程を以下に示す。 トランジスタを形成し、 更にタン グステンなどで電極部を形成したシリコンウェハの上層いわゆる電極配線層に、 図 1の多層基板内シールド線 1の構造を形成する例を示す。 この方法を応用する ことにより、 夕一ン数、 列 （層） 数、 形成方向などは任意に設定可能である。 まず、 図 1 3に示すように、 トランジスタ、 電極部を形成したシリコンウェハ 2 0上に、 最下層の絶縁層 2 1を形成する。 CVDなどの気相法を用いてシリコ ン酸化膜を形成するか、 近年注目されているポリイミド、 ベンゾシクロブテンな どの有機素材をスピンコート後にボストべ一クする事によって形成できる。 続い て、 図 1 4に示すように必要な箇所の穴 2 2を各種レーザーを用いて形成する。 穴 2 2は、 下層の電極部との電気的接続を行う箇所である。続いて、 図 1 5に示 すように、 導電性パターン 2 3を形成する。 一般的に用いられている、 アルミ二 ゥムのスパッタリング、 あるいは銅の層を C VDなどの気相法、 あるいはメヅキ 法などの湿式法を用いて形成する。 ついで露光、 エッチングしてパターニングす る。 この場合、 先にパ夕一ニングしたレジスト層を形成した後に導電化を行って も良い。 この工程で、 図 1 4に示した工程で穴開けされた穴 2 2も導電ィ匕され、 第一層と第二層の電気的接続がなされる。 なお、 露光工程の前には通常、 物理的 な研磨、 あるいは CMP法と呼ばれる化学的研磨と物理的研磨を組み合わせた方 法などにより、 表面を平坦化する。 The process of simultaneously forming a coil or an external conductor and a conductor having a central axis in a direction parallel to the substrate plane on a semiconductor substrate will be described below. An example in which the structure of the shield line 1 in the multilayer substrate of FIG. 1 is formed on an upper layer, that is, an electrode wiring layer of a silicon wafer in which a transistor is formed and an electrode portion is formed by tungsten or the like. By applying this method, the number of evenings, the number of columns (layers), the direction of formation, etc. can be set arbitrarily. First, as shown in FIG. 13, a lowermost insulating layer 21 is formed on a silicon wafer 20 on which transistors and electrode portions are formed. The silicon oxide film can be formed using a vapor phase method such as CVD, or by spin coating an organic material such as polyimide or benzocyclobutene, which has recently attracted attention, and then performing a post-baking process. Subsequently, as shown in FIG. 14, necessary holes 22 are formed using various lasers. The hole 22 is where electrical connection with the lower electrode portion is made. Then, as shown in Figure 15 Thus, the conductive pattern 23 is formed. A commonly used method is aluminum sputtering, or a copper layer is formed by a vapor phase method such as CVD or a wet method such as a plating method. Then, patterning is performed by exposing and etching. In this case, the conductive layer may be formed after the patterned resist layer is formed. In this step, the hole 22 drilled in the step shown in FIG. 14 is also electrically conductive, and the first layer and the second layer are electrically connected. Before the exposure step, the surface is usually flattened by physical polishing or a combination of chemical polishing and physical polishing called a CMP method.
次に、 図 1 6のように、 第 2の絶縁層 2 4を形成する。 ついで、 図 1 7のよう に、 再び穴開け、 導体パターン形成により第 2層の導電性パターン 2 5を形成す る。 この際、 導線も同時に形成できる。 ついで図 1 8のように第 3の絶縁層 2 6 を前述の方法により形成し、 穴開け、 導電化、 パターニングを施し、 第 3の導電 性パターン 2 7を形成すると共に第二層、 第三層の導通を取る。 この段階で、 図 1に示すような後続が半導体上に形成できる。 この操作を応用すれば、 夕一ン数 の増減、 列 （層）数の増減、 異なる伸長方向を有する複数のシールド線の形成な どが簡便に行える。  Next, as shown in FIG. 16, a second insulating layer 24 is formed. Then, as shown in FIG. 17, a hole is formed again, and a conductive pattern 25 of the second layer is formed by forming a conductive pattern. At this time, a conductive wire can be formed at the same time. Next, as shown in FIG. 18, a third insulating layer 26 is formed by the above-described method, a hole is formed, the conductive layer is patterned, a third conductive pattern 27 is formed, and the second layer and the third layer are formed. Take continuity of the layers. At this stage, the following can be formed on the semiconductor as shown in FIG. By applying this operation, it is possible to easily increase or decrease the number of evenings, increase or decrease the number of rows (layers), or form multiple shield wires having different extending directions.
絶縁層形成、 穴開け後に導電層を形成すると共に線間の電気的接続を行う際、 図 1 9に示すように、 穴部分 （ビアホール） 2 8を導電体 2 9で充填すると、 図 2 0にコイル断面を示すように、 一般的にスタックトビアと呼ばれる構造すなわ ち充填されたビアホール上に再びビアホールのある構造を形成でき、 コィルの辺 を直線にすることができる。  When forming a conductive layer after forming an insulating layer and making a hole and making an electrical connection between wires, as shown in FIG. As shown in the figure, a structure generally called a stacked via, that is, a structure having a via hole can be formed again on a filled via hole, and the side of the coil can be made straight.
シリコンゥェ一ハ 2 0上の多層基板内に所望のシールド線が形成された後に、 そのシリコンゥェ一ハ 2 0とシ一ルド線を含む多層基板とを半導体チップ単位に 切り分ける。  After a desired shield line is formed in the multilayer substrate on the silicon wafer 20, the silicon wafer 20 and the multilayer substrate including the shield line are separated into semiconductor chip units.
なお、 シリコンゥヱ一ハ 2 0にシールド線を内蔵する多層基板を積層させる前 に、 シリコンゥヱーハ 2 0をチップ単位に切り分けておくこともできる。 この場 合、 あらかじめ切り分けた半導体チップの外面に、 上記の工程と同様にして、 シ —ルド線を内蔵する多層基板を積層させるとよい。 Before laminating a multilayer substrate incorporating a shield wire on silicon wafer 20 Alternatively, the silicon wafer 20 can be cut into chips. In this case, a multilayer substrate having a built-in shield line may be laminated on the outer surface of the semiconductor chip cut in advance in the same manner as the above process.
また、 一般的に行われている方法、 すなわち、 ビアホールを導電体で充填しな い方法では、 スタックトビァ構造は形成できない。 その際、 製造されたコイルは、 図 2 1に示すような、 ビアホール接続部が階段状となった断面を有する。 このよ うな構造となっても、 シールド効果には実用上影響しない。  In addition, a stacked via structure cannot be formed by a commonly used method, that is, a method in which a via hole is not filled with a conductor. At that time, the manufactured coil has a cross-section in which the via-hole connection portion is stepped, as shown in FIG. Such a structure has no practical effect on the shielding effect.
以上のように、 本発明の方法により製造された構造は、 信号ラインを、 同時に 形成したコィル又は外部導体で覆う構造とすることにより、 従来のものに比べて 飛躍的に小型化でき、 かつシールド効果が高まる。  As described above, the structure manufactured by the method of the present invention has a structure in which the signal line is covered with a coil or an external conductor formed at the same time. The effect increases.

Claims

請求の範囲 The scope of the claims
1 . 多層基板と一体的に形成されるコイルであって、 当該多層基板に平行な卷 線部分及び当該多層基板に垂直な卷線部分を含むコィルと、 1. a coil formed integrally with the multilayer substrate, the coil including a winding portion parallel to the multilayer substrate and a winding portion perpendicular to the multilayer substrate;
前記多層基板と一体的に形成される導線であって、 前記コイルの内部に形成さ れる導線と、 を有することを特徴とする多層基板内シールド線。  A conductive wire formed integrally with the multilayer substrate, comprising: a conductive wire formed inside the coil.
2 . 前記コイルの単位卷線は、 隣接する他の単位卷線と同じ方向から見た場合 に互いに反対方向に旋回する螺旋状のパターンをそれぞれ有し、 及び  2. Each of the unit windings of the coil has a helical pattern that turns in opposite directions when viewed from the same direction as other adjacent unit windings, and
前記コイルの互いに隣接する単位巻線の組は、 当該螺旋状のパターンの先端同 士又は末端同士において交互に接続されることを特徴とする請求の範囲第 1項に 記載の多層基板内シールド線。  The shield wire according to claim 1, wherein sets of unit windings adjacent to each other of the coil are alternately connected at the leading end or the trailing end of the spiral pattern. .
3 . 前記コイルは、 前記多層基板に平行な卷線部分が、 積層された導電層の一 部として形成され、 前記多層 ¾反に垂直な卷線部分が、 前記絶縁層を介して隣接 する前記導電層間を接続するバンプとして形成されることを特徴とする請求の範 囲第 1又は 2項に記載の多層基板内シールド線。  3. In the coil, a winding portion parallel to the multilayer substrate is formed as a part of a stacked conductive layer, and a winding portion perpendicular to the multilayer substrate is adjacent to the multilayer substrate via the insulating layer. 3. The shielded wire in a multilayer substrate according to claim 1, wherein the shielded wire is formed as a bump connecting the conductive layers.
4 . 前記コイルは、 ビルドアップ工法により、 前記多層基板に平行な卷線部分 が、 積層された導電層の一部として形成され、 前記多層基板に垂直な卷線部分が、 前記絶縁層を通して隣接する前記導電層間を接続するビア或いはスルーホールと して形成されることを特徴とする請求の範囲第 1又は 2項に記載の多層基板内シ ールド線。  4. In the coil, a winding part parallel to the multilayer substrate is formed as a part of a stacked conductive layer by a build-up method, and a winding part perpendicular to the multilayer substrate is adjacent through the insulating layer. 3. The shield line in a multilayer substrate according to claim 1, wherein the shield line is formed as a via or a through hole connecting the conductive layers.
5 . 多層基板と一体的に形成される外部導体であって、 当該多層基板に平行な 導体部分及び当該多層 ¾ί反に垂直な導体部分を含む外部導体と、  5. An external conductor integrally formed with the multilayer substrate, the external conductor including a conductor portion parallel to the multilayer substrate and a conductor portion perpendicular to the multilayer substrate;
前記多層基板と一体的に形成される導線であって、 前記外部導体の内部に形成 される導線と、 を有することを特徴とする多層基板内シールド線。  A conductive wire formed integrally with the multilayer substrate, comprising: a conductive wire formed inside the outer conductor.
6 . 前記外部導体は、 前記多層基板に平行な導体部分が導体ストリップである ことを特徴とする請求の範囲第 5項に記載の多層基板内シールド線。 6. In the outer conductor, a conductor portion parallel to the multilayer substrate is a conductor strip. 6. The shielded wire in a multilayer substrate according to claim 5, wherein:
7 . 前記外部導体は、 前記多層基板に平行な導体部分が、 積層された導電層の —部として形成され、 前記多層基板に垂直な導体部分が、 前記絶縁層を介して隣 接する前記導電層間を接続するバンプとして形成されることを特徴とする請求の 範囲第 5又は 6項に記載の多層基板内シールド線。  7. The outer conductor is formed such that a conductor portion parallel to the multilayer substrate is formed as a negative portion of a stacked conductive layer, and a conductor portion perpendicular to the multilayer substrate is adjacent to the conductive layer via the insulating layer. 7. The shielded wire in a multilayer substrate according to claim 5, wherein the shielded wire is formed as a bump for connecting the shield wire.
8 . 前記外部導体は、 ビルドアヅプ工法により、 前記多層基板に平行な導体部 分が、 積層された導電層の一部として形成され、 前記多層基板に垂直な導体部分 が、 前記絶縁層を通して隣接する前記導電層間を接続するビア或いはスルーホー ルとして形成されることを特徴とする請求の範囲第 5又は 6項に記載の多層基板 内シールド線。  8. In the outer conductor, a conductor portion parallel to the multilayer substrate is formed as a part of a stacked conductive layer by a build-up method, and a conductor portion perpendicular to the multilayer substrate is adjacent through the insulating layer. 7. The shield wire according to claim 5, wherein the shield wire is formed as a via or a through hole connecting the conductive layers.
9 . 請求の範囲第 1乃至 8項のいずれか 1項に記載の多層基板内シールド線を 含む多層 *反が外面に積層されたことを特徴とする半導体チップ。  9. A semiconductor chip having a multilayer structure including the multilayer substrate shield wire according to any one of claims 1 to 8 laminated on an outer surface.
1 0 . 請求の範囲第 1乃至 8項のいずれか 1項に記載の多層基板内シールド線 を含む多層基板上に搭載されたことを特徴とする電子回路素子。  10. An electronic circuit element mounted on a multilayer substrate including the multilayer substrate shield wire according to any one of claims 1 to 8.
1 1 . 多層基板を構成する 1つの絶縁層を形成するステップと、  1 1. forming a single insulating layer that constitutes the multilayer substrate;
前記多層基板に平行なコィルの卷線部分の少なくとも一部を前記多層基板内の 絶縁層上に形成するステヅプと、  Forming at least a part of a winding portion of a coil parallel to the multilayer substrate on an insulating layer in the multilayer substrate;
導線を、 前記コイルの内側に当該コイルと前記絶縁層を介在させて形成するス テツプと、  Forming a conductive wire inside the coil with the coil and the insulating layer interposed;
前記多層基板に平行なコイルの前記卷線部分の少なくとも一部同士を絶縁層間 で電気的に接続する垂直接続部を形成し、 それによつて前記多層基板に垂直なコ ィルの卷線部分の少なくとも一部を形成するステップと、  A vertical connection portion is formed to electrically connect at least some of the winding portions of the coil parallel to the multilayer substrate between insulating layers, thereby forming a winding portion of the coil perpendicular to the multilayer substrate. Forming at least a part of;
絶縁層を形成する前記ステップ、 前記多層基板に平行なコィルの卷線部分の少 なくとも一部を形成する前記ステップ、 及び前記多層基板に垂直なコイルの巻線 部分の少なくとも一部を形成する前記ステツプの少なくともいずれかを、 前記多 層基板に平行なコィルの卷線部分と前記多層 *反に垂直なコィルの卷線部分とで 前記多層基板内に支持される所定のコィルが形成されるまで、 それまでに形成さ れた多層 の部分に対して適宜反復するステップと、 を具備することを特徴と する多層基板内シールド線の製造方法。 The step of forming an insulating layer; the step of forming at least a part of a winding part of a coil parallel to the multilayer substrate; and the forming of at least a part of a winding part of a coil perpendicular to the multilayer substrate. At least one of the steps The multilayer formed up to the predetermined coil supported in the multilayer substrate is formed by the coil winding part parallel to the layer substrate and the multilayer * contrary vertical coil winding part. And a step of appropriately repeating the step of (a).
1 2 . 前記所定のコイルの単位巻線は、 隣接する他の単位卷線と同じ方向から 見た場合に互いに反対方向に旋回する螺旋状のパターンをそれそれ有し、 及び 前記所定のコィルの互いに隣接する単位巻線の組は、 前記螺旋状のパターンの 先端同士又は末端同士において交互に接続されることを特徴とする請求の範囲第 12. The unit windings of the predetermined coil each have a spiral pattern that turns in opposite directions when viewed from the same direction as the other adjacent unit windings, and The sets of unit windings adjacent to each other are connected alternately at the tips or ends of the spiral pattern.
1 1項に記載の多層基板内シールド線の製造方法。 11. The method for manufacturing a shielded wire in a multilayer substrate according to item 1.
1 3 . 多層基板を構成する 1つの絶縁層を形成するステップと、  1 3. A step of forming one insulating layer constituting a multilayer substrate;
前記多層基板に平行な外部導体の導体部分の少なくとも一部を前記多層基板内 の絶縁層上に形成するステヅプと、  Forming at least a part of a conductor portion of an external conductor parallel to the multilayer substrate on an insulating layer in the multilayer substrate;
導線を、 前記外部導体の内側に当該外部導体と前記絶縁層を介在させて形成す るステップと、  Forming a conductive wire inside the outer conductor with the outer conductor and the insulating layer interposed;
前記多層基板に平行な外部導体の前記導体部分の少なくとも一部同士を絶縁層 間で電気的に接続する垂直接続部を形成し、 それによつて前記多層基板に垂直な 外部導体の導体部分の少なくとも一部を形成するステップと、  Forming a vertical connection portion for electrically connecting at least a part of the conductor portions of the external conductor parallel to the multilayer substrate between the insulating layers, thereby forming at least a conductor portion of the external conductor perpendicular to the multilayer substrate; Forming a part;
絶縁層を形成する前記ステヅプ、 前記多層基板に平行な外部導体の導体部分の 少なくとも一部を形成する前記ステップ、 及び前記多層基板に垂直な外部導体の 導体部分の少なくとも一部を形成する前記ステップの少なくともいずれかを、 前 記多層基板に平行な外部導体の導体部分と前記多層基板に垂直な外部導体の導体 部分とで前記多層基板内に支持される所定の外部導体が形成されるまで、 それま でに形成された多層基板の部分に対して適宜反復するステヅプと、 を具備するこ とを特徴とする多層基板内シールド線の製造方法。  The step of forming an insulating layer; the step of forming at least a portion of a conductor portion of an external conductor parallel to the multilayer substrate; and the step of forming at least a portion of a conductor portion of an external conductor perpendicular to the multilayer substrate. Until at least one of the conductor portions of the external conductors parallel to the multilayer substrate and the conductor portions of the external conductors perpendicular to the multilayer substrate forms a predetermined external conductor supported in the multilayer substrate. And a step of appropriately repeating steps of the multilayer substrate formed up to that time.
1 4 . 前記外部導体の多層基板に平行な導体部分は、 導体ストリヅプであるこ とを特徴とする請求の範囲第 1 3項に記載の多層基板内シールド線の製造方法。14. The conductor part of the outer conductor parallel to the multilayer board shall be a conductor strip. 14. The method for manufacturing a shielded wire in a multilayer substrate according to claim 13, wherein:
1 5 . 請求の範囲第 1 1乃至 1 4項のいずれか 1項に記載の多層基板内シール ド線の製造方法のステップを有し、 15. The method according to any one of claims 11 to 14, comprising the steps of:
前記多層基板内シールド線は半導体ゥヱ一八の外面に積層されるものであり、 前記多層基板内シールド線が積層された前記半導体ゥヱーハを半導体チップ単 位に切り分けるステップ、  A step of cutting the semiconductor wafer on which the multilayer substrate shield wire is laminated into semiconductor chip units, wherein the multilayer substrate shield wire is laminated on the outer surface of the semiconductor substrate;
を更に有することを特徴とする、 半導体チップの製造方法。 A method for manufacturing a semiconductor chip, further comprising:
1 6 . 請求の範囲第 1 1乃至 1 4項のいずれか 1項に記載の多層基板内シール ド線の製造方法のステップを有し、  16. The method according to any one of claims 11 to 14, comprising the steps of:
前記多層基板内シールド線は半導体チップの外面に積層されることを特徴とす る、 半導体チップの製造方法。  The method for manufacturing a semiconductor chip, wherein the shield wire in the multilayer substrate is laminated on an outer surface of the semiconductor chip.
1 7 . 請求の範囲第 1 1乃至 1 4項のいずれか 1項に記載の多層基板内シール ド線の製造方法のステヅプを有し、  17. A method for manufacturing a shielded wire in a multilayer substrate according to any one of claims 11 to 14, comprising:
前記多層基板内シールド線を含む多層基板の上に電子回路素子が搭載されるこ . とを特徴とする、 電子回路素子の製造方法。  An electronic circuit element is mounted on a multilayer substrate including the shield wire in the multilayer substrate.
PCT/JP2003/006647 2002-05-29 2003-05-28 Shielding wire in multilayer board, semiconductor chip, electronic circuit element, and method for producing the same WO2003100852A1 (en)

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