JP2010027977A - Semiconductor package and its production process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package and its production process in which a voltage fluctuation in a power source can be reduced even if the packaging density of electrode terminals formed on a semiconductor chip is increased, and wirings can easily be drawn from the electrode terminals. <P>SOLUTION: The semiconductor package incldues a wiring board 50 having an embedded laminated capacitor 10 in which a first external electrode 26a and a second external electrode 26b are formed, and a plurality of electrode terminals 41 of a semiconductor chip 40 are connected to a plurality of electrode pads formed on the wiring board. Some of the plurality of electrode pads are connected with the first external electrode and the second external electrode of the laminated capacitor, and at least some of the plurality of electrode pads arranged outside the electrode pads connected with the first external electrode and the second external electrode among the plurality of electrode pads are connected with some of wiring layers constituting the wiring board through wires 65. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor package incorporating a multilayer capacitor and a method for manufacturing the same.

  In recent years, the operating frequency of semiconductor chips has increased and the current consumption has increased. Accordingly, the operating voltage tends to decrease due to the reduction in power consumption. Therefore, in the power source that supplies power to the semiconductor chip, a large current fluctuation occurs at a higher speed, and it is very difficult to suppress the voltage fluctuation of the power source accompanying the current fluctuation within the allowable value of the power source.

  For this reason, a plurality of chip capacitors are mounted on a semiconductor package on which a semiconductor chip is mounted in order to reduce voltage fluctuations of the power supply. In other words, when the current fluctuates at a high speed, the current is supplied from the chip capacitor to the semiconductor chip by quick charge / discharge to suppress the voltage fluctuation of the power supply.

  Hereinafter, an example of a conventional semiconductor package on which a chip capacitor is mounted will be described with reference to FIG. 1 and the like. FIG. 1 is a cross-sectional view illustrating a conventional semiconductor package. Referring to FIG. 1, the semiconductor package 300 includes a multilayer wiring board 500, a semiconductor chip 400, electrode terminals 410, and an underfill resin layer 420. A support body 510 is provided at the center of the multilayer wiring board 500.

  A first wiring layer 610 a is formed on the first main surface 510 a of the support 510. The support 510 is formed with a through via 640 penetrating from the first main surface 510a to the second main surface 510b. The first wiring layer 610a is electrically connected to a later-described fourth wiring layer 610b via a through via 640. Further, a first insulating layer 520a is formed so as to cover the first wiring layer 610a, and a second wiring layer 620a is formed on the first insulating layer 520a. The first wiring layer 610a and the second wiring layer 620a are electrically connected through a via hole 520x that penetrates the first insulating layer 520a.

  Further, a second insulating layer 530a is formed so as to cover the second wiring layer 620a. A third wiring layer 630a is formed on the second insulating layer 530a. The second wiring layer 620a and the third wiring layer 630a are electrically connected through a via hole 530x that penetrates the second insulating layer 530a.

  Further, a solder resist film 550a having an opening 550x is formed so as to cover the third wiring layer 630a. The portion exposed from the opening 550x of the solder resist film 550a of the third wiring layer 630a functions as an electrode pad (hereinafter, the portion exposed from the opening 550x of the solder resist film 550a of the third wiring layer 630a is the electrode pad 630a). Sometimes). Hereinafter, the surface on which the electrode pad 630a is formed may be referred to as a first main surface of the multilayer wiring board 500.

  A fourth wiring layer 610b is formed on the second main surface 510b of the support 510, and a third insulating layer 520b is formed so as to cover the fourth wiring layer 610b. A fifth wiring layer 620b is formed on the third insulating layer 520b. The fourth wiring layer 610b and the fifth wiring layer 620b are electrically connected through a via hole 520y that penetrates the third insulating layer 520b.

  Further, a fourth insulating layer 530b is formed so as to cover the fifth wiring layer 620b. A sixth wiring layer 630b is formed on the fourth insulating layer 530b. The fifth wiring layer 620b and the sixth wiring layer 630b are electrically connected through a via hole 530y that penetrates the fourth insulating layer 530b.

  Further, a solder resist film 550b having an opening 550y is formed so as to cover the sixth wiring layer 630b. The portion of the sixth wiring layer 630b exposed from the opening 550y of the solder resist film 550b functions as an electrode pad (hereinafter, the portion of the sixth wiring layer 630b exposed from the opening 550y of the solder resist film 550b is the electrode pad 630b). Sometimes). Hereinafter, the surface on which the electrode pad 630b is formed may be referred to as a second main surface of the multilayer wiring board 500.

  Solder bumps 680 are formed on some of the electrode pads 630b. The solder bump 680 functions as an external connection terminal that is electrically connected to a corresponding terminal of the circuit board when the semiconductor package 300 is mounted on the circuit board (not shown). A chip capacitor 100 is mounted on some electrode pads 630b. The electrode pad 630b and the external electrodes 260a and 260b of the chip capacitor 100 are electrically connected.

  The first wiring layer 610a, the second wiring layer 620a, the third wiring layer 630a, the fourth wiring layer 610b, the fifth wiring layer 620b, and the sixth wiring layer 630b include the support 510, the first insulating layer 520a, and the second insulating layer. The layer 530a, the third insulating layer 520b, and the fourth insulating layer 530b are electrically connected through a through via (not shown) penetrating the layer 530a, the third insulating layer 520b, and the fourth insulating layer 530b.

  A semiconductor chip 400 is mounted on the first main surface of the multilayer wiring board 500. The semiconductor chip 400 is obtained by forming a semiconductor integrated circuit (not shown) and electrode pads (not shown) on a thinned semiconductor substrate (not shown) made of silicon or the like. Electrode terminals 410 are formed on electrode pads (not shown) of the semiconductor chip 400.

  Electrode pads (not shown) of the semiconductor chip 400 are electrically connected to corresponding electrode pads 630 a of the multilayer wiring board 500 by electrode terminals 410. The electrode terminal 410 is made of, for example, solder. An underfill resin layer 420 is filled between the semiconductor chip 400 and the solder resist film 550a of the multilayer wiring substrate 500.

  FIG. 2 is an enlarged cross-sectional view illustrating the chip capacitor shown in FIG. Referring to FIG. 2, the chip capacitor 100 includes a dielectric layer 210, a plurality of internal electrodes 220a and 220b, and two external electrodes 260a and 260b.

  Inside the dielectric layer 210, a plurality of internal electrodes 220a and 220b are alternately stacked in the Z direction. The plurality of internal electrodes 220a and 220b are arranged in a region sandwiched between the external electrodes 260a and 260b and substantially perpendicular to 260a1 and 260b1, which are the opposing surfaces of the external electrode 260a and the external electrode 260b. The plurality of internal electrodes 220a are connected to the external electrode 260a, and the plurality of internal electrodes 220b are connected to the external electrode 260b. Thereby, a capacitance is formed between the plurality of internal electrodes 220a and the plurality of internal electrodes 220b.

  A plurality of chip capacitors 100 shown in FIG. 2 are connected between the power supply of the semiconductor chip 400 and a reference potential (GND) in order to reduce voltage fluctuations of the power supply caused by the operating current of the semiconductor chip 400, for example. However, since it is difficult to dispose the chip capacitor 100 in the vicinity of the semiconductor chip 400, the chip capacitor 100 is a surface on the opposite side of the first main surface that is the mounting surface of the semiconductor chip 400 of the multilayer wiring substrate 500. Usually, it is mounted on two main surfaces.

  That is, the power supply and reference potential (GND) of the semiconductor chip 400 are extended to the second main surface of the multilayer wiring board 500 through the wiring layer, via hole, through via, etc., and the chip capacitor 100 is mounted there. On the second main surface of the multilayer wiring board 500, for example, 30 to 50 chip capacitors 100 each having a capacitance of 1 to 10 μF are mounted, and the multilayer wiring board 500 as a whole has a static capacity of 50 to 100 μF. By using the capacitance, voltage fluctuations of the power supply are reduced.

  When the semiconductor chip 400 operates at a high frequency, in order to reduce the voltage fluctuation of the power supply by the chip capacitor 100, it is preferable to arrange the chip capacitor 100 as close as possible to the power supply of the semiconductor chip 400 and the reference potential (GND). However, as described above, the chip capacitor 100 is connected between the power supply of the semiconductor chip 400 and the reference potential (GND) via a wiring layer, a via hole, a through via, and the like. Therefore, it is difficult to reduce the inductance caused by the wiring layer or the like, and when the semiconductor chip 400 operates at a high frequency, there is a limit to reducing the voltage fluctuation of the power source by the chip capacitor 100. This is because when the inductance is increased, the chip capacitor 100 is prevented from being charged and discharged in response to high-speed current fluctuation.

  In order to solve such a problem, a technique for forming a capacitor having the same structure as that shown in FIG. By forming a capacitor inside the multilayer wiring substrate 500, the capacitor can be brought closer to the semiconductor chip 400.

  At this time, the pitch of the external electrodes of the capacitor is made equal to the pitch of the electrode terminals 410 formed on the semiconductor chip 400, and the capacitor is formed immediately below the electrode terminals 410 corresponding to the power supply and reference potential (GND) of the semiconductor chip 400. It is preferable to do. One of the external electrodes of the capacitor is connected to the electrode terminal 410 corresponding to the power source of the semiconductor chip 400, and the other of the external electrodes of the capacitor is connected to the electrode terminal 410 corresponding to the reference potential (GND) of the semiconductor chip 400. Is preferred.

In this way, by forming capacitors in the multilayer wiring board 500 and connecting them as described above, it is possible to reduce the inductance caused by the wiring layers and the like. Even when it operates, the voltage fluctuation of the power source can be reduced (see, for example, Patent Documents 1, 2, and 3).
JP 2001-319992 A JP 2002-260959 A JP 2007-81166 A

  However, as the semiconductor package 300 becomes smaller and thinner, the pitch of the electrode terminals 410 formed on the semiconductor chip 400 is becoming narrower. That is, the electrode terminal 410 is becoming denser. As the pitch of the electrode terminals 410 becomes narrower, the pitch of the external electrodes of the capacitors connected to the electrode terminals 410 also needs to be reduced.

  In the conventional capacitor, the internal electrode is provided in a direction orthogonal to the thickness direction of the wiring board. Therefore, when the pitch of the external electrode of the capacitor is reduced, the area of the internal electrode of the capacitor cannot be increased. When the area of the internal electrode of the capacitor is reduced, the capacitance of the capacitor is reduced in proportion to it, and there is a problem that it is difficult to reduce the voltage fluctuation of the power supply.

  Further, when the density of the electrode terminals 410 is increased, it becomes difficult for the wiring to pass between the adjacent electrode terminals 410, which makes it difficult to draw the wiring from the electrode terminals 410.

  The present invention has been made in view of the above, and even if the electrode terminals formed on the semiconductor chip are densified, it is possible to reduce the voltage fluctuation of the power source of the semiconductor chip, and from the electrode terminals. It is an object of the present invention to provide a semiconductor package from which wiring can be easily pulled out and a manufacturing method thereof.

  In order to achieve the above object, a first invention has a wiring board in which a multilayer capacitor in which a first external electrode and a second external electrode are formed, and a plurality of wiring boards formed on the wiring board. A plurality of electrode terminals of a semiconductor chip connected to the electrode pads of the semiconductor chip, wherein a part of the plurality of electrode pads includes the first external electrode and the second electrode of the multilayer capacitor. At least part of the electrode pads that are connected to the external electrodes and are arranged outside the electrode pads that are connected to the first external electrode and the second external electrode among the plurality of electrode pads. Further, the wiring board is connected to any wiring layer constituting the wiring board through a wire.

  According to a second aspect of the present invention, there is provided a first step of bonding a metal foil provided with a resist film having a predetermined opening on one surface of a wiring board having a cavity, and the metal foil positioned in the cavity A second step of connecting a part of the predetermined opening and any wiring layer constituting the wiring substrate with a wire, and laminating on a part of the predetermined opening of the metal foil located in the cavity A third step of bonding the first external electrode and the second external electrode of the capacitor, and a surface opposite to the surface bonded to the opening of the multilayer capacitor in the peripheral portion of the multilayer capacitor and the wire of the cavity A fourth step of filling an insulating resin so as to be exposed, and a fifth step of patterning the metal foil to form a wiring layer including an electrode pad for connecting a semiconductor chip. is there.

  According to a third aspect of the present invention, there is provided a first step of joining a metal foil to one surface of a wiring board having a cavity portion, a predetermined portion of the metal foil positioned in the cavity portion, and any of the wiring board constituting the wiring board A second step of connecting the wiring layers to each other by a wire, and a first step of bonding the first external electrode and the second external electrode of the multilayer capacitor to a predetermined portion of the metal foil located in the cavity with an insulating resin. A third step, and a fourth step of filling an insulating resin in the peripheral portion of the multilayer capacitor and the wire in the cavity so that a surface opposite to the surface bonded to the opening of the multilayer capacitor is exposed; and And a fifth step of forming a wiring layer including an electrode pad for connecting a semiconductor chip by patterning a metal foil.

  According to the present invention, even when the electrode terminals formed on the semiconductor chip are densified, it is possible to reduce the voltage fluctuation of the power source of the semiconductor chip and to easily draw out the wiring from the electrode terminals. A semiconductor package and a method for manufacturing the same can be provided.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

<Structure of multilayer capacitor according to the present invention>
FIG. 3 is a diagram illustrating a multilayer capacitor according to the present invention. FIG. 3A is a perspective view, and FIG. 3B is an enlarged cross-sectional view illustrating a portion A in FIG.
Referring to FIG. 3, the multilayer capacitor 10 includes a dielectric layer 21, a plurality of first internal electrodes 22a, a plurality of second internal electrodes 22b, a via hole 21x, a via hole 21y, and a plurality of first holes. External electrodes 26a and a plurality of second external electrodes 26b. In FIG. 3B, the width W1 of the first external electrode 26a and the second external electrode 26b is drawn narrower than that in FIG.

  The multilayer capacitor 10 shown in FIG. 3 has a structure having three first external electrodes 26a and three second external electrodes 26b for convenience, but is not limited to this. A structure having the external electrode 26a and the second external electrode 26b can be employed.

In FIG. 3, in the dielectric layer 21, the first external electrodes 26a and the second external electrodes 26b are alternately formed in the X direction at a predetermined cycle. In a region sandwiched between the adjacent first external electrode 26a and second external electrode 26b, a plurality of first internal electrodes 22a and a plurality of second internal electrodes 22b are connected to the first external electrode 26a and the second external electrode 26b. and arranged substantially parallel to 26a ₁ and 26b ₁ are opposing surfaces of the second external electrode 26b.

  The plurality of first internal electrodes 22a are juxtaposed at a predetermined interval in the X direction, and the first internal electrodes 22a are located in a region in the dielectric layer 21 where the second internal electrodes 22b are not formed. They are electrically connected to each other through a penetrating via hole 21y. The plurality of second internal electrodes 22b are juxtaposed at a predetermined interval in the X direction so as to be interleaved with the plurality of first internal electrodes 22a via the dielectric layer 21. The electrodes 22b are electrically connected to each other through a via hole 21x that penetrates a region of the dielectric layer 21 where the first internal electrode 22a is not formed.

  The plurality of first internal electrodes 22a that are electrically connected to each other are further electrically connected to adjacent first external electrodes 26a through via holes 21y. The plurality of second internal electrodes 22b that are electrically connected to each other are further electrically connected to adjacent second external electrodes 26b through via holes 21x. The plurality of first internal electrodes 22 a and the plurality of second internal electrodes 22 b are electrically insulated from each other by the dielectric layer 21.

  Thereby, a capacitance is formed between the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b. In the multilayer capacitor 10, a plurality of first external electrodes 26a and a plurality of second external electrodes 26b, a plurality of first internal electrodes 22a and a plurality of second internal electrodes 22b, and via holes 21x and 21y are excluded. The portion is the dielectric layer 21.

  The first external electrode 26a and the second external electrode 26b are rectangular parallelepiped electrodes, and have a wide surface substantially parallel to the YZ plane. As shown in FIG. 18 to be described later, the width W1 of the first external electrode 26a and the second external electrode 26b is arbitrarily set according to the size of the electrode terminal such as a solder bump formed on the electrode pad of the semiconductor chip. For example, it can be about 50 to 200 μm. The pitch P1 between the first external electrode 26a and the second external electrode 26b adjacent to each other can be arbitrarily determined according to the pitch of the electrode terminals of the semiconductor chip, and can be set to about 80 to 350 μm, for example. As a material of the first external electrode 26a and the second external electrode 26b, for example, Cu or Ni can be used.

  The plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b are rectangular parallelepiped electrodes that are narrower than the first external electrode 26a and the second external electrode 26b, and are substantially parallel to the YZ plane. It has a wide surface. The width W2 of the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b can be, for example, about 1 to 10 μm. The pitch P2 between the adjacent first internal electrode 22a and second internal electrode 22b can be set to about 1 to 10 μm, for example. As a material of the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b, for example, Cu or Ni can be used.

The dielectric layer 21 is made of a material having a high dielectric constant. As a material of the dielectric layer 21, for example, a ceramic material such as SrTiO ₃ (strontium titanate) or BaTiO ₃ (barium titanate) can be used.

The multilayer capacitor 10 is built in the wiring board in the direction shown in FIG. 3, and one of the first external electrode 26a and the second external electrode 26b is an electrode terminal corresponding to the power supply of the semiconductor chip mounted on the wiring board. The other is connected to an electrode terminal corresponding to the reference potential (GND) of the semiconductor chip. At this time, the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b are substantially parallel to the thickness direction of the wiring board (on the surfaces where the first external electrode 26a and the second external electrode 26b face each other). there 26a ₁ and 26b ₁ are arranged substantially parallel to) the thickness direction of the wiring board.

  Thus, in the multilayer capacitor 10 according to the present invention, when incorporated in the wiring board, the plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b are arranged in the thickness direction of the wiring board (described later). Since the pitch of the electrode terminals of the semiconductor chip is narrowed and the pitch of the first external electrode 26a and the second external electrode 26b is correspondingly narrowed, the pitch between the electrode terminals of the semiconductor chip is narrow. The plurality of first internal electrodes 22a and the plurality of second internal electrodes 22b can be expanded in the thickness direction and the depth direction (Z direction and Y direction in FIG. 3) of the wiring board. A large area can be secured. As a result, since the multilayer capacitor 10 can have a sufficient capacity, it is possible to reduce voltage fluctuations of the power source of the semiconductor chip.

<Method for Manufacturing Multilayer Capacitor According to the Present Invention>
A method of manufacturing the multilayer capacitor 10 according to the present invention will be described with reference to FIGS. 4 to 17 are diagrams illustrating the manufacturing process of the multilayer capacitor according to the present invention. 4 to 17, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof may be omitted. First, in the step shown in FIG. 4, a support metal 20 is prepared. For example, Cu or Ni can be used as the material of the support metal 20. Moreover, you may use what plated Cu, Ni, Ag, Pd etc. to these materials.

  The support metal 20 is used as one of external electrodes (first external electrode or second external electrode) when the multilayer capacitor 10 is completed. Accordingly, the support metal 20 has the same thickness as the first external electrode 26a and the second external electrode 26b. The thickness of the support metal 20 can be 50-200 micrometers, for example. In FIG. 4, 20 a and 20 b indicate the first main surface and the second main surface of the support metal 20.

Next, in the step shown in FIG. 5, the dielectric layer 21 is formed on the first main surface 20 a and the second main surface 20 b of the support metal 20. As a material of the dielectric layer 21, for example, a ceramic material such as SrTiO ₃ (strontium titanate) or BaTiO ₃ (barium titanate) can be used. The dielectric layer 21 can be formed by sputtering, for example. Next, in the step shown in FIG. 6, a conductor layer (hereinafter, sometimes referred to as the conductor layer 22 a for convenience) is formed on the dielectric layer 21 as the first internal electrode 22 a. For example, Cu or Ni can be used as the conductor layer 22a. The conductor layer 22a can be formed by, for example, a sputtering method, a CVD method, an electrolytic plating method, or the like. The thickness of the conductor layer 22a can be, for example, about 1 to 10 μm.

  Next, in a step shown in FIG. 7, an opening 22x is formed in the conductor layer 22a. Specifically, for example, a resist film such as a dry film is formed on the conductor layer 22a, and a patterning process is performed on the resist film so as to cover a portion other than the portion where the opening 22x is to be formed. Then, the conductor layer 22a in the portion where the resist film is not formed is removed by etching. Further, the opening 22x is formed by removing the resist film.

  Next, in the step shown in FIG. 8, the dielectric layer 21 is further laminated on the dielectric layer 21 so as to cover the conductor layer 22a. Next, in the step shown in FIG. 9, a via hole 21x is formed in a portion of the dielectric layer 21 where the conductor layer 22a is not formed. The via hole 21x is formed so that the first main surface 20a and the second main surface 20b of the support metal 20 are exposed. The via hole 21x can be formed using, for example, a laser processing method or a plasma etching method.

  Next, in the step shown in FIG. 10, a conductor layer (hereinafter, sometimes referred to as a conductor layer 22b for convenience) is formed in the via hole 21x and on the dielectric layer 21 as the second internal electrode 22b. Thereby, the conductor layer 22b is electrically connected to the support metal 20 via the via hole 21x. Since the material and forming method of the conductor layer 22b are the same as those of the conductor layer 22a, the description thereof is omitted.

  Next, in the step shown in FIG. 11, an opening 22y is formed in the conductor layer 22b. Since the method of forming the opening 22y is the same as that of the opening 22x, description thereof is omitted. Next, in the step shown in FIG. 12, the dielectric layer 21 is further laminated on the dielectric layer 21 so as to cover the conductor layer 22b.

  Next, in the step shown in FIG. 13, a via hole 21y is formed in a portion of the dielectric layer 21 where the conductor layer 22b is not formed. The via hole 21y is formed so that the conductor layer 22a is exposed. The method of forming the via hole 21y is the same as that of the via hole 21x, and thus the description thereof is omitted.

  Thereafter, the structure shown in FIG. 14 is manufactured by repeating the process shown in FIG. 13 from the process shown in FIG. Next, in the step shown in FIG. 15, a conductor layer (hereinafter, sometimes referred to as a conductor layer 26 a for convenience) is formed on the dielectric layer 21 as the first external electrode 26 a. Specifically, a seed layer made of Cu or the like is formed on the dielectric layer 21 by sputtering or the like. Then, the conductor layer 26a is formed by forming, for example, Cu or Ni on the seed layer by an electrolytic plating method using the seed layer as a power feeding layer. The thickness of the seed layer can be set to 1 μm, for example. The thickness of the conductor layer 26a can be about 50-200 micrometers, for example. The conductor layer 26a may be formed only by sputtering.

  Thereafter, the structure shown in FIG. 16 is manufactured by repeating the process shown in FIG. 13 from the process shown in FIG. In FIG. 16, B indicates a position for cutting the structure shown in FIG. 16 (hereinafter referred to as cutting position B). In FIG. 16, reference numeral 26b denotes a conductor layer serving as a second external electrode (hereinafter sometimes referred to as a conductor layer 26b for convenience). The conductor layer 26b has the same structure as the conductor layer 26a, but the conductor layer 26a is connected to the conductor layer 22a via the via hole 21y, and the conductor layer 26b is connected to the conductor layer 22b via the via hole 21x. To do. Next, in the step shown in FIG. 17, the multilayer capacitor 10 is obtained by cutting the structure shown in FIG. 16 at a cutting position B with a dicing blade or the like.

The multilayer capacitor according to the present invention can also be manufactured by the following method. First, a green sheet mainly composed of a ceramic material such as SrTiO ₃ (strontium titanate) or BaTiO ₃ (barium titanate) is prepared. Next, a via hole is formed in the green sheet by a puncher or the like, and a conductive paste is embedded in the via hole, and then the conductive paste is screen-printed to form a conductor layer serving as an internal electrode. Further, a predetermined number of green sheets on which via holes and conductor layers are formed are laminated and thermocompression bonded to produce a laminate. And the multilayer capacitor | condenser which concerns on this invention can be formed by baking a laminated body in a non-oxidizing atmosphere, and cut | disconnecting and dividing | segmenting at a designated position.

<Semiconductor package according to the present invention>
A semiconductor package 30 incorporating the multilayer capacitor 10 according to the present invention will be described with reference to FIG. FIG. 18 is a cross-sectional view illustrating a semiconductor package incorporating a multilayer capacitor according to the present invention. 18, the same components as those in FIG. 3 are denoted by the same reference numerals, and the description thereof may be omitted. Referring to FIG. 18, the semiconductor package 30 includes a semiconductor chip 40, an electrode terminal 41, an underfill resin layer 42, and a wiring substrate 50.

  A hollow portion 50x is provided at the center of the wiring board 50, and the multilayer capacitor 10 according to the present invention is built in the hollow portion 50x. The hollow portion 50x is provided with a conductor wire 65 that connects predetermined wiring layers. An insulating resin 67 is filled in the periphery of the multilayer capacitor 10 and the conductor wire 65 in the cavity 50x.

  The multilayer capacitor 10 is the one shown in FIG. The first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 have the same pitch P1 between the adjacent first external electrode 26a and the second external electrode 26b as the pitch of the adjacent electrode terminals 41 of the semiconductor chip 40 ( (Pitch between adjacent electrode terminals 41a and 41b) P3.

  Of the electrode terminals 41, 41 a is an electrode terminal connected to the power source of the semiconductor chip 40, 41 b is an electrode terminal connected to the reference potential (GND) of the semiconductor chip 40, and 41 c is a signal line of the semiconductor chip 40. The electrode terminal connected to is shown.

  In the wiring substrate 50, a first wiring layer 61a is formed on the first main surface 51a of the support 51, and further, a first insulating layer 52a is formed so as to cover the first wiring layer 61a. A second wiring layer 62a is formed on the first insulating layer 52a. The first wiring layer 61a and the second wiring layer 62a are electrically connected through a first via hole 52x that penetrates the first insulating layer 52a.

  Further, a second insulating layer 53a is formed so as to cover the second wiring layer 62a. A third wiring layer 63a is formed on the second insulating layer 53a. The second wiring layer 62a and the third wiring layer 63a are electrically connected through a second via hole 53x that penetrates the second insulating layer 53a.

  A portion of the third wiring layer 63a formed at a position corresponding to the electrode terminals 41a and 41b of the semiconductor chip 40 and the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 are a conductor layer. 66 is joined. As a material of the conductor layer 66, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used.

  A portion of the third wiring layer 63 a formed at a position corresponding to the electrode terminal 41 c of the semiconductor chip 40 is connected to the electrode terminal 41 of the semiconductor chip 40 of the third wiring layer 63 a that is on the same plane by the conductor wire 65. It is electrically connected to the second wiring layer 62a which is not a part or a different plane.

  Further, a solder resist film 54a having an opening 54x is formed so as to cover the third wiring layer 63a. The portion exposed from the opening 54x of the solder resist film 54a of the third wiring layer 63a functions as an electrode pad (hereinafter, the portion exposed from the opening 54x of the solder resist film 54a of the third wiring layer 63a is the electrode pad 63a. Sometimes). Hereinafter, the surface on which the electrode pad 63a is formed may be referred to as a first main surface of the wiring board 50.

  Here, the conductor wire 65 will be described in detail with reference to FIG. 19 once leaving FIG. FIG. 19 is a cross-sectional view illustrating the form of the conductor wire. As the conductor wire 65, a wire generally used as a bonding wire in the field of semiconductor devices can be used, but it is preferable that the conductor wire 65 can be stably fixed by the insulating resin 67 and has excellent heat dissipation. .

  Specifically, as the conductor wire 65, for example, a wire made of a conductor metal as shown in FIG. 19A, or a wire 65a made of a conductor metal as shown in FIG. The wire 65a covered with 65b, and the wire 65a made of a conductor metal as shown in FIG. 19C is covered with a cover layer 65b made of an insulating material and further formed with a conductor layer 65c (a coaxial structure with the wire 65a as a core). Can be used).

  In particular, in order to avoid crosstalk, a wire 65a made of a conductor metal as shown in FIG. 19C is covered with a covering layer 65b made of an insulating material, and a conductor layer 65c is further formed (the wire 65a is used as a core). It is preferable to use one having a coaxial structure. In this case, as the wire 65a constituting the conductor wire 65, for example, Au, Ag, Cu, Ni, Al, or an alloy thereof can be used.

  As the coating layer 65b constituting the conductor wire 65, for example, a coating layer of an insulating resin such as an epoxy resin or a polyimide resin can be used. When Al is used as the wire 65a, an oxide film may be used as the covering layer 65b. When coating an insulating resin as the coating layer 65b, methods such as electrostatic coating, spray coating, and dip coating can be used.

  As the conductor layer 65c constituting the conductor wire 65, for example, Au, Ag, Cu, Ni, Al, or an alloy thereof can be used, and it is particularly preferable to use Cu. When Cu is used as the conductor layer 65c, the layer can be easily formed by a method such as electroless copper plating or electrolytic copper plating. The conductor layer 65c is preferably electrically connected to a reference potential (GND) in order to obtain a shielding effect. By enhancing the shielding effect, it is possible to reduce crosstalk and EMI noise.

  The size of the conductor wire 65 may be arbitrary, but a conductor 65a is formed by covering a wire 65a made of a conductor metal as shown in FIG. 19C with a covering layer 65b made of an insulating material (wire 65a). ), The outer diameter φ1 of the wire 65a serving as the core can be set to 20 to 40 μm, for example.

  The thickness of the covering layer 65b covering the core wire 65a is, for example, 2 when the conductor wire 65 in which the covering layer 65b is previously formed around the core wire 65a is used and wire bonding is performed. It can be set to ˜8 μm. Further, when the coating layer 65b is formed around the wire 65a after wire bonding of the uncoated wire 65a, the thickness can be set to 10 to 50 μm, for example. The thickness of the covering layer 65b is preferably set to an optimum value depending on the material constituting the covering layer 65b and impedance matching requirements. The thickness of the conductor layer 65c can be 5-30 micrometers, for example.

  In FIG. 19C, the ratio between the outer diameter φ1 of the wire 65a and the inner diameter φ2 of the conductor layer 65c is preferably in the range of approximately 1: 3-6. By setting such a ratio, in addition to avoiding the occurrence of crosstalk, impedance matching can be performed more effectively.

  Returning to FIG. 18 again, a fourth wiring layer 61b is formed on the second main surface 51b of the support 51, and a third insulating layer 52b is formed so as to cover the fourth wiring layer 61b. . A fifth wiring layer 62b is formed on the third insulating layer 52b. The fourth wiring layer 61b and the fifth wiring layer 62b are electrically connected through a third via hole 52y that penetrates the third insulating layer 52b.

  Further, a fourth insulating layer 53b is formed so as to cover the fifth wiring layer 62b. A sixth wiring layer 63b is formed on the fourth insulating layer 53b. The fifth wiring layer 62b and the sixth wiring layer 63b are electrically connected through a fourth via hole 53y that penetrates the fourth insulating layer 53b.

  Further, a solder resist film 54b having an opening 54y is formed so as to cover the sixth wiring layer 63b. The portion exposed from the opening 54y of the solder resist film 54b of the sixth wiring layer 63b functions as an electrode pad (hereinafter, the portion exposed from the opening 54y of the solder resist film 54b of the sixth wiring layer 63b is the electrode pad 63b. Sometimes). Hereinafter, the surface on which the electrode pad 63b is formed may be referred to as a second main surface of the wiring board 50.

  An external connection terminal 68 is formed on the electrode pad 63b. The external connection terminal 68 is, for example, a solder bump. The external connection terminal 68 functions as a connection terminal that is electrically connected to a corresponding terminal of the circuit board when the semiconductor package 30 is mounted on a circuit board (not shown).

  The first wiring layer 61 a and the fourth wiring layer 61 b are electrically connected through a through via 64 that penetrates the support 51.

  A semiconductor chip 40 is mounted on the first main surface of the wiring board 50. The semiconductor chip 40 is obtained by forming a semiconductor integrated circuit (not shown) and electrode pads (not shown) on a thinned semiconductor substrate (not shown) made of silicon or the like. On the electrode pad (not shown) of the semiconductor chip 40, an electrode terminal 41 serving as an electrode is formed. Electrode pads (not shown) of the semiconductor chip 40 are electrically connected to corresponding electrode pads 63a of the wiring board 50 by electrode terminals 41. The electrode terminal 41 is made of, for example, solder. An underfill resin layer 42 is filled between the semiconductor chip 40 and the solder resist film 54 a of the wiring substrate 50.

  FIG. 20 is a bottom view illustrating the positional relationship between the arrangement of the electrode terminals of the semiconductor chip and the multilayer capacitor. FIG. 20A shows only the portion of the semiconductor chip 40 in the semiconductor package 30 shown in FIG. As shown in FIG. 20A, in the semiconductor chip 40, the electrode terminals 41c are arranged in two rows on the outer periphery, and the electrode terminals 41a and 41b are arranged inside thereof. Six electrode terminals 41a and 41b are continuously arranged in the Y direction. The electrode terminals 41a and 41b are alternately arranged in the X direction.

  Note that the number of electrode terminals 41a to 41c is determined for the sake of convenience, and is not limited to this. It is possible to arrange the electrode terminals 41a to 41c in numbers other than those shown here. Further, the arrangement of the electrode terminals 41a to 41c is not limited to that shown in FIG. 20, and may be arranged in a dust shape, for example.

  FIG. 20B schematically shows the positional relationship between the electrode terminals 41 a and 41 b and the multilayer capacitor 10. As shown in FIG. 20B, the multilayer capacitor 10 is disposed directly below the region where the electrode terminals 41a and 41b are disposed. The plurality of first external electrodes 26 a of the multilayer capacitor 10 are electrically connected to electrode terminals 41 a connected to the power source of the semiconductor chip 40, and the plurality of second external electrodes 26 b are reference potentials (GND) of the semiconductor chip 40. It is electrically connected to the electrode terminal 41b connected to the.

  As shown in FIG. 18, a third wiring layer 63 a and a conductor layer 66 are formed between the semiconductor chip 40 and the multilayer capacitor 10. Therefore, the electrode terminals 41a and 41b of the semiconductor chip 40 and the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 are electrically connected via the third wiring layer 63a and the conductor layer 66. .

  Thus, in the multilayer capacitor 10 according to the present invention, the first internal electrode 22a and the second internal electrode 22b are arranged in the thickness direction (Z direction) of the wiring board 50 when incorporated in the wiring board 50. Since the pitches of the electrode terminals 41 of the semiconductor chip 40 are reduced and the pitches of the first external electrodes 26a and the second external electrodes 26b are correspondingly reduced, the first internal electrodes are arranged in parallel. Since the electrode 22a and the second internal electrode 22b can be expanded in the thickness direction and the depth direction (Z direction and Y direction in FIG. 18) of the wiring board 50, a sufficient area can be secured. . As a result, since the multilayer capacitor 10 can have a sufficient capacity, it is possible to reduce the voltage fluctuation of the power source of the semiconductor chip 40.

  For example, as the pitch of the electrode terminals 41 of the semiconductor chip 40 becomes narrower, the width of the region sandwiched between the adjacent first external electrode 26a and second external electrode 26b becomes the first external electrode 26a and Even when the width is smaller than the width W1 (see FIG. 3) of the second external electrode 26b, the multilayer capacitor 10 can have a sufficient capacity.

  In the semiconductor package 30 according to the present invention, the wiring board 50 is provided with the cavity 50x, and the electrode terminal 41c connected to the signal line of the semiconductor chip 40 in the cavity 50x and the arbitrary wiring layer are three-dimensionally provided. Are electrically connected by using a bendable conductor wire 65. As a result, even if the electrode terminal 41c becomes extremely dense, the electrode terminal 41c and an arbitrary wiring layer can be easily connected.

  Further, by using a conductor wire 65 in which a wire 65a made of a conductor metal is covered with a coating layer 65b made of an insulating material and further a conductor layer 65c is formed (having a coaxial structure with the wire 65a as a core). Crosstalk reduction and EMI noise reduction can be realized.

<Method for Manufacturing Semiconductor Package According to the Present Invention>
A method of manufacturing the semiconductor package 30 incorporating the multilayer capacitor 10 according to the present invention will be described with reference to FIGS. 21 to 34 are diagrams illustrating the manufacturing process of the semiconductor package according to the present invention. 21 to 34, the same components as those in FIG. 18 are denoted by the same reference numerals, and the description thereof may be omitted.

  First, in the step shown in FIG. 21, a wiring board 50a having a hollow portion 50x at the center is prepared. FIG. 21A is a cross-sectional view, and FIG. 21B is a perspective view. FIG. 21B shows only the appearance of the wiring board 50a, and the fourth wiring layer 61b and the like are omitted. The wiring board 50a becomes the wiring board 50 shown in FIG. 18 through a series of steps. The wiring board 50a has a support 51 made of an insulating material. On the first main surface 51a of the support 51, the first wiring layer 61a, the second wiring layer 62a, the first insulating layer 52a, the first Two insulating layers 53a, a first via hole 52x, and a second via hole 52y are formed. A fourth wiring layer 61 b is formed on the second main surface 51 b of the support 51. The first wiring layer 61 a and the fourth wiring layer 61 b are electrically connected through a through via 64 that penetrates the support 51.

  Next, in a step shown in FIG. 22, a metal foil 63 to be the third wiring layer 63a is prepared and bonded onto the second insulating layer 53a. Arbitrary adhesive agent, an adhesive sheet, etc. can be used for joining. For example, a copper foil can be used as the metal foil 63, but other metals may be used. On the metal foil 63, a resist film (not shown) having an opening in a portion that becomes the third wiring layer 63a is formed.

  Next, in the step shown in FIG. 23, the position where the metal foil 63 is to be connected to the electrode terminal 41c of the semiconductor chip 40 and the position where the metal foil 63 is not connected to the electrode terminal 41 of the semiconductor chip 40 on the same plane. Alternatively, the second wiring layer 62 a which is a different plane is electrically connected by wire bonding using the conductor wire 65. As the conductor wire 65, a wire 65a made of a conductor metal as shown in FIG. 19C is covered with a coating layer 65b made of an insulating material, and further a conductor layer 65c is formed (a coaxial structure having the wire 65a as a core). Can be used). The material and the like constituting the conductor wire 65 are as described above.

  As an example, a conductor 65a made of a conductive metal as shown in FIG. 19C is covered with a covering layer 65b made of an insulating material, and a conductor layer 65c is formed (having a coaxial structure with the wire 65a as a core). A wire bonding method using the above will be described in detail with reference to FIG.

  FIG. 24 is a diagram illustrating a wire bonding method. Reference numeral 63x denotes an opening (hereinafter referred to as opening 63x) of the resist film corresponding to a position to be connected to the electrode terminal 41c of the semiconductor chip 40 of the metal foil 63. First, as shown in FIG. 24A, one end of a wire 65 a constituting the conductor wire 65 is connected to the opening 63 x of the metal foil 63.

  Next, as shown in FIG. 24B, the surface of the wire 65a connected to the metal foil 63 and the opening 63x are covered with an insulating material to form a coating layer 65b. Next, as shown in FIG. 24C, the covering layer 65b is covered with a conductor metal to form a conductor layer 65c. The conductor layer 65c can be formed by, for example, an electroless plating method or a metal compound thermal decomposition method. In this way, the conductor wire 65 can be wire bonded to the opening 63x of the metal foil 63.

  After completion of the wire bonding, in the step shown in FIG. 25, the multilayer capacitor 10 according to the present invention manufactured in advance by a predetermined manufacturing method is prepared. Then, an opening (not shown) of the resist film corresponding to the position of the metal foil 63 to be connected to the electrode terminals 41a and 41b of the semiconductor chip 40, the corresponding first external electrode 26a of the multilayer capacitor 10, and The second external electrode 26 b is joined by the conductor layer 66.

  Next, in the step shown in FIG. 26, the insulating resin 67 is filled around the multilayer capacitor 10 and the conductor wire 65 in the cavity 50x and cured. The insulating resin 67 is preferably filled in an amount sufficient to completely close the cavity 50x and cover the entire surface of the metal foil 63, the conductor wire 65, and the conductor layer 66. However, the insulating resin 67 is filled so that the upper surface of the insulating resin 67 and the second main surface 51b of the support body 51 are substantially flush with each other, and the side of the multilayer capacitor 10 where the conductor layer 66 is not formed. The surface is formed so as to be exposed from the insulating resin 67. The insulating resin 67 can be formed, for example, by applying a three-component epoxy resin or the like by potting, and curing the resin while maintaining a temperature of 50 to 100 ° C., for example.

  Next, in the step shown in FIG. 27, the fourth wiring layer 61b is coated on the second main surface 51b of the support 51, the insulating resin 67, and the surface exposed from the insulating resin 67 of the multilayer capacitor 10. A third insulating layer 52b is formed. As a material of the third insulating layer 52b, a resin material such as an epoxy resin or a polyimide resin can be used.

  The third insulating layer 52b is formed, for example, by laminating a resin film on the second main surface 51b of the support 51, the insulating resin 67, and the surface exposed from the insulating resin 67 of the multilayer capacitor 10, and then the resin film Can be formed by pressing (pressing) and then heat-treating at a temperature of about 190 ° C. and curing.

  Next, in a step shown in FIG. 28, a third via hole 52y is formed at a predetermined position of the third insulating layer 52b by using a laser processing method, a plasma etching method, or the like. The third via hole 52y is formed so that the first external electrode 26a, the second external electrode 26b, or the fourth wiring layer 61b of the multilayer capacitor 10 is exposed.

  Here, the width of the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 is wider than the outer diameter of the third via hole 52y on the first external electrode 26a and the second external electrode 26b side. Is preferred. If processing deviation does not occur at all in the manufacturing process, the width of the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 is the same as the width of the first external electrode 26a and the second external electrode 26a of the third via hole 52y. It may be equal to the outer diameter on the external electrode 26b side. However, in actuality, since processing deviation occurs, the width of the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 is set to be, for example, equal to or larger than the minimum pad diameter of the interlayer connection of the wiring board 50 in consideration of this. It is preferable.

  Here, the interlayer connection minimum land diameter is the portion of the second wiring layer 62a formed on the opposite side of the external electrode 26a of the first via hole 52x formed on the external electrode 26a of the multilayer capacitor 10 (this portion is referred to as The minimum diameter).

  Alternatively, a method may be used in which a photosensitive resin film is used as the third insulating layer 52b and is patterned by photolithography and the third via hole 52y is formed, or a resin film provided with an opening is patterned by screen printing. Then, a method of forming the third via hole 52y may be used.

  Next, in a step shown in FIG. 29, a fifth wiring layer 62b connected to the fourth wiring layer 61b through the third via hole 52y is formed on the third insulating layer 52b. For example, Cu or the like can be used as the fifth wiring layer 62b. The fifth wiring layer 62b is formed by, for example, a semi-additive method.

  An example in which the fifth wiring layer 62b is formed by a semi-additive method will be described in more detail. First, a Cu seed layer (see FIG. 5) in the third via hole 52y and on the third insulating layer 52b by an electroless plating method or a sputtering method. After forming, a resist film (not shown) having an opening corresponding to the fifth wiring layer 62b is formed. Next, a Cu layer pattern (not shown) is formed in the opening of the resist film by electrolytic plating using the Cu seed layer as a plating power supply layer.

  Subsequently, after removing the resist film, the Cu wiring layer 62b is obtained by etching the Cu seed layer using the Cu layer pattern as a mask. As a method for forming the fifth wiring layer 62b, various methods such as a subtractive method can be used in addition to the semi-additive method described above.

  Next, in the process shown in FIG. 30, the fourth insulating layer 53b and the sixth wiring layer 63b are stacked by repeating the same process as described above. That is, after forming the fourth insulating layer 53b covering the fifth wiring layer 62b, the fourth via hole 53y is formed in the portion of the fourth insulating layer 53b on the fifth wiring layer 62b.

  Further, a sixth wiring layer 63b connected to the fifth wiring layer 62b through the fourth via hole 53y is formed on the fourth insulating layer 53b. For example, Cu or the like can be used as the material of the sixth wiring layer 63b. The sixth wiring layer 63b is formed by, for example, a semi-additive method.

  In this way, a predetermined buildup wiring layer is formed on the second main surface 51b of the support 51. In the present embodiment, three build-up wiring layers (first wiring layer 61a to third wiring layer 63a and fourth wiring layer 61b to on the first main surface 51a and the second main surface 51b of the support 51, respectively. Although the sixth wiring layer 63b) is formed, a build-up wiring layer of n layers (n is an integer of 1 or more) may be formed.

  Next, in a step shown in FIG. 31, the metal foil 63 is patterned to form a third wiring layer 63a. Specifically, a resist film (not shown) is formed on the portion of the metal foil 63 that will become the third wiring layer 63a, and then etching is performed, and the metal in the portion where the resist film (not shown) is not formed. The foil 63 is removed. Then, the third wiring layer 63a can be formed by removing the resist film (not shown). When copper foil is used as the metal foil 63, for example, ferric chloride can be used as an etchant.

  Next, in a step shown in FIG. 32, solder resist films 54a and 54b are formed on the second insulating layer 53a and the fourth insulating layer 53b so as to cover the third wiring layer 63a and the sixth wiring layer 63b. Then, the openings 54x and 54y are formed by exposing and developing the solder resist films 54a and 54b. Thereby, the third wiring layer 63a and the sixth wiring layer 63b are exposed in the openings 54x and 54y of the solder resist films 54a and 54b.

  Next, in the step shown in FIG. 33, for example, a Ni plating layer and an Au plating layer are laminated in this order on the third wiring layer 63a and the sixth wiring layer 63b in the openings 54x and 54y of the solder resist films 54a and 54b. A Ni / Au plating layer or the like (not shown) is formed. Then, external connection terminals 68 are formed on the Ni / Au plating layer or the like formed on the sixth wiring layer 63b in the opening 54y of the solder resist film 54b. The external connection terminal 68 is, for example, a solder bump.

  Next, in the step shown in FIG. 34, the semiconductor chip 40 on which the electrode terminals 41 are formed is prepared. Then, a pre-solder (not shown) is formed on the Ni / Au plating layer formed on the third wiring layer 63a in the opening 54x of the solder resist film 54a. The pre-solder is obtained by applying a solder paste on a Ni / Au plating layer or the like and performing a reflow process. Also, solder balls may be mounted on the Ni / Au plating layer or the like.

  Then, the electrode terminal 41 of the semiconductor chip 40 and the pre-solder formed in the opening 54x of the solder resist film 54a are electrically connected. The electrical connection between the electrode terminal 41 of the semiconductor chip 40 and the pre-solder is performed, for example, by heating to 230 ° C. and melting the solder. In addition, when the electrode terminal 41 of the semiconductor chip 40 is made of solder, the electrode terminal 41 and the pre-solder are melted to become an alloy, and one bump is formed. Next, the underfill resin 42 is filled between the semiconductor chip 40 and the solder resist film 54a, thereby completing the semiconductor package 30 shown in FIG.

<Modification of Semiconductor Package According to the Present Invention>
A semiconductor package 70 that is a modification of the semiconductor package 30 incorporating the multilayer capacitor 10 according to the present invention will be described with reference to FIG. FIG. 35 is a cross-sectional view showing a modification of the semiconductor package incorporating the multilayer capacitor according to the present invention. 35, the same components as those in FIG. 18 are denoted by the same reference numerals, and the description thereof may be omitted. Referring to FIG. 35, in the semiconductor package 70, one surface of the multilayer capacitor 10 and a part of the third wiring layer 63 a are bonded via an adhesive layer 72. The adhesive layer 72 is made of, for example, an epoxy-based adhesive having insulating properties.

  A fifth via hole 73x is provided in a part of the third wiring layer 63a and the adhesive layer 72, and the electrode terminals 41a and 41b of the semiconductor chip 40 and the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 are provided. Are electrically connected through a metal layer 74 formed in the fifth via hole 73x. Since the configuration excluding these is the same as that of the semiconductor package 30 shown in FIG. 18, the description thereof is omitted. The semiconductor package 70 has the same effect as the semiconductor package 30.

<Modification of Manufacturing Method of Semiconductor Package According to the Present Invention>
A method of manufacturing the semiconductor package 70 incorporating the multilayer capacitor 10 according to the present invention will be described with reference to FIGS. 36 to 42 are views showing modifications of the manufacturing process of the semiconductor package according to the present invention. 36 to 42, the same components as those in FIG. 35 are denoted by the same reference numerals, and the description thereof may be omitted.

  First, the structure shown in FIG. 23 is manufactured through the same steps as those shown in FIGS. However, as the metal foil, unlike the metal foil 63, a metal foil 71 having a resist film formed on the surface thereof is used. As the metal foil 71, for example, a copper foil can be used, but other metals may be used.

  Next, in the step shown in FIG. 36, the multilayer capacitor 10 according to the present invention manufactured in advance by a predetermined manufacturing method is prepared. Then, the multilayer capacitor 10 is bonded to the position where the metal foil 71 is to be connected to the electrode terminals 41 a and 41 b of the semiconductor chip 40. The adhesive layer 72 is a layer formed by curing the adhesive. As the adhesive, for example, an epoxy-based semi-cured sheet-like adhesive having insulating properties can be used.

  Next, in the step shown in FIG. 37, the insulating resin 67 is filled around the multilayer capacitor 10 and the conductor wire 65 in the cavity 50x and cured. The insulating resin 67 is preferably filled in a sufficient amount so as to completely close the cavity 50x and cover the metal foil 71 and the conductor wire 65 entirely. However, the insulating resin 67 is filled so that the upper surface of the insulating resin 67 and the second main surface 51b of the support 51 are substantially flush with each other, and the side of the multilayer capacitor 10 where the adhesive layer 72 is not formed. The surface is formed so as to be exposed from the insulating resin 67. The insulating resin 67 can be formed, for example, by applying a three-component epoxy resin or the like by potting and maintaining the temperature at, for example, 50 to 100 ° C. to cure.

  Next, in the step shown in FIG. 38, the fourth wiring layer 61b is covered on the second main surface 51b of the support 51, the insulating resin 67, and the surface exposed from the insulating resin 67 of the multilayer capacitor 10. A third insulating layer 52b is formed. As a material of the third insulating layer 52b, a resin material such as an epoxy resin or a polyimide resin can be used.

  The third insulating layer 52b is formed, for example, by laminating a resin film on the second main surface 51b of the support 51, the insulating resin 67, and the surface exposed from the insulating resin 67 of the multilayer capacitor 10, and then the resin film Can be formed by pressing (pressing) and then heat-treating at a temperature of about 190 ° C. and curing.

  Next, in a step shown in FIG. 39, a third via hole 52y is formed at a predetermined position of the third insulating layer 52b by using a laser processing method, a plasma etching method, or the like. Further, a fifth via hole 73x is formed by using a laser processing method, a plasma etching method, or the like at a position corresponding to the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 of the metal foil 71 and the adhesive layer 72. To do. The third via hole 52y and the fifth via hole 73x are formed so that the first external electrode 26a, the second external electrode 26b, or the fourth wiring layer 61b of the multilayer capacitor 10 is exposed.

  Next, in a step shown in FIG. 40, a fifth wiring layer 62b connected to the fourth wiring layer 61b through the third via hole 52y is formed on the third insulating layer 52b. Further, a metal layer 74 is formed in the fifth via hole 73x. As the fifth wiring layer 62b and the metal layer 74, for example, Cu or the like can be used. The fifth wiring layer 62b and the metal layer 74 are formed by, for example, a semi-additive method.

  Next, in the step shown in FIG. 41, the fourth insulating layer 53b and the sixth wiring layer 63b are stacked by repeating the same steps as described above. That is, after forming the fourth insulating layer 53b covering the fifth wiring layer 62b, the fourth via hole 53y is formed in the portion of the fourth insulating layer 53b on the fifth wiring layer 62b.

  Further, a sixth wiring layer 63b connected to the fifth wiring layer 62b through the fourth via hole 53y is formed on the fourth insulating layer 53b. For example, Cu or the like can be used as the material of the sixth wiring layer 63b. The sixth wiring layer 63b is formed by, for example, a semi-additive method.

  In this way, a predetermined buildup wiring layer is formed on the second main surface 51b of the support 51. In the present embodiment, three build-up wiring layers (first wiring layer 61a to third wiring layer 63a and fourth wiring layer 61b to on the first main surface 51a and the second main surface 51b of the support 51, respectively. Although the sixth wiring layer 63b) is formed, a build-up wiring layer of n layers (n is an integer of 1 or more) may be formed.

  Next, in a step shown in FIG. 42, a third wiring layer 63a is formed. The third wiring layer 63a can be formed by, for example, a semi-additive method again after the metal foil 71 is once removed by etching. In addition, when a copper foil is used as the metal foil 71, for example, ferric chloride can be used as an etchant. Next, the semiconductor package 70 shown in FIG. 35 is completed through steps similar to those shown in FIGS.

  The multilayer capacitor according to the present invention, the semiconductor package incorporating the multilayer capacitor, and the manufacturing method thereof have been described in detail.

  According to the present invention, when the multilayer capacitor 10 is built in the wiring board 50, the first internal electrode 22a and the second internal electrode 22b are substantially parallel (supported) in the thickness direction (Z direction) of the wiring board 50. The pitch of the electrode terminals 41 of the semiconductor chip 40 is narrowed, and the first external electrode 26a and the second external electrode 26a are correspondingly arranged in the first main surface 51a and the second main surface 51b of the body 51. Even if the pitch of the external electrodes 26b is reduced, the first internal electrode 22a and the second internal electrode 22b are in the thickness direction and depth direction of the wiring board 50 (Z direction and Y direction in FIGS. 18 and 35). Therefore, a sufficient area can be ensured. As a result, since the multilayer capacitor 10 can have a sufficient capacity, it is possible to reduce the voltage fluctuation of the power source of the semiconductor chip 40.

  In addition, the connection between the electrode terminal 41a connected to the power source of the semiconductor chip 40 and the electrode terminal 41b connected to the reference potential (GND) and the multilayer capacitor 10 can be minimized, and the parasitic inductance can be kept extremely low. Can do.

  In addition, since the multilayer capacitor 10 is built in the semiconductor package 30 or the semiconductor package 70, the semiconductor package 30 or the semiconductor package 70 can be thinned.

  Further, since it is not necessary to connect the first external electrode 26a and the second external electrode 26b of the multilayer capacitor 10 and the electrode terminals 41a and 41b of the semiconductor chip 40 with solder, it is possible to achieve high connection reliability. it can.

  Further, in the semiconductor package 30 or the semiconductor package 70 according to the present invention, the wiring board 50 is provided with the cavity 50x, and the electrode terminal 41c connected to the signal line of the semiconductor chip 40 and the arbitrary wiring layer in the cavity 50x. Are electrically connected using a three-dimensionally bendable conductor wire 65. As a result, even if the electrode terminal 41c becomes extremely dense, the electrode terminal 41c and an arbitrary wiring layer can be easily connected.

  Further, by using a conductor wire 65 in which a wire 65a made of a conductor metal is covered with a coating layer 65b made of an insulating material and further a conductor layer 65c is formed (having a coaxial structure with the wire 65a as a core). Crosstalk reduction and EMI noise reduction can be realized.

  The preferred embodiment of the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made to the above-described embodiment without departing from the scope of the present invention. And substitutions can be added.

It is sectional drawing which illustrates the conventional semiconductor package. It is sectional drawing which expands and illustrates the chip capacitor shown in FIG. It is a figure which illustrates the multilayer capacitor concerning this invention. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the multilayer capacitor in accordance with the present invention; It is FIG. (The 2) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. FIG. 6 is a diagram (No. 3) illustrating the manufacturing process of the multilayer capacitor in accordance with the invention; FIG. 7 is a diagram (No. 4) illustrating the production process for the multilayer capacitor in accordance with the present invention; FIG. 5 is a diagram (No. 5) illustrating a manufacturing step of the multilayer capacitor in accordance with the present invention; It is FIG. (The 6) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. FIG. 7 is a view (No. 7) illustrating the manufacturing step of the multilayer capacitor according to the invention; It is FIG. (The 8) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (The 9) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (10) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (The 11) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (12) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (13) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is FIG. (The 14) which illustrates the manufacturing process of the multilayer capacitor which concerns on this invention. It is sectional drawing which illustrates the semiconductor package which incorporates the multilayer capacitor concerning this invention. It is sectional drawing which illustrates the form of a conductor wire. It is a bottom view illustrating the positional relationship between the arrangement of the electrode terminals of the semiconductor chip and the multilayer capacitor. It is FIG. (The 1) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 2) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 3) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is a figure which illustrates about the method of wire bonding. It is FIG. (The 4) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. FIG. 10 is a diagram (No. 5) for exemplifying the manufacturing process for the semiconductor package according to the invention; It is FIG. (The 6) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 7) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 8) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (9) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 10) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (The 11) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. FIG. 12 is a view (No. 12) illustrating the manufacturing process of the semiconductor package according to the invention; It is FIG. (The 13) which illustrates the manufacturing process of the semiconductor package which concerns on this invention. It is sectional drawing which shows the modification of the semiconductor package which incorporates the multilayer capacitor concerning this invention. It is a figure (the 1) which shows the modification of the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (2) which shows the modification of the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (3) which shows the modification of the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (4) which shows the modification of the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (5) which shows the modification of the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (6) which shows the modification of the manufacturing process of the semiconductor package which concerns on this invention. It is FIG. (7) which shows the modification of the manufacturing process of the semiconductor package which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Multilayer capacitor 20 Support metal 20a 1st main surface 20b of support metal 20 2nd main surface of support metal 20 21 Dielectric layer 21x, 21y Via hole 22a 1st internal electrode 22b 2nd internal electrode 22x, 22y, 54x, 54y, 63x opening 26a first external electrode 26b second external electrodes 26a _1, 26b ₁ surface 30,70 semiconductor package 40 semiconductor chips 41, 41a, 41b, 41c electrode terminal 42 underfill resin layer 50,50a wiring board 50x cavity 51 support 51a first main surface 51b of support 51 second main surface 52a of support 51 52a first insulating layer 52b third insulating layer 52x first via hole 52y third via hole 53a second insulating layer 53b fourth Insulating layer 53x Second via hole 53y Fourth via hole 54a, 54b Solder Resist film 61a First wiring layer 61b Fourth wiring layer 62a Second wiring layer 62b Fifth wiring layer 63, 71 Metal foil 63a Third wiring layer 63b Sixth wiring layer 64 Through via 65 Conductor wire 65a Wire material 65b Covering layer 65c, 66 Conductor layer 67 Insulating resin 68 External connection terminal 72 Adhesive layer 73x Fifth via hole 74 Metal layer A part B Cutting position P1, P2, P3 Pitch W1, W2 Width φ1, φ2 Diameter

Claims (16)

A wiring board having a built-in multilayer capacitor in which a first external electrode and a second external electrode are formed;
A semiconductor package in which a plurality of electrode terminals of a semiconductor chip are connected to a plurality of electrode pads formed on the wiring board,
A part of the plurality of electrode pads is connected to the first external electrode and the second external electrode of the multilayer capacitor,
Among the plurality of electrode pads, at least a part of the electrode pads arranged outside the electrode pads connected to the first external electrode and the second external electrode are arranged via the wires. A semiconductor package characterized by being connected to any wiring layer constituting a wiring board. The multilayer capacitor and the wire are arranged in a cavity provided in the wiring board,
2. The semiconductor package according to claim 1, wherein a peripheral portion of the multilayer capacitor and the wire in the hollow portion is filled with an insulating resin.   The semiconductor package according to claim 1, wherein the wires are three-dimensionally arranged in the hollow portion.   4. The semiconductor package according to claim 1, wherein the wire has a structure in which a wire made of a conductive metal is covered with a covering layer made of an insulating material and a conductor layer is further formed. 5. The multilayer capacitor includes a plurality of first internal electrodes arranged in parallel at a predetermined interval and connected to each other,
A plurality of second internal electrodes arranged in parallel with each other at a predetermined interval so as to be interleaved with the plurality of first internal electrodes via a dielectric layer;
The first external electrode connected to the plurality of first internal electrodes;
The second external electrode connected to the plurality of second internal electrodes,
The plurality of first internal electrodes and the plurality of second internal electrodes are arranged in a region sandwiched between the first external electrode and the second external electrode, and the first external electrode and the second external electrode. 5. The semiconductor package according to claim 1, wherein the semiconductor package is disposed substantially parallel to the opposing surface of the external electrode.   A plurality of the first external electrodes and the second external electrodes are provided, respectively, and the first external electrodes and the second external electrodes are alternately formed at a predetermined cycle. Item 6. The semiconductor package according to Item 5. The first internal electrodes are connected to each other through a via hole provided in a region where the second internal electrode of the dielectric layer is not formed,
The second internal electrodes are connected to each other through via holes provided in a region of the dielectric layer where the first internal electrodes are not formed. The semiconductor package described.   The width of the region sandwiched between the first external electrode and the second external electrode is narrower than the width of the first external electrode and the second external electrode. A semiconductor package according to any one of the above.   The said 1st internal electrode and the said 2nd internal electrode are arrange | positioned so that it may become substantially parallel to the thickness direction of the said wiring board, The one of Claim 5 thru | or 8 characterized by the above-mentioned. Semiconductor package. Among the plurality of electrode terminals, a plurality of electrode terminals corresponding to the power source of the semiconductor chip and a plurality of electrode terminals corresponding to the reference potential of the semiconductor chip are arranged in parallel at a predetermined pitch,
10. The semiconductor package according to claim 5, wherein the predetermined pitch is equal to a pitch between the first external electrode and the second external electrode adjacent to each other. One of the first external electrode and the second external electrode is connected to a plurality of electrode terminals corresponding to the power source of the semiconductor chip,
11. The other of the first external electrode and the second external electrode is connected to a plurality of electrode terminals corresponding to a reference potential of the semiconductor chip. A semiconductor package according to item. One of the first external electrode and the second external electrode is disposed directly below a plurality of electrode terminals corresponding to the power source of the semiconductor chip,
12. The other of the first external electrode and the second external electrode is disposed directly below a plurality of electrode terminals corresponding to a reference potential of the semiconductor chip. The semiconductor package according to any one of the above. A first step of bonding a metal foil provided with a resist film having a predetermined opening on one surface of a wiring board having a cavity;
A second step of connecting a part of a predetermined opening of the metal foil located in the hollow portion and any wiring layer constituting the wiring board with a wire;
A third step of joining the first external electrode and the second external electrode of the multilayer capacitor to a part of the predetermined opening of the metal foil located in the hollow portion;
A fourth step of filling an insulating resin so that a surface opposite to a surface bonded to the opening of the multilayer capacitor is exposed at a peripheral portion of the multilayer capacitor and the wire in the hollow portion;
A fifth step of patterning the metal foil to form a wiring layer including an electrode pad for connecting a semiconductor chip. A first step of joining a metal foil to one surface of a wiring board having a cavity,
A second step of connecting a predetermined portion of the metal foil located in the hollow portion and any wiring layer constituting the wiring board with a wire;
A third step of bonding the first external electrode and the second external electrode of the multilayer capacitor to a predetermined portion of the metal foil located in the cavity with an insulating resin;
A fourth step of filling an insulating resin so that a surface opposite to a surface bonded to the opening of the multilayer capacitor is exposed at a peripheral portion of the multilayer capacitor and the wire in the hollow portion;
And a fifth step of forming a wiring layer including an electrode pad for connecting a semiconductor chip on the surface on which the metal foil is formed after removing the metal foil.   In the third step, the multilayer capacitor is disposed in the cavity so that the first internal electrode and the second internal electrode of the multilayer capacitor are substantially parallel to the thickness direction of the wiring board. A method for manufacturing a semiconductor package according to claim 13 or 14.   The method further comprises a sixth step of alternately laminating insulating layers and wiring layers on the entire surface of the wiring board on the side where the surface opposite to the surface bonded to the opening of the multilayer capacitor is exposed. The method for manufacturing a semiconductor package according to any one of 13 to 15.

Images